JP2001272651A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a field sequential liquid crystal display device capable of displaying a complete image by performing sufficient writing to each pixel of a liquid crystal display element in each sub-frame, and displaying a color image of excellent quality without color irregularity by equalizing display color density of pixels in each row of the liquid crystal display element. SOLUTION: The liquid crystal display device is configured by connecting source electrodes of a pair of TFTs 6a, 6b with plural pixel electrodes 5 each, connecting a write gate line 12a and a drain line 13a with the gate electrode and drain electrode of one TFT 6a respectively, and connecting a reset gate line 12b and a drain line 13b with the gate electrode and drain electrode of the other TFT 6b. After the display data are written to the pixels of each row and light emission from the backlight is finished, the written state of the pixels in each row is reset once before writing the next display data to the pixels in each row, and thereafter the next display data are written to the pixels in each row, and also the light is emitted from the backlight in each sub-frame after the display data have been written.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field sequential liquid crystal display device.

[0002]

2. Description of the Related Art Recently, a liquid crystal display device for displaying a color image has a liquid crystal element in which a liquid crystal is sandwiched between a pair of substrates having electrodes formed on opposing inner surfaces, and controls transmission of light to form an image. And a backlight that is disposed behind the liquid crystal display element and that sequentially emits light of a plurality of colors toward the liquid crystal display element at a predetermined cycle to display one color image. For each of a plurality of subframes obtained by dividing one frame by the number of colors of light emitted from the backlight, writing display data corresponding to one of the plurality of colors to the liquid crystal display element; Control means for emitting light of a color corresponding to the display data from the backlight, and displaying one color image by combining display of a plurality of colors for each of the plurality of subframes. It has been studied ones.

[0003] This system is generally called a field sequential system, and a conventional field sequential liquid crystal display device emits one color light from the backlight during a subframe for each of the plurality of subframes. In such a state, display data corresponding to the one color is written in the liquid crystal display element.

[0004] In this field sequential liquid crystal display device, since the liquid crystal display element is not provided with a color filter, light is not absorbed by the color filter.
In order to display one color image by synthesizing bright light of a plurality of colors for each of a plurality of subframes obtained by dividing a frame by the number of colors of light emitted from a backlight, a plurality of colors corresponding to a plurality of pixels are displayed. Compared to a liquid crystal display device using a liquid crystal display element provided with a color filter, a bright and high-definition color image can be displayed.

[0005]

By the way, as a liquid crystal display element, a thin film transistor (hereinafter, referred to as TFT) is used.
An active matrix liquid crystal display device using an active element as an active element is used. This active matrix liquid crystal display element supplies a gate signal for turning on the TFT to each of a plurality of gate lines and synchronizes with the gate signals. The write driving is performed by supplying a write data signal corresponding to the display data to each of the plurality of drain lines. Therefore, in order to sufficiently perform writing to each pixel, the drive duty, that is, the selection period of each gate line, is sufficiently charged to the pixel capacitance composed of the pixel electrode, the counter electrode, and the liquid crystal therebetween by the writing voltage. You need to set it up.

However, the above-described field sequential liquid crystal display device writes display data to the liquid crystal display element and writes the display data from the backlight for each of a plurality of subframes obtained by dividing one frame by the number of colors of light emitted from the backlight. Therefore, the liquid crystal display element must be driven with a considerably higher drive duty than a liquid crystal display device using a liquid crystal display element having a plurality of color filters.

Therefore, in this field sequential liquid crystal display device, the selection period of each gate line of the liquid crystal display element is extremely short, and therefore, writing to each pixel (charging of a writing voltage) is performed for each of the subframes during this short period. )
Was completed, and it was difficult to display a complete image.

In addition, as described above, the conventional field-sequential liquid crystal display device emits one color light from the backlight for each of a plurality of sub-frames during the sub-frame period. Since the display data corresponding to one color is written, the light emission time of the pixel in the row of the liquid crystal display element where the writing time is early is long, and the pixel in the row where the writing time is late is long. The light emission time is short, and therefore, there is a difference in the display color density of the pixels in each row, which causes a problem that color unevenness occurs in a displayed color image.

According to the present invention, a complete image is displayed by sufficiently writing to each pixel of the liquid crystal display element for each subframe, and the display color density of the pixels in each row of the liquid crystal display element is made uniform. It is an object of the present invention to provide a field sequential type liquid crystal display device capable of displaying a good quality color image without color unevenness.

[0010]

According to the present invention, there is provided a liquid crystal device having a liquid crystal element sandwiching a liquid crystal between a pair of substrates having electrodes formed on opposing inner surfaces, and displaying an image by controlling light transmission. A display element, a backlight disposed behind the liquid crystal display element, and a backlight for sequentially emitting light of a plurality of colors toward the liquid crystal display element at a predetermined cycle, and one frame for displaying one color image; For each of a plurality of sub-frames divided by the number of colors of light emitted from the backlight, writing of display data corresponding to one of the plurality of colors to the liquid crystal display element; Control means for emitting light of a color corresponding to the display data, and displaying a single color image by combining the display of a plurality of colors for each of the plurality of sub-frames, Serial liquid crystal display device, a plurality of pixel electrodes provided one of the row direction and the column direction on the inner surface of the substrate are arranged in a matrix of the pair of substrates,
A plurality of TFTs arranged in a pair corresponding to the plurality of pixel electrodes, respectively, and a plurality of TFTs each having a source electrode connected to the corresponding pixel electrode; A plurality of first gate lines connected to one of the gate electrodes, and a wiring line corresponding to each of the pixel electrode rows.
A plurality of second gate lines connected to the other gate electrode of the FT; and a plurality of first drains wired in correspondence with the respective pixel electrode columns and connected to one drain electrode of the pair of TFTs. A plurality of second drain lines connected to the other drain electrode of the pair of TFTs, and a plurality of second drain lines connected to the other drain electrode of the pair of TFTs; A control electrode, and the control means controls the one of the plurality of first gate lines of the liquid crystal display element for each of the plurality of subframes.
A write gate signal for turning on the FT is supplied, and the plurality of first drain lines are synchronized with these write gate signals in accordance with display data corresponding to one of the plurality of colors. Writing means for supplying a write data signal, and sequentially writing the display data to the pixels of each row of the liquid crystal display element; and for each of the plurality of subframes, the display data of the display data to the pixels of each row of the liquid crystal display element. A backlight lighting means for emitting light of a color corresponding to the display data from the backlight for a predetermined time after writing, and after ending the emission of the light from the backlight, to a pixel in each row of the liquid crystal display element. Prior to writing the next display data, a reset gate for turning on the other TFT to the second gate line of the liquid crystal display element. A signal is supplied, and a predetermined voltage between a voltage at which the transmittance of the liquid crystal display element is minimized and a voltage at which the transmittance is maximized is supplied to the second drain line in synchronization with the reset gate signal. Reset means for supplying a reset signal for obtaining a voltage of a value and resetting a writing state of the pixels in each row.

That is, in the liquid crystal display device according to the present invention, a liquid crystal display element is provided with a pair of TFTs on each of a plurality of pixel electrodes.
, A first gate line and a drain line for writing display data are connected to a gate electrode and a drain electrode of one of the TFTs, and a gate electrode and a drain electrode of the other TFT are connected to a gate electrode and a drain electrode of the other TFT.
A configuration in which a second gate line and a drain line for resetting the writing of the display data are connected,
Writing display data to the liquid crystal display element for each of a plurality of subframes obtained by dividing one frame for displaying one color image by the number of colors of light emitted from the backlight,
First, a reset gate signal is supplied to the second gate line and a voltage between the voltage at which the transmittance of the liquid crystal display element to the second drain line is minimum and the voltage at which the transmittance is maximum is determined in advance. By supplying a reset signal for obtaining a voltage having a predetermined value, the write state of the pixels in each row of the liquid crystal display element is reset once, and thereafter, the supply of the write gate signal to the first gate line and the supply of the first gate line are performed. Supply of a write data signal to the drain line of the liquid crystal display device, the next display data is written to the pixels of each row of the liquid crystal display element, and the light from the backlight for each of the plurality of subframes is transmitted. The emission is performed after the display data is written in the pixels of each row of the liquid crystal display element.

According to this liquid crystal display device, the writing of the display data to the pixels of each row of the liquid crystal display element for each subframe is performed after the previous writing state is reset by supplying the reset signal. Therefore, the next display data can be written in a short time.

Further, in the liquid crystal display device, when resetting the previous writing state, it is only necessary to recharge the pixel capacitor from the voltage in the previous writing state to the voltage in the reset state. Can be reset in a short time.

The reset of the writing state of the pixels in each row of the liquid crystal display element is performed by simultaneously supplying a reset gate signal to the plurality of second gate lines and synchronizing the reset gate signals with the plurality of second gate lines. In a batch reset by simultaneously supplying the reset signal to the drain lines, a reset gate signal is supplied to each of the plurality of second gate lines, and the plurality of second gate lines are synchronized with the reset gate signal. Sequential reset may be performed by supplying the reset signal to each drain line.

According to the batch reset, the period from the end of the backlight lighting in the previous sub-frame to the start of display data writing in the next sub-frame corresponds to a selection period of one second gate line. It is only necessary to secure a very short reset period.

In the case of the sequential reset, before starting the writing of the display data, the writing state of the pixels of at least the first row of the liquid crystal display element is reset, and then the display is sequentially performed on the pixels of each row of the liquid crystal display element. It is sufficient to sequentially reset the writing state of the pixels in each row before writing the data while writing the data. Therefore, even in this sequential resetting, the display in the next subframe is completed after the backlight is turned on in the previous subframe. It is only necessary to secure an extremely short reset period before the start of data writing.

As described above, in this liquid crystal display device, display data can be written to the pixels in each row of the liquid crystal display element in a short time, and the reset period of the writing state can be an extremely short period. Even if the selection period of each gate line of the liquid crystal display element is extremely short, writing to each pixel of the liquid crystal display element can be sufficiently performed and a complete image can be displayed.

Moreover, in this liquid crystal display device, light is emitted from the backlight for each of the plurality of sub-frames after display data is written to pixels in each row of the liquid crystal display element. Light is emitted for the same amount of time from the pixels in the row where the writing time is early in the rows of the liquid crystal display element and the pixels in the row where the writing time is late, and the display color density of the pixels in each row is equalized. Can be.

Therefore, according to this liquid crystal display device,
By making the display colors of the pixels of each row of the liquid crystal display element uniform, a color image of good quality without color unevenness can be displayed.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS As described above, in a liquid crystal display device of the present invention, a liquid crystal display element is connected to a plurality of pixel electrodes by connecting the source electrodes of a pair of TFTs to one of the TFTs.
A first gate line and a drain line for writing display data are connected to the gate electrode and the drain electrode of the TFT, and a first gate line and a drain electrode for resetting the writing of the display data to the gate electrode and the drain electrode of the other TFT. 2 is connected to the gate line and the drain line, and after the writing of display data to the pixels of each row of the liquid crystal display element and the emission of light from the backlight are completed, the liquid crystal display element is connected to the pixels of each row. Prior to the writing of the next display data, the supply of the reset gate signal to the second gate line and the voltage at which the transmittance of the liquid crystal display element to the second drain line is minimized and the transmittance become By supplying a reset signal for obtaining a voltage of a predetermined value between the maximum voltage and the maximum voltage, the writing of pixels in each row of the liquid crystal display element is performed. The liquid crystal display element is reset once, and then the write gate signal is supplied to the first gate line and the write data signal is supplied to the first drain line. And writing light from the backlight for each of the plurality of sub-frames after writing display data to pixels in each row of the liquid crystal display element. By doing
Writing to each pixel of the liquid crystal display element for each sub-frame is sufficient to display a complete image, and moreover, uniformity of the display colors of the pixels in each row of the liquid crystal display element is uniform so that there is no color unevenness. This makes it possible to display a high quality color image.

In the liquid crystal display device according to the present invention, the liquid crystal display element includes a liquid crystal element in which a ferroelectric liquid crystal or an antiferroelectric liquid crystal is sandwiched between a pair of substrates, and one of the liquid crystal elements and the other outer surface. A pair of polarized lights arranged so that one of the optical axes is oriented toward the average alignment direction of the liquid crystal molecules in the alignment state of the liquid crystal molecules when a write data signal of either the maximum value or the minimum value is applied. And a ferroelectric or antiferroelectric liquid crystal display device having a plate, and the ferroelectric liquid crystal or antiferroelectric liquid crystal can be driven at a higher driving duty because of a quick response to an applied voltage. it can.

In the case where the ferroelectric or antiferroelectric liquid crystal display element is used, the control means controls the plurality of first drain lines of the liquid crystal display element so that the liquid crystal molecules are aligned so as to minimize the transmittance. Writing means for supplying a writing data signal for aligning the liquid crystal molecules in any one of an alignment state between the liquid crystal display element and the liquid crystal molecules. And a reset means for supplying a reset signal for aligning the liquid crystal display element to an alignment state near the middle between the alignment state in which the transmittance of the liquid crystal display element is minimum and the alignment state in which the transmittance is maximum. Desirably, by doing so, the voltage difference between the reset state and the written state is reduced, and the voltage-transmittance characteristic of the ferroelectric or antiferroelectric liquid crystal display element is reduced. By reducing the lysis, it is possible to prevent display flicker due to the hysteresis.

In this case, if the reset signal is different from the potential of the counter electrode in a direction in which an electric field in a direction opposite to the direction in which the ferroelectric liquid crystal or the antiferroelectric liquid crystal exhibits a fast response speed is obtained. It is more preferable that the signal has a given potential. By doing so, writing of the next display data after the reset can be performed with good responsiveness.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a basic configuration diagram of a field sequential liquid crystal display device, and FIG. 2 is a diagram showing a principle of displaying a color image by the liquid crystal display device.

As shown in FIG. 1, the field sequential liquid crystal display device of this embodiment has a liquid crystal display element 1 for controlling transmission of light to display an image, and a plurality of liquid crystal display elements 1 arranged behind the liquid crystal display element 1. A backlight 22 that sequentially emits color light toward the liquid crystal display element 1 at a predetermined cycle;
For each of a plurality of subframes obtained by dividing one frame for displaying one color image by the number of colors of light emitted from the backlight 22, one of the plurality of colors to the liquid crystal display element 1 And control means 23 for writing display data corresponding to the display data and emitting light of a color corresponding to the display data from the backlight 22. The backlight 22 is a surface light source that sequentially emits the light of the plurality of colors from the entire front surface.

In this liquid crystal display device, display data corresponding to the one color is written into the liquid crystal display element 1 for each of the plurality of subframes.
By emitting light of a color corresponding to the display data from 2, a single color image is displayed by combining display of a plurality of colors for each of the plurality of subframes.

In this embodiment, a surface light source for sequentially emitting light of three colors of red, green and blue is used as the backlight 22, and the one frame is divided into three sub-frames. In the first sub-frame of the sub-frames, writing of display data corresponding to red to the liquid crystal display element 1 as shown in FIG.
The red image R is displayed by the emission of the red light from
2B, a green image G is displayed by writing display data corresponding to green into the liquid crystal display element 1 and emitting green light from the backlight 22, as shown in FIG. In the sub-frame, a blue image B is displayed by writing display data corresponding to blue into the liquid crystal display element 1 and emitting blue light from the backlight 22, as shown in FIG.
These red, green, and blue display images R,
One full-color image is displayed by combining G and B.

FIG. 3 is a plan view of an equivalent circuit of a pixel electrode, a TFT, a gate line and a drain line provided on one substrate of the liquid crystal display element, and FIG. 4 is a liquid crystal display element taken along line IV-IV in FIG. FIG.

The liquid crystal display element 1 used in this embodiment is a ferroelectric or antiferroelectric liquid crystal display element, and transparent electrodes 5 and 16 are formed on opposing inner surfaces as shown in FIG. A liquid crystal element 2 having a ferroelectric liquid crystal or an antiferroelectric liquid crystal liquid crystal 19 interposed between a pair of transparent substrates 3 and 4; and a pair of polarizing plates 20 and 21 disposed on one and the other outer surfaces of the liquid crystal element 2. And

The liquid crystal display element 1 is of an active matrix type using a TFT as an active element.
For example, a plurality of transparent pixels arranged in a matrix in a row direction (horizontal direction in FIG. 2) and a column direction (vertical direction in FIG. 2) on an inner surface of a rear substrate 3 which is a substrate on a side opposite to a display observation side. An electrode 5 and a plurality of TFTs 6 arranged in pairs corresponding to the plurality of pixel electrodes 5, respectively.
a, 6b and a plurality of first and second gate lines 12a, 12 wired in correspondence with the respective pixel electrode rows.
b, and a plurality of first and second drain lines 13a and 13b wired in correspondence with the respective pixel electrode columns.

Each of the pair of TFTs 6a and 6b corresponding to each of the plurality of pixel electrodes 5 includes a gate electrode 7 formed on the rear substrate 3 and a substantially entire surface of the rear substrate 3 covering the gate electrode 7. A gate insulating film (transparent film) 8 formed on the substrate and the gate electrode 7 on the gate insulating film 8
And a source electrode 10 and a drain electrode 11 formed on both sides of the i-type semiconductor film 9 via an n-type semiconductor film (not shown). , One of the TFTs (hereinafter referred to as a writing T
An FT 6a is provided in a region outside one side edge of the pixel electrode 5, and the other TFT (hereinafter, reset TF) is provided.
6b is provided in a region outside the other side edge of the pixel electrode 5.

The pair of TFTs 6 a and 6 b are formed in a shape in which the side on which the source electrode 10 is formed and the side on which the drain electrode 11 is formed are reversed, that is, in a shape having the source electrode 10 on the side adjacent to the pixel electrode 5. Have been.

Further, the plurality of pixel electrodes 5 are formed on the gate insulating film 8 and the pair of TFTs
The source electrodes 10 of the pair 6a and 6b respectively
The FTs 6a and 6b are connected to one corresponding pixel electrode 5.

Further, of the first and second gate lines 12a and 12b respectively corresponding to each pixel electrode row, a first gate line (hereinafter referred to as a writing gate line) 12a is connected to each pixel electrode row. The second gate line (hereinafter, referred to as a reset gate line) 12b is arranged in one of the upper and lower regions (the upper region in FIG. 3) of the pixel electrode rows. Is wired to the other area (the lower area in FIG. 3),
The write gate line 12a is connected to the pair of TFTs.
Gate electrode 7 of writing TFT 6a of 6a and 6b
And the reset gate line 12b is connected to the reset TFT 6 of the pair of TFTs 6a and 6b.
b is connected to the gate electrode 7.

The write gate line 12a and the reset gate line 12b are formed integrally with the gate electrode 7 of the write TFT 6a and the gate electrode 7 of the reset TFT 6b on the rear substrate 3, respectively. I have.

Further, of the first and second drain lines 13a and 13b corresponding to the respective pixel electrode columns,
A first drain line (hereinafter, referred to as a writing drain line) 13a is wired to a region where the writing TFT 6a is provided among left and right regions of each pixel electrode row, and a second drain line (hereinafter, referred to as a drain line). The reset drain line 13b is wired to the other region (the lower region in FIG. 3) of the upper and lower regions of each pixel electrode row, and the write drain line 13a is connected to the pair of pixel electrodes. The drain line 11b of the reset TFT 6b is connected to the drain electrode 11 of the reset TFT 6b of the pair of TFTs 6a, 6b.

In this embodiment, as shown in FIG. 4, the plurality of TFTs 6a and 6b are covered with a protective insulating film 14 having openings in regions corresponding to the plurality of pixel electrodes 5, respectively. The write drain line 13a and the reset drain line 13b are wired thereon, and these drain lines 13a and 13b are formed in the contact holes provided in the protective insulating film 14 through the drain electrodes 12 of the write TFT 6a and the reset TFT 6b. To the drain line 13
a and 13b may be formed on the gate insulating film 8 integrally with the drain electrodes 12 of the writing TFT 6a and the reset TFT 6b.

On the other hand, on the inner surface of the other substrate, that is, the front substrate 4 which is a substrate on the display observation side, a transparent film-like single film facing the plurality of pixel electrodes 5 provided on the rear substrate 3 is provided. A counter electrode 17 is provided.

Further, alignment films 17 and 18 are provided on the innermost surfaces of the pair of substrates 3 and 4 so as to cover the plurality of pixel electrodes 5 and the counter electrode 16, respectively. 18 are oriented in directions substantially parallel to each other or slightly obliquely shifted.

The pair of substrates 3 and 4 are joined at their peripheral edges via a frame-shaped sealing material (not shown), and are formed in a region between the substrates 3 and 4 surrounded by the sealing material. A ferroelectric liquid crystal or an antiferroelectric liquid crystal 19 is filled.

One of the pair of polarizing plates 20 and 21 disposed on the outer surface of one of the liquid crystal elements 2 and the other, for example, the rear polarizing plate 20 has an optical axis (transmission axis). Or the absorption axis) of the liquid crystal in the alignment state of the liquid crystal molecules of the ferroelectric liquid crystal or the antiferroelectric liquid crystal 19 when either the maximum or minimum write data signal is applied to the pixel electrode 5. The other front polarizing plate 21 is provided so as to face the average orientation direction of the molecules, and the transmission axis of the other front polarizing plate 21 is provided to be substantially orthogonal to or substantially parallel to the transmission axis of the rear polarizing plate 20.

That is, the liquid crystal display element 1 has a transmittance that becomes maximum or minimum when a write data signal of either the maximum value or the minimum value is applied. The optical axis (transmission axis or absorption axis) is oriented in the average alignment direction of the liquid crystal molecules in the alignment state of the liquid crystal molecules when the minimum write data signal is applied. When the axis is substantially orthogonal to the transmission axis of the one polarizing plate 20,
When the minimum write data signal is applied, the transmittance becomes minimum (black display), and as the write data signal increases, the transmittance increases.

Next, the control means 23 will be described. The control means 23 converts one frame for displaying one color image into the number of colors of light emitted from the backlight 22 (red, green, blue). In each of the three sub-frames divided by the three colors (3 colors), the writing TFTs 6 a
Supply a write gate signal to turn on
In synchronization with these write gate signals, write data signals corresponding to display data corresponding to one of the plurality of colors are supplied to the plurality of write drain lines 13a, respectively, and the liquid crystal display element 1 Writing means for sequentially writing the display data to the pixels of each row, and for each of the plurality of sub-frames, after writing the display data to the pixels of each row of the liquid crystal display element 1, the display data is written from the backlight 22 to the display data. A backlight lighting means for emitting light of a corresponding color for a predetermined time; and after finishing the emission of the light from the backlight 22, prior to writing the next display data to the pixels of each row of the liquid crystal display element 1. A reset gate signal for turning on the reset TFT 6b is supplied to the reset gate line 12b of the liquid crystal display element 1. In both cases, a voltage having a predetermined value between a voltage at which the transmittance of the liquid crystal display element 1 is minimum and a voltage at which the transmittance is maximum is applied to the reset drain line 13b in synchronization with the reset gate signal. And reset means for supplying a reset signal to obtain the write state of the pixels in each row.

As shown in FIG. 1, the control means 23 includes a display driving section 24 for writing display data to the liquid crystal display element 1 and resetting the writing state, and for turning on the backlight 22. And a control unit 26 of the display drive unit 24 and the backlight drive unit 25.

FIG. 5 shows the configuration of the display drive unit 24. The display drive unit 24 supplies the write gate signal to a plurality of write gate lines 12a of the liquid crystal display element 1, and Multiple reset gate lines 1
A gate driver 24G for supplying the reset gate signal to the gate 2b, and a write data signal to a plurality of write drain lines 13a of the liquid crystal display element 1;
The drain driver 24D supplies the reset signal to the plurality of reset drain lines 13b.

In this embodiment, as shown in FIG. 5, a plurality of reset gate lines 12b of the liquid crystal display element 1 are connected in common on the rear substrate 3 of the liquid crystal element 2, and the plurality of reset gate lines 12b are connected. By connecting a predetermined line (one upper reset gate line in FIG. 5) of the reset gate lines 12b to the gate driver 24G, the reset gate signals are collectively transmitted to the plurality of reset gate lines 12b. In addition, a plurality of reset drain lines 13b are connected in common on the rear substrate 3, and a predetermined line of the plurality of reset drain lines 13b (one right end in FIG. 5). By connecting a reset drain line to the drain driver 24D, the reset signal is transmitted to the plurality of reset lines. It is to be supplied in bulk to use drain line 13b.

Therefore, in the liquid crystal display element 1, the number of gate lines and the number of drain lines are respectively set to the reset gate line 12b and the reset drain line 13
The number of gate driver connection terminals and the number of drain driver connection terminals are twice the number of the write gate lines 12a and the number of the reset gate lines 12b, respectively. The number obtained by adding the number of predetermined lines (one in FIG. 5), the number of the drain lines for writing 13a, and the number of the predetermined lines in the drain line for reset 13b (one in FIG. 5)
And therefore, the gate driver 2
The 4G and the drain driver 24D may have a small number of output terminals.

FIG. 6 shows a write gate signal and a write data signal supplied from the gate driver 24G to the liquid crystal display element 1, and a reset gate signal supplied from the drain driver 24D to the liquid crystal display element 1. 3 shows a reset signal and a backlight lighting signal supplied from the backlight driving unit 25 to the backlight 22.

In FIG. 6, G1, G2,.
Row, 2nd row ... Gate line 1 for writing in the last row (n rows)
The write gate signal D supplied to each of 2b is
Drain line 13 for writing in one of first to last columns
This is a write data signal supplied to a.

The write gate signals G1, G2... Gn
Is defined for each writing period of the first, second, and third subframes obtained by dividing one frame for displaying one color image by the number of colors of red, green, and blue light emitted from the backlight 22. The write data signal D is a signal for turning on the write TFT 6a during the selection period of each write gate line 12b, and the write data signal D is the write gate signals G1, G2.
A signal that becomes a potential corresponding to the gray scale of display data corresponding to one of the three colors of red, green, and blue in synchronization with Gn.

The write data signal D is a signal whose potential changes within a range of ± 5 V with respect to the potential of the counter electrode 16, for example, and the transmittance of the ferroelectric or antiferroelectric liquid crystal display element 1 Changes according to the potential of the write data signal D supplied to the pixel electrode 5 via the write TFT 6a. For example, when a write data signal of -5V with respect to the potential of the counter electrode 16 is supplied. The transmittance becomes maximum, and the transmittance becomes minimum when a + 5V write data signal is supplied.

In FIG. 6, PG is a reset gate signal supplied collectively to a plurality of reset gate lines 12b, and PD is a reset signal supplied collectively to a plurality of reset drain lines 13b. It is.

The reset gate signal PG is a signal for turning on the reset TFT 6b in each reset period of the first, second, and third subframes (collectively selecting a plurality of reset gate lines 12b). And the reset signal PD is the reset gate signal PG
And a potential signal that is synchronized with the voltage at which a voltage having a predetermined value between the voltage at which the transmittance of the liquid crystal display element 1 becomes minimum and the voltage at which the transmittance becomes maximum is obtained. The reset signal PD is preferably a signal having a potential at which a voltage at which the transmittance has a value substantially intermediate between the maximum transmittance and the minimum transmittance is obtained.

As described above, the liquid crystal display element 1 has a ferroelectric or antiferroelectric property whose transmittance becomes maximum or minimum when a write data signal of either the maximum value or the minimum value is applied. Since the write data signal is a signal whose potential changes within a range of ± 5 V with respect to the potential of the counter electrode 16 as described above, the transmittance of the intermediate value can be obtained. The reset signal PD is a signal having a potential near the potential of the counter electrode 16 (for example, 0 V).

Further, in FIG. 6, BL is a backlight lighting signal supplied to the backlight 22. The backlight lighting signal BL is generated by the first, second, and third signals.
Is a signal for turning on the backlight 22 for each backlight lighting period of each sub-frame, and the backlight 22 emits one of red, green, and blue light during the backlight lighting period of the first sub-frame. A color, for example, red light is emitted, and another color, for example, green light is emitted during the backlight lighting period of the second sub-frame. The other light is emitted during the backlight lighting period of the third sub-frame. Emit a color, for example, blue light.

In this embodiment, as shown in FIG. 6, the initial state of each of the first, second, and third sub-frames is set at a time, and the writing state of the pixels in each row of the liquid crystal display element 1 is collectively determined. A reset period for resetting, and after the reset period of each sub-frame, writing of display data corresponding to one of the red, green, and blue colors to pixels of each row of the liquid crystal display element 1 is performed. While securing a writing period for sequentially writing, at the end of each sub-frame,
A backlight lighting period in which light of a color corresponding to the display data is emitted from the backlight 22 is secured.

If the lighting timing of the backlight 22 overlaps within the writing period, the display of the pixels which are in the writing state before the backlight is turned on and the pixels which have been changed from the reset state to the writing state after the backlight is turned on are displayed. If there is a difference in color density and the timing of turning off the backlight 22 overlaps with the next sub-frame, the display color of the previous sub-frame affects the display color of the next sub-frame, causing color mixing. .

Therefore, in this embodiment, the backlight lighting period is set slightly shorter than the period from the end of the writing period to the end of the subframe, and after the writing to all the pixels of the liquid crystal display element is completed. While taking a little extra time to light the backlight 22,
The backlight 22 slightly before the end of the subframe.
Are turned off, the display colors of the pixels in each row are balanced, and the color mixture with the display color of the next sub-frame is eliminated.

In this liquid crystal display device, the liquid crystal display element 1 is
Source electrodes 10 of a pair of writing and resetting TFTs 6a and 6b are connected to a plurality of pixel electrodes 5, respectively, and a writing gate line 12a and a drain line 13a are connected to a gate electrode 7 and a drain electrode 11 of the writing TFT 6a. The reset gate line 1 is connected to the gate electrode 7 and the drain electrode 11 of the reset TFT 6b.
2b and the drain line 13b are connected,
Writing of display data to the liquid crystal display element 1 for each of three sub-frames obtained by dividing one frame for displaying one color image by the number of colors of red, green, and blue light emitted from the backlight 22 includes: First, supply of the reset gate signal PG to the plurality of reset gate lines 12b and reset signal P to the plurality of reset drain lines 13b
By supplying D, the write state of the pixels in each row of the liquid crystal display element 1 is once reset, and thereafter, the write gate signals G1, G2,.
Supply of Gn and a plurality of write drain lines 13a
By supplying the write data signal D to the pixels, the next display data is written to the pixels of each row of the liquid crystal display element 1 and the light from the backlight 22 for each of the plurality of sub-frames is written. The emission is performed after the display data is written into the pixels of each row of the liquid crystal display element 1.

According to this liquid crystal display device, the writing of the display data to the pixels of each row of the liquid crystal display element 1 for each of the sub-frames is performed by changing the previous writing state to the reset signal P.
Since the reset operation is performed after the supply of D, the next display data can be written in a short time.

That is, for example, the previous writing state is a state in which a pixel capacitance composed of the pixel electrode 5, the counter electrode 16 and the liquid crystal 19 therebetween is charged with a voltage that minimizes the transmittance, and the next writing state is performed. When the pixel capacitance is charged with a voltage at which the transmittance becomes maximum, if the next writing is performed without performing the reset, the pixel capacitance is changed from the voltage at which the transmittance becomes minimum to the transmittance at which the transmittance becomes minimum. It takes a long time to write because it must be recharged to the maximum voltage.

In this respect, the liquid crystal display device changes the writing state before the pixels in each row of the liquid crystal display element 1 by the liquid crystal display element 1.
Is reset by supplying a reset signal PD for obtaining a voltage having a predetermined value between the voltage at which the transmittance becomes minimum and the voltage at which the transmittance becomes maximum, and then the next writing is performed. Therefore, for example, as described above, the previous writing state is a state in which the pixel capacitance is charged with a voltage that minimizes the transmittance, and in the next writing, the pixel capacitance is charged with the voltage that maximizes the transmittance. In the following writing, the next writing is performed by changing the pixel capacitance from the voltage in the reset state (a voltage having a predetermined value between a voltage at which the transmittance becomes minimum and a voltage at which the transmittance becomes maximum). It is only necessary to recharge to the voltage at which the transmittance becomes maximum, and therefore, writing can be performed in a short time.

Also, in this liquid crystal display device, when resetting the previous write state, it is only necessary to recharge the pixel capacitor from the voltage in the previous write state to the voltage in the reset state. Can be reset in a short time.

In this embodiment, as described above, the reset of the writing state of the pixels in each row of the liquid crystal display element 1 is performed by simultaneously supplying a reset gate signal PG to the plurality of reset gate lines 12b. The reset signal PD is simultaneously supplied to the plurality of reset drain lines 13b in synchronization with the reset gate signal PG so that the reset signal PD is simultaneously supplied. In order to reset the write state of the pixels of the row at a time, one reset gate line 13a is connected between the end of backlight lighting in the previous subframe and the start of display data writing in the next subframe. It is only necessary to secure an extremely short reset period corresponding to the selection period.

In the write period, the selection period of each write gate line 12a and the reset period are respectively the pixel capacity of each pixel and the gate lines 12a, 1a.
The resistance is determined by the electrical resistance of the drain line 2b and the drain lines 13a and 13b, and can be shortened by reducing the resistance value of each line. In this embodiment, the selection period of each of the write gate lines 12a and the reset period are each set to 1 for a margin.
It is set to 60 μs.

On the other hand, the driving frequency per frame for causing the liquid crystal display device to perform a display in which the human eyes do not feel flickering is 50 Hz or more (one frame period is 20 Hz).
msec or less), and the field sequential liquid crystal display element of this embodiment divides one frame into first, second, and third sub-frames, and each of the sub-frames includes red, green, and blue sub-frames. Since an image is displayed, if the driving frequency per sub-frame is 150 Hz or more, that is, if one sub-frame period is about 6.6 msec or less, flicker-free display can be obtained.

Therefore, in this liquid crystal display device, the sub-frame period of about 6.6 ms may be allocated to the reset period, the writing period, and the backlight lighting period.

For example, the liquid crystal display element 1 has 220 rows ×
In the case of a vertically long screen of 35200 pixels in 160 columns, in this embodiment, the selection period of each writing gate line 12a is set to 160 μsec as described above, and all the writing gate lines 12a are sequentially selected. Is set to 160 μs × 220 = 3.52 msec.

In this embodiment, since the reset period before the write period is set to 160 μsec,
At the end of the subframe, a period obtained by subtracting the reset period (160 μsec) and the writing period (3.52 msec) from the subframe period (about 6.6 msec) is used as a backlight lighting period. Can be.

During the backlight lighting period, as described above, the display colors of the pixels in each row are balanced and the display colors of the next sub-frame are not mixed. After writing to all the pixels is completed, the backlight 22 is turned on with a slight margin time, and the backlight 22 is turned off slightly before the end of the subframe. Is about 3 msec when the margin time is 30 μsec to 40 μsec.

The backlight lighting period is about 3 hours.
The time may be shorter than m seconds, and even in that case, by adjusting the luminance of the light emitted from the backlight 22, the red, green, and blue images of each subframe can be displayed with sufficient luminance.

As described above, in this liquid crystal display device, display data can be written to the pixels of each row of the liquid crystal display element 1 in a short time, and the reset period of the written state can be extremely short. Therefore, even if the selection period of each gate line of the liquid crystal display element is extremely short, writing to each pixel of the liquid crystal display element can be sufficiently performed, and a complete image can be displayed.

Further, this liquid crystal display device emits light from the backlight 22 for each of the plurality of sub-frames.
Since the writing is performed after the display data is written to the pixels of each row of the liquid crystal display element 1, the liquid crystal display element 1
In each row, light is emitted for the same amount of time from the pixels in the row with the earlier writing time and the pixels in the row with the later writing time, and the display colors of the pixels in each row can be made uniform.

Therefore, according to this liquid crystal display device,
By making the display colors of the pixels in each row of the liquid crystal display element 1 uniform, a color image of good quality without color unevenness can be displayed.

Further, in this liquid crystal display device, as the liquid crystal display element 1, a liquid crystal element 2 in which a ferroelectric liquid crystal or an antiferroelectric liquid crystal 19 is sandwiched between a pair of substrates 3 and 4, and one of the liquid crystal elements 2 On the other outer surface, one of the optical axes is directed toward the average alignment direction of the liquid crystal molecules in the alignment state of the liquid crystal molecules when a write data signal of either the maximum value or the minimum value is applied. A ferroelectric or antiferroelectric liquid crystal display element having a pair of polarizing plates 20 and 21 disposed is used. The ferroelectric liquid crystal or antiferroelectric liquid crystal 19 has a response response to an applied voltage. Since it is fast, it can be driven with a higher drive duty.

However, since the ferroelectric or antiferroelectric liquid crystal display element 1 has a hysteresis in the voltage-transmittance characteristic, it is necessary to prevent the display from flickering due to the hysteresis.

Therefore, in this embodiment, as described above, the control means 23 controls the plurality of writing drain lines 13a of the liquid crystal display element 1 so that the liquid crystal molecules are aligned with the alignment state in which the transmittance is minimized. The liquid crystal molecules are supplied to writing means for supplying a writing data signal D for aligning the liquid crystal molecules to any one of the alignment states between the transmittance maximum state and the plurality of reset drain lines 13b of the liquid crystal display element 1. Reset means for supplying a reset signal for aligning the liquid crystal display element 1 to an alignment state near an intermediate between an alignment state in which the transmittance of the liquid crystal display element is minimum and an alignment state in which the transmittance is maximum. By doing so, the voltage difference between the reset state and the write state is reduced, and the voltage-transmittance of the ferroelectric or antiferroelectric liquid crystal display element 1 is reduced. To reduce the sexual hysteresis, it is possible to prevent display flicker due to the hysteresis.

As described above, the reset signal PD is preferably a signal having a potential near the potential of the counter electrode 16, but the ferroelectric liquid crystal or the antiferroelectric liquid crystal of the ferroelectric or antiferroelectric liquid crystal display element 1 is preferably used. The response speed of the ferroelectric liquid crystal 19 is
Since the reset signal PD is different depending on the direction of the electric field applied between the pixel electrode 5 and the counter electrode 16, the reset signal PD is close to the potential of the counter electrode 16, and moreover, the reset signal PD is higher than the potential of the counter electrode 16. It is more preferable that the potential of the antiferroelectric liquid crystal 19 is a signal having a potential different from a direction in which an electric field in a direction opposite to the direction in which the antiferroelectric liquid crystal 19 exhibits a high response speed is obtained.
By doing so, writing of the next display data after the reset can be performed with good responsiveness.

That is, the electric field when the potential of the pixel electrode 5 (the potential of the write data signal supplied to the pixel electrode 5 via the writing TFT 6a) is higher than the potential of the counter electrode 16 is defined as + electric field. The potential of the electrode 5 is equal to the counter electrode 1
Assuming that the electric field when the electric field is lower than the electric potential of No. 6 is a negative electric field, the ferroelectric liquid crystal or the antiferroelectric liquid crystal 19 has a larger electric field than when the applied electric field is one of the positive electric field and the negative electric field.
The other electric field shows a slightly faster response speed.

The difference in response speed depending on the direction of the applied electric field is determined by the difference between the ferroelectric liquid crystal or antiferroelectric liquid crystal 19 and the alignment film 1.
It is determined by the interaction with the alignment films 7 and 18, the thickness of the alignment films 17 and 18, the alignment regulating force, and the like.

Therefore, for example, when the response speed of the ferroelectric liquid crystal or the antiferroelectric liquid crystal 19 is higher when the applied electric field is − electric field than when the applied electric field is + electric field,
The potential of the reset signal PD is set to a potential slightly higher than the potential of the counter electrode 16, and the response speed of the ferroelectric liquid crystal or the antiferroelectric liquid crystal 19 is higher than when the applied electric field is-electric field. In the case where the voltage is also faster when the electric field is positive, the potential of the reset signal PD is changed to
Ideally, the potential is set to be slightly lower than the potential of.

By setting the potential of the reset signal PD in this way, the writing time by supplying a writing data signal of a potential in the direction in which the response speed of the liquid crystal 19 is slower than the potential of the reset signal PD is shortened. Writing of the next display data after reset can be performed with good responsiveness.

In the above embodiment, the reset period is secured at the beginning of each subframe. However, the reset period may be secured after the backlight lighting period of each subframe.

In the above embodiment, the writing state of the pixels in each row of the liquid crystal display element 1 is reset collectively. However, the resetting of the writing state is performed by resetting the reset gate lines 12b respectively. A reset signal may be supplied by supplying a reset gate signal to each of the plurality of reset drain lines 13b in synchronization with the reset gate signal.

In the case of the sequential reset, before starting the writing of the display data, the writing state of the pixels of at least the first row of the liquid crystal display element 1 is reset, and thereafter, the display is sequentially performed on the pixels of each row of the liquid crystal display element 1. It is sufficient to sequentially reset the writing state of the pixels in each row before writing the data while writing the data. Therefore, even in this sequential resetting, the display in the next subframe is completed after the backlight is turned on in the previous subframe. It is only necessary to secure an extremely short reset period before the start of data writing.

That is, the sequential reset may be reset for each row or reset for several rows (preferably 2 to 5 rows). In the case of resetting for each row, reset of the first row is performed in the next sub-row. Since it is sufficient to perform the operation before the start of display data writing in the frame, the selection period of one resetting gate line 12b is between the end of backlight lighting in the previous subframe and the start of display data writing in the next subframe. It is only necessary to secure a very short reset period corresponding to.

When the sequential reset is performed for every several rows, the first few rows may be reset before the start of display data writing in the next subframe. It is only necessary to secure an extremely short reset period corresponding to a period in which several reset gate lines 12b are sequentially selected from the end of light lighting to before the start of display data writing in the next subframe.

[0088]

According to the liquid crystal display device of the present invention, a liquid crystal display element has a plurality of pixel electrodes each connected to a source electrode of a pair of TFTs, and display data is written to a gate electrode and a drain electrode of one of the TFTs. The first to do
And a second gate line and a drain line for resetting the writing of the display data are connected to the gate electrode and the drain electrode of the other TFT, respectively. After the writing of the display data to the pixels of each row and the emission of light from the backlight are completed, prior to the writing of the next display data to the pixels of each row of the liquid crystal display element, the second gate line is connected to the second gate line. And a reset for obtaining a voltage having a predetermined value between a voltage at which the transmittance of the liquid crystal display element to the second drain line is minimized and a voltage at which the transmittance is maximized. By the supply of the signal, the writing state of the pixels in each row of the liquid crystal display element is once reset, and thereafter, the writing state to the first gate line is reset. And by supplying the next display data to the pixels of each row of the liquid crystal display element by supplying a write signal to the first drain line and supplying the write data signal to the first drain line. Since light is emitted from the backlight for each sub-frame after display data is written to pixels in each row of the liquid crystal display element, the light is emitted to each pixel of the liquid crystal display element for each subframe. A sufficient image can be displayed by sufficiently writing, and a color image of good quality without color unevenness can be displayed by equalizing the display colors of the pixels in each row of the liquid crystal display element. It was done.

In the liquid crystal display device according to the present invention, the liquid crystal display element includes a liquid crystal element in which a ferroelectric liquid crystal or an antiferroelectric liquid crystal is sandwiched between a pair of substrates; A pair of polarized lights arranged so that one of the optical axes is oriented toward the average alignment direction of the liquid crystal molecules in the alignment state of the liquid crystal molecules when a write data signal of either the maximum value or the minimum value is applied. And a ferroelectric or antiferroelectric liquid crystal display device having a plate, and the ferroelectric liquid crystal or antiferroelectric liquid crystal can be driven at a higher driving duty because of a quick response to an applied voltage. it can.

When the ferroelectric or anti-ferroelectric liquid crystal display device is used, the control means controls the plurality of first drain lines of the liquid crystal display device so that the liquid crystal molecules are oriented to minimize the transmittance. Writing means for supplying a writing data signal for aligning the liquid crystal molecules in any one of an alignment state between the liquid crystal display element and the liquid crystal molecules. And a reset means for supplying a reset signal for aligning the liquid crystal display element to an alignment state near the middle between the alignment state in which the transmittance of the liquid crystal display element is minimum and the alignment state in which the transmittance is maximum. Desirably, by doing so, the voltage difference between the reset state and the written state is reduced, and the voltage-transmittance characteristic of the ferroelectric or antiferroelectric liquid crystal display element is reduced. By reducing the lysis, it is possible to prevent display flicker due to the hysteresis.

In this case, if the reset signal is different from the potential of the counter electrode in a direction in which an electric field in a direction opposite to the direction in which the ferroelectric liquid crystal or the antiferroelectric liquid crystal exhibits a fast response speed is obtained. It is more preferable that the signal has a given potential. By doing so, writing of the next display data after the reset can be performed with good responsiveness.

[Brief description of the drawings]

FIG. 1 is a basic configuration diagram of a field sequential liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a principle of displaying a color image by the liquid crystal display device.

FIG. 3 is an equivalent circuit plan view of a pixel electrode, a TFT, a gate line, and a drain line provided on one substrate of a liquid crystal display element of the liquid crystal display device.

FIG. 4 is a cross-sectional view of the liquid crystal display device along the line IV-IV in FIG.

FIG. 5 is a configuration diagram of a display drive unit of the liquid crystal display device.

FIG. 6 shows a write gate signal and a write data signal;
FIG. 4 is a diagram showing a reset gate signal, a reset signal, and a backlight lighting signal.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Liquid crystal display element 2 ... Liquid crystal element 3, 4 ... Substrate 5 ... Pixel electrode 6a ... Writing TFT 6b ... Reset TFT 7 ... Gate electrode 10 ... Source electrode 11 ... Drain electrode 12a ... Writing gate line 12b ... Reset Gate line 13a Write drain line 13b Reset drain line 16 Counter electrode 17, 18 Alignment film 19 Ferroelectric liquid crystal or antiferroelectric liquid crystal 20, 21 Polarizer 22 Backlight 23 Control means

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09F 9/00 337 G09F 9/00 337B 9/30 338 9/30 338 G09G 3/20 641 G09G 3/20 641E 642 642J 3/36 3/36 F term (reference) 2H093 NA14 NA15 NA16 NA43 NA65 NC16 NC34 NC43 NC44 ND05 ND09 ND10 ND17 ND34 NE06 NF19 NF20 5C006 AA22 AC02 AC24 AC25 AF44 AF71 BA12 BA13 BB16 BC06 ACA13 BF16 BC06 A08022 BB05 CC03 CC10 DD05 DD30 EE28 EE32 FF09 JJ02 JJ04 JJ06 KK43 5C094 AA00 AA02 AA03 BA03 BA43 CA19 DA09 EA04 HA08 5G435 AA00 AA01 BB12 DD11 LL08

Claims (4)

[Claims] 1. A liquid crystal display element having a liquid crystal element sandwiching liquid crystal between a pair of substrates having electrodes formed on opposing inner surfaces thereof, and controlling the transmission of light to display an image, and the liquid crystal display element. And a backlight that sequentially emits a plurality of colors of light toward the liquid crystal display element at a predetermined cycle and a frame for displaying one color image by the light emitted by the backlight. For each of a plurality of sub-frames divided by the number of colors, writing of display data corresponding to one of the plurality of colors to the liquid crystal display element and color corresponding to the display data from the backlight A liquid crystal display device, comprising: a control unit for emitting light of a plurality of colors, and displaying one color image by combining display of a plurality of colors for each of the plurality of subframes. A plurality of pixel electrodes arranged in a matrix on the inner surface of one of the substrates in the row direction and the column direction, and a pair of the pixel electrodes are arranged corresponding to the plurality of pixel electrodes, respectively. A plurality of thin film transistors whose electrodes are connected to the corresponding pixel electrode; a plurality of first gate lines connected to one gate electrode of the pair of thin film transistors, wired in correspondence with each pixel electrode row; A plurality of second gate lines connected to each of the pixel electrode rows and connected to the other gate electrode of the pair of thin film transistors; and a plurality of second gate lines connected to each of the pixel electrode columns; A plurality of first drain lines connected to one drain electrode of the thin film transistor; A plurality of second drain lines wired and connected to the other drain electrode of the pair of thin film transistors; and a counter electrode provided on the inner surface of the other substrate and facing the plurality of pixel electrodes. The control means supplies a write gate signal for turning on the one thin film transistor to each of the plurality of first gate lines of the liquid crystal display element for each of the plurality of subframes. Supplies a write data signal corresponding to display data corresponding to one of the plurality of colors to each of the plurality of first drain lines in synchronization with the plurality of first drain lines, and supplies the display data to pixels in each row of the liquid crystal display element. Writing means for sequentially writing data; and for each of the plurality of subframes, the display data of the display data to the pixels of each row of the liquid crystal display element. Backlight lighting means for emitting light of a color corresponding to the display data from the backlight for a predetermined period of time after the backlighting, after ending the emission of the light from the backlight, to the pixels in each row of the liquid crystal display element Prior to the writing of the next display data, a reset gate signal for turning on the other thin film transistor is supplied to the second gate line of the liquid crystal display element, and the second gate line is synchronized with the reset gate signal. And supplying a reset signal for obtaining a voltage having a predetermined value between a voltage at which the transmittance of the liquid crystal display element is minimized and a voltage at which the transmittance is maximized, to the drain line of the second pixel, A liquid crystal display device comprising: reset means for resetting a write state. 2. A liquid crystal display device, comprising: a liquid crystal element in which a ferroelectric liquid crystal or an antiferroelectric liquid crystal is sandwiched between a pair of substrates; and one of the optical axes on one and the other outer surface of the liquid crystal element. A pair of polarizing plates arranged in an average alignment direction of the liquid crystal molecules in an alignment state of the liquid crystal molecules when a write data signal of any of a maximum value and a minimum value is applied; Aligning the liquid crystal molecules in one of a plurality of first drain lines of the liquid crystal display element in one of an alignment state between a minimum transmittance state and a maximum transmittance state. Writing means for supplying a write data signal to be written; and a plurality of second drain lines of the liquid crystal display element, the liquid crystal molecules being aligned in an alignment state in which the transmittance of the liquid crystal display element is minimized and the transmittance is maximized. Orientation 2. The liquid crystal display device according to claim 1, further comprising: reset means for supplying a reset signal for orienting the liquid crystal in an alignment state near an intermediate state. 3. The liquid crystal display device according to claim 2, wherein the reset signal is a signal having a potential near the potential of the counter electrode. 4. A reset signal according to the potential of a counter electrode,
The liquid crystal according to claim 3, wherein the ferroelectric liquid crystal or the antiferroelectric liquid crystal is a signal having a potential different from a direction in which an electric field in a direction opposite to a direction in which a fast response speed is obtained is obtained. Display device.