JP2001266581A - Discharge circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a discharge circuit in which the fall of the level of high voltage caused by a leak current can be prevented when no discharge operation is performed in a discharge circuit in which high voltage generated by a high voltage generating circuit used for a non-volatile memory is discharged. SOLUTION: A Native NMOS transistor Q2 of which the threshold voltage is approximately 0 V and a CMOS circuit 12 are provided between a high voltage line 2 and the ground. In a period other than the time of discharge, the input of the CNOS circuit 12 is made a ground potential and its output is made power source voltage. VCC. In the transistor Q2, therefore, its source voltage is made power source voltage VCC and its gate voltage is made 50% of power source voltage VCC, and hence the transistor Q2 is turned off. Consequently, a leak current at the time of 'off' of a transistor Q3 is supplied from a power source by a transistor Q4 which is in an 'on' state, and is not supplied from a high voltage line 2 connected to the transistor Q2 being in an 'off' state.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a discharge circuit for discharging a high voltage generated by a high voltage generation circuit used in a nonvolatile memory such as an EEPROM,
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a discharge circuit capable of preventing a switch MOS transistor from leaking when a discharge circuit is not performing a discharge operation and preventing a decrease in a high voltage generated by a high voltage generation circuit.

[0002]

2. Description of the Related Art Conventionally, as a discharge circuit of this kind, for example, a circuit as shown in FIG. 4 is known. As shown in FIG. 4, the discharging circuit 3 is connected in parallel with a capacitor C1 connected between the high voltage line 2 of the high voltage generating circuit 1 and the ground, and short-circuits the high voltage line 2 to the ground during discharging. It is for doing.

That is, the discharge circuit 3 is connected to the high voltage line 2
An NMOS transistor Q1 and a high-voltage native NMOS transistor Q2 for preventing a high voltage from being applied to the NMOS transistor Q1 and being destroyed are connected in series between the ground and the ground. A gate control voltage V1 is applied to the gate of the NMOS transistor Q1,
The power supply voltage Vcc is always applied to the gate of the Native NMOS transistor Q2.

The operation of the discharge circuit 3 having such a configuration will be described with reference to the waveform diagram of FIG. The ENABLE (enable) signal WE of the high voltage generation circuit 1 is
As shown in (A), when rising at time t1, the capacitor C1 starts charging, and the high voltage Vpp of the high voltage line 2
Rises at a predetermined time constant and reaches a predetermined value (for example, about 17 V) as shown in FIG.

Then, at time t2 as shown in FIG. 5, the ENABLE signal WE falls and the MOS
Since the gate control voltage V1 of the transistor Q1 rises (see FIGS. 5A and 5C), the NMOS transistor Q1
1 turns on. Native NMOS transistor Q2 is always on. As a result, the high voltage line 2 is connected to the ground, and the electric charge of the capacitor C1 is discharged.
The high voltage Vpp of the high voltage line 2 sharply falls to 0 V as shown in FIG.

[0006]

Incidentally, the high voltage generating circuit 1 generally uses a charge pump. This charge pump has no current supply capability because a voltage is generated by a capacitor. Therefore, in the discharge circuit 3, if there is a leakage current I as shown in FIG. 4 due to the leakage when the NMOS transistor Q1 is turned off, FIG.
During the period from time t1 to time t2, the high voltage V
There is a disadvantage that the pp level is reduced.

FIG. 6 is a conceptual diagram of a charge pump included in the high voltage generation circuit 1. This charge pump is configured by connecting diodes (N + 1) stages in series, and producing a high output voltage Vout from the power supply voltage Vcc.
This is a stage booster circuit. More specifically, as shown in FIG. 6, one end of a capacitor C is connected to the cathode side of each diode D, and an oscillator 4 is connected to the other end of each capacitor C.
Is supplied directly or after being inverted by the inverter 5.

Here, assuming that the forward voltage Vf of the diode D is 0 V, an N-stage booster circuit is equivalent to a series connection of a power supply 6 and a resistor 7 as shown in FIG. The voltage E and the resistance value r of the resistor 7 are expressed by the following equations (1) and (2). E = (N + 1) Vcc (1) r = N / Cf (2) where Vcc in the equation (1) is the power supply voltage and the amplitude of the clock of the oscillator 4, and C in the equation (2) is a capacitor C And f is the frequency of the clock.

Also, the output voltage Vout of the charge pump
Becomes the following equation (3). Vout = (N + 1) × Vcc− (N / Cf) × Iout (3) where Iout is the supply current (leakage current when the MOS transistor Q1 is off). For example,
N = 30 steps, f = 1 MHz, C = 1.2 pF, Vcc =
When the output voltage Vout is calculated at 1.4 V, the following (4) is obtained.
It becomes an expression.

Vout = 43.4-25 × 10 ⁶ × Iout (4) Now, for example, assuming that the output voltage Vout required for writing to the EEPROM is 16 V, the leakage current I
out needs to be 1 μA or less. However, NMO
Leakage current Iou when S transistor Q1 is off
It is generally difficult to make t less than 1 μA in a conventional discharge circuit as shown in FIG.

It is an object of the present invention to provide a discharge circuit for discharging a high voltage generated by a high voltage generation circuit used in a nonvolatile memory. It is an object of the present invention to provide a discharge circuit capable of preventing a reduction in the discharge.

[0012]

Means for Solving the Problems In order to solve the above problems and achieve the object of the present invention, the inventions according to claims 1 and 2 have the following configurations. In other words, a first aspect of the present invention provides a discharge circuit for discharging a high voltage Vpp generated by a high voltage generation circuit used in a nonvolatile memory, wherein a high voltage line for generating and outputting the high voltage Vpp and a ground are provided. A first transistor having a threshold voltage of approximately 0 V and a CMOS circuit, wherein the first transistor has a drain connected to the high-voltage line and a source connected to the CMOS circuit. And the CMOS circuit is connected between a power supply line supplied with a power supply voltage Vcc (Vpp ≧ Vcc) and ground.

According to a second aspect of the present invention, in the discharge circuit according to the first aspect, when the NMOS transistor of the CMOS circuit is turned on, the first transistor is turned on at the gate of the first transistor. , The C
When the PMOS transistor of the MOS circuit is turned on, a voltage for turning off the first transistor is applied and used.

In the present invention having such a configuration, at the time of discharging, for example, the power supply voltage Vcc is applied to the input of the CMOS circuit, and the output thereof is at the ground potential. Thus, the first transistor is turned on because the source voltage is at the ground potential, the threshold value is approximately 0 V, and the predetermined voltage is applied to the gate. As a result, during discharge, the high voltage line is short-circuited to ground via the first transistor and the CMOS circuit.

On the other hand, when not discharging, the input of the CMOS circuit becomes, for example, the ground potential, so that its output becomes the power supply voltage Vcc. Thus, the first transistor has its source at the power supply voltage Vcc and its gate at, for example, about の of the power supply voltage Vcc.
Turns off. As a result, when not discharging, CMO
The leak current of the S circuit is supplied not from the high voltage line but from the power supply side, and is not supplied from the first transistor in the off state. Therefore, according to the present invention, it is possible to prevent the high voltage level of the high voltage line from lowering due to the leak current when the discharging operation is not performed.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. An embodiment of the discharge circuit of the present invention will be described with reference to the circuit diagram of FIG. FIG.
An example of the configuration of the discharge circuit of this embodiment is shown including a high-voltage generation circuit.

As shown in FIG. 1, this discharge circuit 11
A native NMOS transistor Q2 having a threshold voltage of approximately 0 V is provided between the high voltage line 2 and ground (ground).
And a CMOS circuit 12. Native N
The MOS transistor Q2 has a drain connected to the high voltage line 2, a source connected to the output side of the CMOS circuit 12, and a gate to which a voltage described later is applied.

The CMOS circuit 12 is a combination of an NMOS transistor Q3 and a PMOS transistor Q4, is connected between a power supply line and the ground, and has an input terminal 14 to which an input voltage described later is applied. , The output voltage of which is the native NMOS transistor Q2
Is applied to the source. More specifically, the NMOS transistor Q3 has a gate connected to the input terminal 14, a drain connected to the drain of the PMOS transistor Q4, and a native NMOS transistor Q3.
2 and connected to ground. The PMOS transistor Q4 has a gate connected to the input terminal 14 and a drain connected to the NMOS terminal.
The source of the transistor Q3 is connected to the power supply line, and the power supply voltage Vcc is applied.

Here, the native NMOS transistor Q
The gate voltage V3 input to the second gate needs to satisfy the following requirements. (1) When the source of the Native NMOS transistor Q2 is at the ground potential,
When the S-transistor Q3 is on and the output voltage of the CMOS circuit is at the ground potential, the Native NMOS transistor Q2 is turned on to bring the high voltage line 2 to the ground potential. (2) When the source of the Native NMOS transistor Q2 is at the power supply voltage Vcc,
When the MOS transistor Q4 is on and the output voltage of the CMOS circuit is the power supply voltage Vcc, and the high voltage V
When the relationship between pp and the power supply voltage Vcc is Vpp ≧ Vcc, the voltage is such that the Native NMOS transistor Q2 is turned off so that no current flows from the high voltage line 2 to the power supply line.

As the gate voltage V3 satisfying the two conditions (1) and (2), for example, the power supply voltage Vcc of 50
%, And this voltage is always applied to the gate of the Native NMOS transistor Q2. Next, an operation example of the discharge circuit of the embodiment having such a configuration will be described with reference to FIGS.

First, the case where the capacitor C1 is charged to the high voltage Vpp by the high voltage generation circuit 1 and the charge of the capacitor C1 is discharged will be described with reference to FIG. In this case, the input voltage V2 of the input terminal 14 of the CMOS circuit 12 is equal to the power supply voltage Vc as shown in FIG.
c, and the CMOS circuit 12 becomes the PMOS transistor Q
4 is turned off, the NMOS transistor Q3 is turned on, and C
The output of the MOS circuit 12 is at the ground potential. As a result, the native NMOS transistor Q2 has a source at the ground potential and a threshold value of approximately 0 V, so that the gate voltage V3 is turned on even at 50% of the power supply voltage Vcc. As a result, at the time of discharging, the electric charge of the capacitor C1 is changed to the high voltage line 2, Nativ, as shown by the arrow in FIG.
e Discharged via NMOS transistor Q2 and NMOS transistor Q3.

Next, the capacitor C1 is charged with electric charge, or the high-voltage line 2 is set to the high voltage V by the charged electric charge.
The case where pp is held will be described. In this case,
The input voltage V2 of the input terminal 14 of the CMOS circuit 12 is shown in FIG.
, The PMOS transistor Q4 is turned on, the NMOS transistor Q3 is turned off, and the output of the CMOS circuit 12 becomes the power supply voltage Vcc. By this, Native NMOS
Transistor Q2 is turned off because its source is at power supply voltage Vcc and its gate voltage V3 is at 50% of power supply voltage Vcc.

As a result, when not discharging, NMO
The leakage current when the S transistor Q3 is off is supplied from the power supply of the power supply line by the PMOS transistor Q4 in the on state and connected to the high voltage line connected to the Native NMOS transistor Q2 in the off state, as shown by the arrow in FIG. There is no supply from the two sides. Thus, according to this embodiment, the NMOS transistor Q
Since the leakage current during off state 3 is not supplied from the high voltage line 2 connected to the Native NMOS transistor Q2, it is possible to prevent the level of the high voltage on the high voltage line 2 from being lowered due to the leakage current.

[0024]

As described above, according to the present invention, the high voltage Vpp is generated and output between the high voltage line and the ground.
A first transistor having a threshold voltage of approximately 0 V;
The first transistor has a drain connected to the high-voltage line and a source connected to the C circuit.
The CMOS circuit is connected to the output side of the MOS circuit and is connected between the power supply line to which the power supply voltage Vcc (Vpp ≧ Vcc) is supplied and the ground. Therefore, according to the present invention, it is possible to prevent the high voltage level of the high voltage line from lowering due to the leak current when the discharging operation is not performed.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration example of an embodiment of the present invention and including a high voltage generation circuit.

FIG. 2 is a circuit diagram of the embodiment, illustrating the operation.

FIG. 3 is a circuit diagram of the embodiment, illustrating another operation.

FIG. 4 is a circuit diagram of a conventional discharge circuit.

FIG. 5 is a diagram showing operation waveforms of each part of the discharge circuit.

FIG. 6 is a conceptual diagram of a charge pump.

FIG. 7 is an equivalent circuit of FIG.

[Explanation of symbols]

 Q2 Native NMOS transistor Q3 NMOS transistor Q4 PMOS transistor 1 High voltage generation circuit 2 High voltage line 11 Discharge circuit 12 CMOS circuit

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5B025 AD10 AE08 5J056 BB40 BB49 CC00 CC03 CC16 CC29 CC30 DD13 DD28 DD29 DD51 DD55 EE12 FF08 GG06

Claims (2)

[Claims] 1. A discharge circuit for discharging a high voltage Vpp generated by a high voltage generation circuit used in a nonvolatile memory, wherein a threshold is provided between a high voltage line for generating and outputting the high voltage Vpp and ground. A first transistor having a value voltage of about 0 V and a CMOS circuit are provided. The first transistor has a drain connected to the high-voltage line and a source connected to the CMO.
The CMOS circuit is connected to the output side of the S circuit, and the power supply voltage Vcc (Vpp ≧
Vcc) is connected between a power supply line to which the power is supplied and ground. 2. The gate of the first transistor,
When the NMOS transistor of the CMOS circuit turns on, the first transistor turns on and the CMOS transistor turns on.
2. The discharge circuit according to claim 1, wherein when the PMOS transistor of the circuit is turned on, a voltage for turning off the first transistor is applied.