JP2001243767A - Fifo memory using volatile memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a FIFO memory using a volatile memory that can accelerate an operation frequency and has high expandability even though the size of the volatile memory is changed. SOLUTION: This FIFO memory using the volatile memory has a memory cell array composed of volatile memory cells arranged in rows and columns, a row address refresh request generation circuit generating a refresh request signal in every row address of the memory cell array, a flag storage cell where a flag is provided in the each row address and the flag becomes an activated or deactivated level in accordance with a write request and a read request, and a refresh decision circuit instructing a refresh operation to a prescribed row address in accordance with the refresh request signal and a flag level state.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of designing a semiconductor integrated circuit which realizes a certain function by combining a plurality of macroblocks and other logic cells.

[0002]

2. Description of the Related Art Conventionally, when configuring a FIFO memory, a non-volatile memory such as an SRAM has been used because it is not necessary to increase the storage capacity and it is necessary to operate at a high speed.

However, in recent years, a case in which continuous large data is handled (for example, compression and decompression of a digital image by hardware) has appeared, and the demand for a large-capacity FIFO memory has been increasing.

Further, in recent years, volatile memories that can be accessed at high speed have appeared, and when converted to the same storage capacity, using volatile memories is less expensive than using non-volatile memories. When combined with the point that
When configuring an O memory, it is necessary to use a volatile memory.

[0005] First, the structure of a volatile memory will be described. The volatile memory includes a memory cell including a transistor and a capacitor, a terminal for inputting an address, a terminal for inputting a control signal, and an input / output terminal for exchanging data. In the volatile memory, internal memory cells are arranged in a lattice.

[0006] Which of the memory cells arranged in the lattice is to be accessed is specified by vertical and horizontal positions. By specifying the vertical and horizontal positions, the memory cell at the intersection is accessed. The addresses for specifying the vertical and horizontal positions are called row addresses and column addresses. That is, the memory cell at the intersection of the row address and the column address is to be accessed. Reading or writing is performed on the memory cell to be accessed. The row address and the column address are sequentially input from an address input terminal at the time of access.

[0007] Reading and writing are determined by the control signal input terminal of the volatile memory. At the time of reading, the value in the accessed memory cell is output from the data terminal, and at the time of writing, the value input to the data terminal is written to the accessed memory cell.

[0008] Memory cells designated by the same row address in the volatile memory lose their values held in the memory cells unless read and written within a specific time. To prevent this, the volatile memory has a function called refresh. For refreshing, only the row address of the volatile memory is specified, and a value indicating that refreshing is to be performed is input to the control signal. By doing so, it is possible to prevent the value in the memory cell existing on the specified row address from being lost. Conversely, the value in the memory cell existing on the row address where none of reading, writing and refreshing has been performed within a certain time is lost.

First-in first-out data transfer using a volatile memory such as a DRAM (hereinafter referred to as FIFO, first-in first-out data transfer refers to data transfer in which written data is read in chronological order) In a memory having a function (a memory having a FIFO function is hereinafter referred to as a FIFO memory), refresh for preventing data loss in the volatile memory is always performed for all row addresses of the volatile memory. Rather, it is performed only for row addresses in which valid data is stored as a FIFO, thereby reducing the number of refreshes.

In the FIFO memory, addresses to be accessed are continuous, and valid data exists only in an area between a write address and a read address. Therefore, it is not necessary to refresh the entire area of the memory, and it is sufficient to refresh only the area where valid data exists.

By doing so, the number of times of refreshing can be reduced, which can be used for data transfer, and a high-performance FIFO can be realized. Conventionally, the area to be refreshed is calculated by using a write address and a read address.

FIG. 7 shows a conventional FIFO using a volatile memory.
2 shows a configuration of a memory.

In FIG. 7, the number of refreshes is controlled by adding a refresh control unit 18. The refresh control unit 18, which is a feature of the present invention, will be described. The refresh request generation timing 1814 generated from the refresh request generation circuit 1
Occurs at regular intervals. The refresh request generation timing 1814 is used to refresh all row addresses in the volatile memory within an interval for performing refresh (hereinafter referred to as a refresh interval) in order to prevent loss of data stored in the volatile memory. Occurs as many times as necessary. The refresh interval is counted by a refresh timer 188, and a refresh time elapse timing 1815 is generated every time the refresh interval elapses. The portion in which valid data is stored as a FIFO is an address sandwiched between a write address 71 indicating a write destination and a read address 61 indicating a read source. Therefore, every time the refresh time lapse timing 1815 occurs, the write address 71 The state of the read address 61 is held and the held contents are compared to find an address space in the volatile memory where valid data is stored. The number of row addresses of the volatile memory that needs to be refreshed is calculated by the address arithmetic circuit 186 based on the address space in which the valid data is held, and is output as the required refresh count 1812.

The number of refreshes within the refresh interval is counted by the refresh counter 187 every time the refresh request generation timing 1814 occurs, and is output as the number of refresh occurrences 1813. The coincidence detection 185 detects that the required number of refreshes 1812 and the number of occurrences of refresh 1813 coincide with each other.
89 occurs. When the request mask 189 is generated, the request mask circuit 181 generates the refresh request 10 with the remaining time of the refresh interval after the coincidence is detected.
The occurrence of is prohibited.

By doing so, it is possible to reduce the number of refreshes as compared with always refreshing all the row addresses of the volatile memory within the refresh interval. However, since the area that requires refresh is obtained by the address operation, the operating frequency is reduced because the number of gate stages of the arithmetic unit is large. When the size of the volatile memory is changed, the request mask circuit 181 and the matching circuit 1 in the broken line in FIG.
Since a value other than 85 must be changed, the expandability is lacking.

When volatile memory is not used as FIFO memory, flags have been used to control refresh.

FIG. 8 shows a conventional refresh method of a volatile memory. An address bus signal is externally input to the address buffer 3 for memory access,
When the S signal becomes active, the address is taken into the row address decoder 4. Thereafter, a target memory area on the memory cell 9 is selected through the address selector 6, and at the same time, a flag on the flag register 8 for this address is set.

When a refresh operation is required, a clock is input from the timing clock circuit 1 to the address counter 5, and the address output from the address counter 5 is decoded by the refresh address decoder 7 and input to the flag check circuit 11. Flag check circuit 1
1 retrieves from the flag register 8 the flag of the register having the same address as the decoding condition indicated by the refresh address decoder 7 and checks whether the flag is set.

If the flag is set, it means that a memory access has been made, so that the flag is reset without issuing a refresh request. If the flag is in the reset state, the request signal generator 12
To output the REFREQ signal and shift to the refresh cycle, and set the flag of the flag register 8. The REFREQ signal is released when a refresh cycle is entered. After the transition to the refresh cycle, the address selector 6 is switched so that the refresh address from the address counter 5 becomes valid for the memory cell 9 and the target address is refreshed.

The same processing is performed when the next refresh cycle is output, the refresh request is controlled according to the state of the flag, the flag is inverted, and if a refresh operation is required, the operation is shifted to the refresh cycle. As described above, the number of refreshes can be reduced.

[0021]

However, if the FIFO memory is refreshed by the above-described method, a portion of the FIFO memory that does not need to be refreshed is refreshed, and the data transfer efficiency is not improved.

[0022]

SUMMARY OF THE INVENTION A FIFO memory using a volatile memory according to the present invention controls a memory cell array composed of volatile memory cells arranged in rows and columns, and controls writing and reading to and from the memory cell array. A memory access control circuit, a row address refresh request generation circuit for generating a refresh request signal for each row address of the memory cell array, and a flag provided for each row address, wherein the flag is activated in response to a write request and a read request A flag storage cell at an activation level or an inactivation level; and a refresh determination circuit for instructing a refresh operation for a predetermined row address in accordance with the state of the refresh request signal and the level of the flag.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS As one of the features of the present invention, FIG.
As shown in (1), a refresh control circuit 10 is added to control the number of refreshes.
First, the refresh control circuit 10 will be described. This row address refresh request generation circuit 10
Row address refresh request 1010 generated from 1
Are generated at intervals of refreshing (hereinafter referred to as refresh intervals) in order to prevent loss of data stored in the volatile memory. The row address refresh request generation circuit 101 has circuits for generating row address refresh requests 1010 to 1014 for the row addresses.

The portion where data effective as a FIFO is stored is an address sandwiched between a write address 71 indicating a write destination and a read address 61 indicating a read source. The flag storage cell 103 has flags 1030 to 1030.
34, one for each row address, and row address 5
7 and WE104 and OE105 in the write mode.
"1" is stored in the read mode, and "0" is stored in the read mode.

The refresh determination circuit 102 has flags 1030 to 103 of each row address of the flag storage cell 103.
4 and refresh requests 1010 to 1014, it is determined whether each row address is to be refreshed (refresh determinations 1020 to 1024). Also, a refresh generation 106 indicating that refresh is being performed is generated.

The present invention will be described in more detail with reference to FIG.

The request arbitration circuit 2 detects the occurrence of a read request 8, which is a read request from the FIFO memory, a write request 9, which is a write request to the FIFO memory, and a busy 13, arbitrates according to the priority order, and simultaneously generates them. This is a circuit for selecting one of a plurality of requests or suspending two requests (when a busy 13 occurs). The arbitration result is output to the memory access control 4 and the selector 3 as the access mode 11. The access mode 11 is as follows depending on the result of the arbitration.

When the read request 8 is selected, the value indicates reading, and when the write request 9 is selected,
The value indicates writing, and when no request is issued, the value indicates non-access. In addition, as a result of mediation,
When the read request 8 is selected, a read address update 21 for updating the read address 61 to the read address pointer 6 is generated. Similarly, when the write request 9 is selected, a write address update 22 for updating the write address 71 to the write address pointer 7 is generated.

According to the state indicated by the access mode 11, the selector 3 corresponds to a read address 61 indicating a read source from the volatile memory, a write address 71 indicating a write destination from the volatile memory, and two address information. The address information is selected and output as the address 12. The address 12 is updated only when the access mode 11 changes.

The memory access control 4 includes an address 12,
This is a circuit for accessing the volatile memory 5 based on the read data 41, the write data 42, and the access mode 11. Access to the volatile memory 5 is performed via a memory address 15, a memory control signal 16, and memory data 17. On the basis of the address 12, a row address and a column address indicating an access destination to the volatile memory are generated,
The row address and the column address are sequentially output to the memory address 15.

The memory control signal 16 indicates whether access to the volatile memory 5 is reading, writing, or not accessing. Memory data 17
Is the data to be written to the volatile memory (write data 4
2) is output or the data read from the volatile memory is fetched. The fetched read data is output to the read data 41. In the memory access control 4, a busy 13 which is a signal indicating that the volatile memory is being accessed is output to the request arbitration circuit 2.

The volatile memory 5 is a memory such as a DRAM in which stored data is lost if access or refreshing is not performed within a predetermined time.

The read address pointer 6 generates a read address 61. When the read address update 21 occurs, the read address 61 is updated.

The write address pointer 7 generates a write address 71. When the write address update 22 occurs, the write address 71 is updated.

By using this circuit, only the area in the FIFO where valid data exists can be refreshed.
The operating frequency can be increased.

Further, since the refresh judgment is performed only by the row address, even if the size of the volatile memory changes, it is sufficient to change the circuit only for the row address, and the expandability is high.

Next, the refresh control circuit 10
The operation of (1) will be described with reference to the timing chart of FIG.

For the sake of explanation, the refresh performance of the volatile memory 5 is assumed as follows. The refresh interval is 64 milliseconds (hereinafter abbreviated as ms), the number of row addresses is 4096, and the number of column addresses (the number of data that can be stored in one row address)
Is 128.

Write address in write mode [18:
7] The active level “1” is set in the flag storage cell 103 selected by 71 (corresponding to the row address) (T6,
Flag [2048] 1033).

Read address in read mode [18:
7] In the flag storage cell 103 selected by 61 (corresponding to the row address), when the read address [18: 7] is incremented by 1, the inactive level is reset to “0” (T7, flag [2048]). 1033).

Row address refresh request generation circuit 1
01 is a row address refresh request 1010 to 101
4 generates one pulse every 64 ms in order from the 0th bit to the 4095th bit (T1 to T2, T3 to T4 and T
9 to T10).

The flags 1030 to 1034 of each row address of the flag storage cell 103 and the refresh request 1020
A logic gate having an AND of 〜１０1024 is provided for each row address in the refresh determination circuit, and its output is used for refresh determination. Therefore, the refresh determination 102
If 0-1024 is "1", refresh is performed (T0-
If "0", refresh is not performed (period T5 to T8).

Next, with respect to portions common to the conventional FIFO memory (other than the refresh control circuit 10),
This will be described with reference to the timing chart of FIG.

A read request 8 occurs. Upon detecting that the read request 8 has occurred, the access mode 11 is switched to a value indicating reading. When the access mode 11 is switched, the address 12 is switched to the read address 61 (T0).

When the access mode 11 is switched to reading, reading from the volatile memory cell array 56 is performed. The memory access control 4 sequentially outputs a row address (Rn row) and a column address (Rn column) based on the value (Rn) of the address 12 for the memory address 15. Further, a value necessary for reading from the volatile memory 5 is output to the memory control signal 16. As a result, the data in the address Rn of the volatile memory 5 is input to the memory access control 4 via the memory data 17. In addition, busy 13 which is a signal indicating that access is in progress
(T1 to T2).

When reading from the volatile memory cell array 56 is completed, the memory address 15, the memory control signal 1
6, busy 13 becomes a value indicating the non-access state. When the busy 13 changes to the non-issue state, the access mode 11 becomes non-access, and the address 12 also becomes 0. The data of the memory data 17 fetched by the memory access control 4 is output to the read data 41. When the busy 13 indicates the non-access state, a pulse is generated in the read address update 21 to update the read address 61 (T2).

A write request 9 occurs. Upon detecting that the write request 9 has occurred, the access mode 11 is switched to a value indicating write. When the access mode 11 is switched, the address 12 is switched to the write address 71. Further, data to be written to the volatile memory 5 is input to the write data 42 (T3).

When the access mode 11 is switched to writing, writing to the volatile memory 5 is performed. The row address (Wn) based on the value (Wn) of the address 12 with respect to the memory address 15 from the memory access control 4
The row address and the column address (Wn column) are sequentially output. Further, a value necessary for performing writing to the volatile memory 5 is output to the memory control signal 16. The memory data 17 includes
The value of the write data 42 is output. As a result, the memory data 1 is stored in the address Wn of the volatile memory 5.
7, the value of the write data 42 is written. Further, a busy 13 which is a signal indicating that access is being performed is generated (T4).
~ T5).

When the writing to the volatile memory 5 is completed, the memory address 15, the memory control signal 16, and the busy 13 become values indicating the non-access state. When the busy 13 changes to the non-access state, the access mode 11 becomes a value indicating non-access, and the address 12 also becomes 0.
When the busy 13 indicates the non-access state, a pulse is generated in the write address update 22 and the write address 71 is changed.
Is updated (T5).

A refresh occurrence 106 occurs. The occurrence of the refresh occurrence 106 is detected, and the memory control signal 16, the busy 13, and the access mode 11 become values indicating the refresh state (T6).

As described above, according to the present invention, the determination of the refresh is performed using the flag, so that the address operation becomes unnecessary, the number of gate stages is reduced, and
The operating frequency is improved. Even if the size of the volatile memory is changed, only the change for the row address is required, and an effect of high expandability is obtained.

FIG. 4 shows the difference in the number of gate stages depending on the size of the volatile memory. However, the gate is AND, OR, INVERTE
Only R was used.

As shown in FIG. 4, there is a difference of about 12 times in the number of gate stages between the conventional method and the method of the present invention, and it can be seen that the number of gate stages does not change even if the column address changes in the method of the present invention.

By using the present invention, the operating frequency can be increased and the expandability of the circuit can be improved.

As another embodiment of the present invention, the basic configuration is as described above, but by further devising, the occurrence of refresh requests can be reduced.

This will be described with reference to FIG. In FIG. 5, the row address refresh request generation circuit 101 of FIG.
Replace with 8.

The refresh timer 107 generates a refresh request timing 108 indicating that the time for refreshing has elapsed.

The operation will be described with reference to FIG. Figure 6
The refresh interval of the volatile memory described in
And

The refresh request timing 108 is 64
One pulse is generated every ms (T0 to T1 and T2 to T3
Period).

The AND of the flag 1030 to 1034 of each row address of the flag storage cell 103 and the refresh request timing 108 is performed. If the refresh judgment 1020 to 1024 of each row address is "1", refresh is performed (period T0 to T1). . Refresh judgment 102
If at least one of 0 to 1024 is "1", the refresh occurrence 106 occurs (period T0 to T1).

By doing so, each row address can be refreshed at most once.

[0062]

According to the present invention, the operation frequency can be increased by using a flag instead of an address operation with a large number of gate stages to obtain a refresh area. In addition, since the refresh determination is performed only by the row address, even if the size of the volatile memory changes, the circuit needs to be changed only for the row address, and the expandability is high.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a timing chart for explaining an operation of a refresh control circuit 10;

FIG. 3 is a timing chart for explaining a part common to a conventional FIFO memory;

FIG. 4 is a diagram illustrating a difference in the number of gate stages depending on the size of a volatile memory.

FIG. 5 is a circuit diagram for explaining another embodiment of the present invention.

FIG. 6 is a timing chart for explaining the operation of FIG. 6;

FIG. 7 is a circuit diagram showing a conventional technique.

FIG. 8 is a circuit diagram showing another conventional technique.

[Explanation of symbols]

 2 Request arbitration circuit 3 Selector 4 Memory access control circuit 56 Memory cell 102 Refresh determination circuit 103 Flag storage cell 107 Refresh timer

Claims (6)

[Claims] 1. A memory cell array comprising volatile memory cells arranged in rows and columns, a memory access control circuit for controlling writing and reading to and from the memory cell array, and a refresh request signal for each row address of the memory cell array A row address refresh request generating circuit, a flag storage cell in which a flag is provided for each row address, and wherein the flag is activated or deactivated in response to a write request or a read request; A FIFO memory using a volatile memory including a signal and a refresh determination circuit for instructing a refresh operation for a predetermined row address in accordance with a state of a level of the flag. 2. The volatile memory according to claim 1, wherein the flag storage cell activates a flag corresponding to a row address in a write mode and deactivates a flag corresponding to a row address in a read mode. FI using non-volatile memory
FO memory. 3. The volatile memory according to claim 1, wherein the refresh determination circuit has a logic gate for each row address that receives the level of the flag and the refresh request signal. FIFO memory. 4. A memory cell array comprising a volatile memory cell, and a flag storage cell for storing information of either an active level or an inactive level for each row address of the memory cell array. Activation level information is stored in a cell corresponding to a row address in which valid data is stored, and a refresh determination circuit instructing a refresh operation for a predetermined row address in accordance with the state of the flag level is provided. FIFO memory using a volatile memory as a feature. 5. The volatile memory according to claim 4, wherein the flag storage cell activates a flag corresponding to a row address in a write mode and deactivates a flag corresponding to a row address in a read mode. FI using non-volatile memory
FO memory. 6. The volatilization device according to claim 4, wherein the refresh determination circuit has a logic gate for each row address that receives the level of the flag and a refresh request signal generated for each row. FIFO using volatile memory
memory.