JP2001134490A - Method for controlling cache memory and computer for realizing the method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for controlling a cache memory for processing data having an address included in a designated address area in a batch in response to an instruction included in software and a computer for realizing the efficiency and quickening of the operation by realizing the method. SOLUTION: This computer is provided with a cache memory 10 including cache ways 15 and 17 constituted of cache blocks B1-B8 and a cache controlling part 30 for turning the cache blocks B1-B8 storing data having an address included in a designated address area into a state inhibiting replacement with other address data according to a supplied instruction, or for releasing the replacement inhibiting state.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a computer and a control method thereof, and more particularly, to a control method of a cache memory and a computer for realizing the method.

[0002]

2. Description of the Related Art In a conventional computer having a cache memory, a part of the control of the cache memory is not performed by software, so that the data stored in the cache memory does not need to be written back to the main memory. In some cases, the data may be written back, thereby deteriorating the efficiency of reading and writing data from and to the main memory.

A cache memory control method for executing a fetch instruction for preloading information into the cache memory in advance in units of one cache block has been conventionally realized. In such a control method, However, it was not possible to guarantee that the fetched information (read from the main memory) was stored in the cache memory until it was actually needed.

In controlling a cache memory,
A method of finding a cache block storing a certain address, copying data stored in the cache block to a main memory (this operation is called “flash”), and invalidating old data at the same address. Has been realized in the past, but there is no control method for selectively flushing and invalidating a plurality of cache blocks storing information in a continuous address area, and it is necessary to further improve operation efficiency. was there.

[0005]

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and has been made in consideration of the above-described problems. It is an object of the present invention to provide a memory control method and a computer capable of realizing operation efficiency and speedup by implementing the method.

[0006]

An object of the present invention is to provide a method of controlling a cache memory composed of cache blocks, wherein a cache block storing data having an address included in a designated address area is stored in a cache block. This is attained by providing a control method of a cache memory, wherein the replacement state to another address data is prohibited or the prohibited state is released in accordance with the supplied instruction. According to such means, it is possible to reliably avoid a cache miss to data having an address included in the specified address area, and to guarantee a cache hit.

It is another object of the present invention to provide a computer including a cache memory constituted by cache blocks, wherein a cache block storing data having an address included in a specified address area is supplied. The present invention is attained by providing a computer which is provided with a control unit which sets a state in which replacement with another address data is prohibited according to an instruction, or includes a control unit which cancels the prohibited state. According to such means, it is possible to reliably avoid a cache miss to data having an address included in the specified address area, and to guarantee a cache hit.

It is another object of the present invention to provide a computer including a cache memory connected to a main memory and configured from a cache block. The computer has an address included in a designated address area and is stored in the main memory. The present invention is attained by providing a computer characterized by comprising a control unit that loads the cached data into a cache block in accordance with a supplied instruction.

It is another object of the present invention to provide a computer including a cache memory connected to a main memory and configured from a cache block, having an address included in a specified address area and being stored in the cache block. The present invention is attained by providing a computer having a control unit for storing data stored in a main memory in accordance with a supplied instruction.

It is another object of the present invention to provide a computer including a cache memory connected to a main memory and configured from a cache block. The computer has an address included in a designated address area and stores the address in a cache block. The present invention is attained by providing a computer having a control unit for copying data stored in a main memory according to a supplied instruction.

It is another object of the present invention to provide a computer including a cache memory constituted by cache blocks, wherein a cache block storing data having an address included in a specified address area is supplied. The present invention is attained by providing a computer having a control unit for invalidating uniformly according to a command.

[0012]

Embodiments of the present invention will be described below in detail with reference to the drawings. In the drawings, the same reference numerals indicate the same or corresponding parts. FIG. 1 is a diagram showing an overall configuration of a computer according to an embodiment of the present invention. As shown in FIG. 1, the computer includes a CPU 1, a cache unit 3, a bus control device 5, a main memory 7, and a peripheral system 9. Then, the CPU 1 executes the fetch unit 1
1 and an execution unit 13. The cache unit 3 includes a cache memory 10, cache ways 15 and 17,
Address registers 19, 21 and data registers 23,
25, 27, and 29, and a cache control unit 30.

Here, the CPU 1 performs an arithmetic operation, a logical operation and the like. The cache unit 3 is connected between the CPU 1 and the bus control device 5 and the peripheral system 9 and temporarily stores information of the main memory 7 or the peripheral system 9. The cache control unit 30 is connected to the execution unit 13 included in the CPU 1 and controls the cache memory 10 and the like in response to a request from the CPU 1 or the peripheral system 9 or the like.

The bus control device 5 controls a memory data bus and an address bus provided between the bus control device 5 and the main memory 7 and controls data transfer with the peripheral system 9. The main memory 7 connected to the bus control device 5 holds instructions or data. On the other hand, the cache memory 10 includes two cache ways 15 and 17, and each cache way 15, 17 is divided into cache blocks B1 to B8. As shown in FIG. 1, each of the cache blocks B1 to B8 includes a valid flag V, a tag TAG, a lock flag L, and cache block data DATA. A change flag M is included.

Here, the valid flag V indicates that the cache block is invalid when a value of 0 is set (when reset), and the cache flag is invalid when a value of 1 is set (when set). Indicates that the block is valid. It is assumed that there is no data stored in the invalidated cache block. The tag TAG holds the address of the cache block data DATA. The lock flag L is a state in which the cache block permits the replacement of the address of the tag TAG when a value of 0 is set, and a state in which the replacement of the address is prohibited when the value of 1 is set. It is shown that. When the change flag M is set to 0, the cache block is not replaced (unchanged), and 1
Means that the data DATA of the cache block has been changed to the updated value.

In general, the write control of the cache memory includes a “write-through” format in which the cache memory and the main memory are updated simultaneously, and a method in which only the cache memory is updated once and a part of the cache memory is replaced. There is a “write-back” format in which the main memory is updated with data that is flushed to the main memory. The computer having the above-described configuration according to the present embodiment includes a load instruction, a store instruction, a lock instruction, an unlock instruction, a preload instruction, a post-store instruction, and a flash instruction written in the cache memory 10 or the main memory 7. , An invalidation instruction or the like is read, and data having an address included in the designated address area is collectively processed under the control of the cache control unit 30 in accordance with the instruction, thereby realizing efficient and high-speed operation. .

Hereinafter, a more specific description will be given. FIG. 2 is a diagram illustrating a configuration of the cache control unit 30 illustrated in FIG. 1 and a connection relationship between the cache control unit 30 and the cache memory 10. As shown in FIG. 2, the cache control unit 30 includes a load control unit 31 and a store control unit 3.
2, a preload control unit 33, and a post store control unit 3.
4, a flash control unit 35, an invalidation control unit 36,
A lock / unlock control unit 37, a decoding unit 38,
An address area control unit 40, an address register 45,
And a size register 47. Then, the address area control unit 40 sets the cache block size defining unit 41
, A comparator 42, an adder 43, and a subtractor 44.

In FIG. 2, although omitted in FIG. 1, the address and tag T included in the cache memory 10 and supplied from the address register 45 are included.
Comparator 12 for comparing with the address stored in AG
Is shown. Here, the decoding unit 38 is connected to the execution unit 13, and the load control unit 31, the store control unit 32, the preload control unit 33, the post store control unit 34, the flash control unit 35, the invalidation control unit 36, and the lock / unlock. The control units 37 are connected to the decoding unit 38, respectively. Further, the address area control unit 40 is connected to the execution unit 13,
Manage the address of the data to be processed. In the following:
FIG. 3 for explaining a difference in configuration between the cache control unit 30 and the conventional cache control unit is a diagram showing the configuration of the conventional cache control unit. As shown in FIG. 3, a conventional cache control unit 50 includes a load control unit 51, a store control unit 52, and a preload control unit 53.
, A flash control unit 55, an invalidation control unit 56, a lock / unlock control unit 57, a decode unit 58, and an address register 59. Therefore, the cache control unit 30 according to the present embodiment is different from the conventional cache control unit 50 in that the cache control unit 30 further includes the address area control unit 40, the size register 47, and the post store control unit 34. is there.

The operation of the computer according to this embodiment will be described below. First, the fetch unit 11 supplies an address for a desired instruction (code) to the cache memory 10 through the address register 19, and issues an instruction fetch request. Here, at the time of a cache hit in which the instruction at the address is stored in the cache memory 10, the instruction is read from the cache memory 10 and supplied to the fetch unit 11 via the data register 23. However, at the time of a cache miss in which the instruction of the address is not stored in the cache memory 10, the instruction is read from the main memory 7 according to the address supplied via the address register 21. The instruction read from the main memory 7 is stored in the data register 25,
The data is supplied to the fetch unit 11 via the control unit 23.

Next, the fetch unit 11 executes the instruction read from the cache memory 10 or the main memory 7 by the execution unit 1.
3 and the execution unit 13 executes the supplied instruction.
And since the following operations differ depending on the type of the instruction,
The operation of each instruction will be described sequentially. (Regarding the lock / unlock instruction) When the lock / unlock instruction is executed by the execution unit 13, the head address to be locked or unlocked to the address area control unit 40 included in the cache control unit 30; The size of the address area to be locked or unlocked is supplied. The head address is supplied to the comparator 12 via the address register 45. The head address is sequentially added to an address of one cache block defined by the cache block size defining part 41 in the adding part 43. Therefore, the comparator 12 scans the address to be locked or unlocked for each cache block and sequentially compares the address with the address stored in the tag TAG.

On the other hand, the size of the address area to be locked or unlocked is supplied to the lock / unlock control unit 37 via the size register 47 and the comparator 42, and only when the predetermined address area is scanned. , The lock / unlock control unit 37 is activated. Note that the size of the address area output from the size register 47 is
Subtractor 44 sequentially according to the size of one cache block
Is subtracted. When the comparator 42 determines that the address area to be locked or unlocked still remains, the lock / unlock control unit 37 is activated. When the comparator 42 determines that the scanning of the address area to be locked or unlocked is completed, the comparator 42 supplies a completion signal to the execution unit 13.

As described above, when the address to be locked or unlocked matches the address stored in the tag TAG (cache hit) as a result of the comparison by the comparator 12, it is determined that the cache hit has occurred. The signal to be notified is supplied to the lock / unlock control unit 37. As a result, the lock / unlock control unit 37 locks or unlocks the cache block that has hit the cache according to the signal. Therefore, 1 is locked when locking to the corresponding lock flag L, and 0 when unlocking. Are set respectively.

The value of the lock flag L set by the above operation is stored in the load control unit 31 and the store control unit 3.
2, preload control unit 33, post store control unit 34,
Flash control unit 35, invalidation control unit 36 and lock /
The cache block is supplied to the unlock controller 37, and when the value of the lock flag L is 0, the cache block can be replaced with another address data. When the value is 1, the cache block is replaced with another address data. Is prohibited.

Therefore, by executing such a lock / unlock instruction, a cache hit can be guaranteed for predetermined cache block data DATA stored in the cache memory 10, and the overall cache hit rate can be improved. it can. In addition, since a predetermined cache block is collectively locked or unlocked corresponding to the address included in the designated address area, the number of instructions to be executed can be reduced and the operation efficiency can be improved.

FIG. 4 is a diagram showing an instruction format of a lock / unlock instruction. As shown in FIG. 4, the lock / unlock instruction includes an instruction code OP-CODE that defines a lock instruction or an unlock instruction, an address specification field AD for specifying an address, and an area for specifying the size of the address area. And a size specification field SIZE. Such an instruction format is also used in the following instructions. (About the load instruction) The load instruction is executed by the execution unit 1.
When the processing is executed in step 3, the load control unit 31 included in the cache control unit 30 is supplied with the head address to be loaded and the size of the address area to be loaded. The start address is stored in the address register 4
5 is supplied to the comparator 12 through the adder 43.
It is sequentially added to the address of one cache block defined by 1. Therefore, the comparator 12 scans the address to be loaded for each cache block and sequentially compares the address with the address stored in the tag TAG.

On the other hand, the size of the address area to be loaded is supplied to the load control section 31 via the size register 47 and the comparator 42, and the load control section 31 is activated only when scanning a predetermined address area. Be transformed into Note that the size of the address area output from the size register 47 is sequentially subtracted by the subtraction unit 44 in accordance with the size of one cache block each time the one cache block is scanned. When the comparator 42 determines that the address area to be loaded still remains, the load control unit 31 is activated. When the comparator 42 determines that all the scanning of the address area to be loaded is completed, the comparator 42 supplies a completion signal to the execution unit 13.

As described above, when the address to be loaded matches the address stored in the tag TAG (cache hit) as a result of the comparison by the comparator 12, a signal notifying of the cache hit is generated. It is supplied to the load control unit 31. Thus, the load control unit 31 transfers the cache block data DATA stored in the cache block having the cache hit to the CPU 1 according to the signal. On the other hand, when a cache hit is not obtained in any of the cache blocks for the address to be loaded, the load control unit 31 reads data having the address from the main memory 7 via the bus control device 5 and And at least one cache block B1
Write to B8.

Therefore, by executing such a multiple register load instruction, data corresponding to the address included in the designated address area can be loaded from the cache block or the main memory 7 at a time. The number of instructions to be reduced can be reduced, and the operation efficiency can be increased. The load instruction includes a single register load instruction and a multiple register load instruction. Here, the single register load instruction is an instruction for reading data of a specified size in a specified address area into one specified register. On the other hand, a multiple register load instruction is an instruction for reading data of a specified size in a specified address area into a specified plurality of registers.

FIG. 7 shows the instruction format of the single register load instruction. That is, as shown in FIG. 7, the instruction format of the single register load instruction is such that an instruction code OP-CODE that specifies loading into a single register, an address specification field AD that specifies an address, and read data. And a register specification field REG for specifying a register to be stored.

On the other hand, the instruction format of the multiple register load instruction is the same as the instruction format of the lock / unlock instruction shown in FIG. That is, the multiple register load instruction is an instruction code OP that defines a load instruction for a plurality of registers.
-CODE and an addressing field to specify the address
An AD and an area size specification field SIZE for specifying the size of the address area are included. (About Store Instruction) When the store instruction is executed by the execution unit 13, the head address to be stored and the size of the address area to be stored are supplied to the store control unit 32 included in the cache control unit 30. You. The start address is supplied to the comparator 12 via the address register 45, but the start address is added to the adder 43.
Are sequentially added to the address of one cache block defined by the cache block size defining unit 41. Therefore, the comparator 12 scans the address to be stored for each cache block, and sequentially scans the tag TA.
Compare with the address stored in G.

On the other hand, the size of the address area to be stored is supplied to the store control unit 32 via the size register 47 and the comparator 42, and the store control unit 32 is activated only when a predetermined address area is scanned. Be transformed into Note that the size of the address area output from the size register 47 is sequentially subtracted by the subtraction unit 44 in accordance with the size of one cache block for each scan of one cache block. When the comparator 42 determines that the address area to be stored still remains, the store control unit 32 is activated. When the comparator 42 determines that all the scanning of the address area to be stored has been completed, the comparator 42 supplies a completion signal to the execution unit 13.

As described above, when the address to be stored matches the address stored in the tag TAG (cache hit) as a result of the comparison in the comparator 12, a signal notifying of the cache hit is generated. It is supplied to the store control unit 32. Thereby, the store control unit 3
2 writes the write data supplied from the execution unit 13 to the main memory 7 when the cache memory 10 is in the write-through operation, and, in response to the signal indicating that the cache hit has occurred, Update the data in the block. On the other hand, when the cache memory 10 performs the write-back operation, only the data of the cache block having the cache hit is updated according to the signal notifying that the cache hit has occurred.

Therefore, by executing such a multiple register store instruction, the write data corresponding to the address included in the designated address area can be stored collectively in the cache block or the main memory 7. The number of instructions to be executed can be reduced, and the efficiency of operation can be increased. The store instructions include a single register store instruction and a multiple register store instruction. Here, the single register store instruction is an instruction for writing data of a specified size from one designated register to a designated address area. On the other hand, a multiple register store instruction is an instruction for writing data of a specified size from a specified plurality of registers to a specified address area.

The instruction format of the single register store instruction is shown in FIG. That is, as shown in FIG. 7, the instruction format of the single register store instruction is an instruction code OP-CODE in which store from one register is specified.
And an address specification field AD for specifying an address;
And a register specification field REG for specifying a register in which data to be written is stored.

On the other hand, the instruction format of the multiple register store instruction is the same as the instruction format of the lock / unlock instruction shown in FIG. In other words, the multiple register store instruction is an instruction code that defines a store instruction from multiple registers.
An OP-CODE, an address specification field AD for specifying an address, and an area size specification field SIZE for specifying the size of an address area are included. (About the preload instruction) The preload instruction is executed by the execution unit 1.
When the processing is executed in step 3, the preload control unit 33 included in the cache control unit 30 is supplied with the head address to be preloaded and the size of the address area to be preloaded. The head address is supplied to the comparator 12 via the address register 45.
The start address is sequentially added to the address of one cache block defined by the cache block size defining unit 41 in the adding unit 43. Therefore, the comparator 12 scans the address to be loaded for each cache block and sequentially compares the address with the address stored in the tag TAG.

On the other hand, the size of the address area to be preloaded is supplied to the preload controller 33 via the size register 47 and the comparator 42, and the preload controller 33 only scans a predetermined address area. Be activated. Note that the size of the address area output from the size register 47 is sequentially subtracted by the subtraction unit 44 in accordance with the size of one cache block for each scan of one cache block. If the address area to be preloaded still remains, the comparator 42
When it is determined that the preload control unit 33 is activated, the preload control unit 33 is activated. If the comparator 42 determines that all the scans of the address area to be preloaded have been completed,
The comparator 42 supplies a completion signal to the execution unit 13.

As a result of the comparison by the comparator 12, the address and tag TAG to be preloaded are
A signal notifying that a cache hit has occurred when the address stored in the cache memory matches (cache hit), and a signal notifying that a cache miss has occurred when the address does not match (cache miss), respectively. 33. Thus, the preload control unit 33, via the bus control unit 5, via the bus control unit 5, when there is a cache miss in any of the cache blocks for the address to be preloaded.
, The data having the address is read out and written into at least one of the cache blocks B1 to B8, and the valid flag V of the cache block is set to 1 .

Therefore, by executing such a preload instruction, data corresponding to an address included in the specified address area can be preloaded from the main memory 7 to the cache memory 10 at a time, and thus should be executed. The number of instructions can be reduced and the efficiency of operation can be increased. Note that the preload instruction may accompany the operation of the lock instruction. At this time, if the data to be preloaded is stored in any of the cache blocks in the cache memory 10, the lock flag L of the cache block is set to 1 (locked). On the other hand, if the data to be preloaded is not stored in the cache memory 10, the data is stored in any of the cache blocks, the valid flag V of the cache block is set to 1, and the lock flag L To 1 (lock).

According to the above instructions, the loading of data into the cache block and the locking of the cache block are realized by executing one instruction, so that the operation efficiency can be improved. Here, in the above-mentioned command, a lock can be designated. That is, as shown in FIG. 5, in the form of an instruction, a lock designation field indicating whether to designate a lock.
A LOCK is further provided, and when data to be preloaded is stored in any of the cache blocks in the cache memory 10, the lock flag L of the cache block is set to 1 only when a lock is specified. (Lock). On the other hand, if the data to be preloaded is not stored in the cache memory 10, the data is stored in any of the cache blocks when the lock is specified, and the valid flag V of the cache block is set to 1. And set the lock flag L to 1 (lock). If the data to be preloaded is not stored in the cache memory 10 and the lock is not specified, the data is stored in any of the cache blocks, and the valid flag V of the cache block is set to 1. I do. (Regarding the post-store instruction) When the post-store instruction is executed by the execution unit 13, the post-store target start address and the post-store target address area are sent to the post store control unit 34 included in the cache control unit 30. Size is supplied. The head address is supplied to the comparator 12 via the address register 45. The head address is sequentially added to the address of one cache block specified by the cache block size specifying unit 41 in the adding unit 43. Therefore, the comparator 12
Scans the address to be post-stored for each cache block and sequentially compares the address with the address stored in the tag TAG.

On the other hand, the size of the address area to be post-stored is supplied to the post-store control section 34 via the size register 47 and the comparator 42. Is activated. Note that the size of the address area output from the size register 47 is sequentially subtracted by the subtraction unit 44 in accordance with the size of one cache block for each scan of one cache block. If the address area to be post-stored still remains, the comparator 4
When it is determined in step 2, the post store control unit 34 is activated. When the comparator 42 determines that all the scanning of the address area to be post-stored is completed, the comparator 42 supplies a completion signal to the execution unit 13.

As a result of the comparison by the comparator 12, when the address to be post-stored matches the address stored in the tag TAG (cache hit), a signal notifying of the cache hit is sent to the post. It is supplied to the store control unit 34. Accordingly, the post store control unit 34 determines that the value of the lock flag L of the cache block having a cache hit is 0 and the change flag M
Only when the value of is 1, the cache block data DATA of the cache block is written back to the main memory 7 and the valid flag V is set to 0. When a signal for notifying a cache miss is supplied from any of the cache blocks B1 to B8, the post store control unit 3
4 does not work.

Therefore, by executing such a post-store instruction, the cache block data DATA corresponding to the address included in the designated address area can be collectively written back to the main memory 7.
The number of instructions to be executed can be reduced, and the efficiency of operation can be increased. Note that the post store instruction may accompany the operation of the unlock instruction. At this time, if the data to be post-stored is stored in any of the cache blocks in the cache memory 10, the data is written back to the main memory 7 and the valid flag V is set to 0. And the lock flag L is set to 0 (unlocked). On the other hand, if the data to be post-stored is not stored in the cache memory 10, no corresponding operation is performed.

According to the above-mentioned instructions, the post-store of data in the main memory 7 and the unlocking of the cache block are realized by executing one instruction, so that the operation efficiency can be improved. Here, in the above-mentioned command, it is also possible to specify unlocking. That is, similarly to the instruction format shown in FIG. 5, an unlock specification field for specifying whether or not to perform unlocking is provided in the instruction format. If the data to be post-stored is stored in any of the cache blocks in the cache memory 10, the data is written back to the main memory 7 when the unlock is specified, and the valid flag V is set. At the same time, the lock flag L is set to 0 (unlocked). If there is no unlock designation at this time, the data is written back to the main memory 7 and the valid flag V is set to 0. on the other hand,
The data to be post-stored is cache memory 1
If it is not stored in 0, the corresponding operation does nothing. (About flash instruction) Flash instruction is executed by execution unit 1
When the processing is executed in step 3, the start address to be flushed and the size of the address area to be flushed are supplied to the flash control unit 35 included in the cache control unit 30. The head address is supplied to the comparator 12 via the address register 45.
The start address is sequentially added to the address for one cache block defined by the cache block size defining unit 41 in the adding unit 43. Therefore, the comparator 12 scans the address to be flashed for each cache block and sequentially compares the address with the address stored in the tag TAG.

On the other hand, the size of the address area to be flashed is supplied to the flash control unit 35 via the size register 47 and the comparator 42, and the flash control unit 35 only scans a predetermined address area. Be activated. Note that the size of the address area output from the size register 47 is sequentially subtracted by the subtraction unit 44 in accordance with the size of one cache block for each scan of one cache block.

When the comparator 42 determines that the address area to be flashed still remains, the flash control unit 35 is activated. It should be noted that the comparator 4 determines that all the above scanning of the address area to be flashed is completed.
If it is determined in step 2, the comparator 42 supplies a completion signal to the execution unit 13. As a result of the comparison by the comparator 12 as described above, when the address to be flushed matches the address stored in the tag TAG (cache hit), a signal notifying the cache hit is sent to the flash control unit 35. Supplied. As a result, the flush control unit 35 writes the cache block data DATA of the cache block into the main memory 7 only when the value of the lock flag L of the cache block that has hit the cache is 0 and the value of the change flag M is 1. And the valid flag V is kept at 1. When a signal notifying of a cache miss is supplied from any of the cache blocks B1 to B8, the flash control unit 35 does not perform a corresponding operation.

Therefore, by executing such a flash instruction, the cache block data DATA corresponding to the address included in the designated address area can be written back to the main memory 7 at a time. And the efficiency of the operation can be increased. The flash command may accompany the operation of the unlock command. At this time, if the data to be flushed is stored in any of the cache blocks in the cache memory 10,
After the data is written back to the main memory 7, the lock flag L is set to 0 (unlocked) while the valid flag V is set to 1. On the other hand, if the data to be post-stored is not stored in the cache memory 10, no corresponding operation is performed.

According to the above instructions, the unlocking of the cache block and the flushing of data to the main memory 7 are realized by executing one instruction and scanning one address, so that the time required for data processing is reduced. It can be shortened and operation efficiency can be increased. Here, in the above-mentioned command, it is also possible to specify unlocking. That is, similarly to the instruction format shown in FIG. 5, an unlock specification field for specifying whether or not to perform unlocking is provided in the instruction format. When the data to be flushed is stored in any of the cache blocks in the cache memory 10,
When the unlock is specified, the data is stored in the main memory 7
And the lock flag L is set to 0 (unlocked) while the valid flag V is set to 1. If there is no unlock designation at this time, the data is written back to the main memory 7. On the other hand, if the data to be flashed is not stored in the cache memory 10, no corresponding operation is performed. (About the invalidation instruction) When the invalidation instruction is executed by the execution unit 13, the invalidation control unit 36 included in the cache control unit 30 sends the invalidation start address and the invalidation target. The size of the address area is supplied.
The head address is supplied to the comparator 12 via the address register 45. The head address is sequentially added to the address of one cache block specified by the cache block size specifying unit 41 in the adding unit 43. Therefore, the comparator 12 scans the address to be flashed for each cache block and sequentially compares the address with the address stored in the tag TAG.

On the other hand, the size of the address area to be invalidated is supplied to the invalidation control unit 36 via the size register 47 and the comparator 42, and the invalidation control is performed only when a predetermined address area is scanned. The unit 36 is activated. Note that the size of the address area output from the size register 47 is sequentially subtracted by the subtraction unit 44 in accordance with the size of one cache block for each scan of one cache block.

When the comparator 42 determines that the address area to be invalidated still remains, the invalidation control unit 36 is activated. When the comparator 42 determines that all the scans of the address area to be invalidated have been completed, the comparator 42 supplies a completion signal to the execution unit 13. If the address to be invalidated matches the address stored in the tag TAG (cache hit) as a result of the comparison by the comparator 12 as described above, a signal for notifying that a cache hit has occurred is set to invalidation control. Part 36
Supplied to As a result, the invalidation control unit 36 sets the valid flag V without writing back the cache block data DATA of the cache block to the main memory 7 only when the value of the lock flag L of the cache block that has hit the cache is 0. Set to 0. When a signal for notifying a cache miss is supplied from any of the cache blocks B1 to B8, the invalidation control unit 3
6 does not work.

Therefore, by executing such an invalidation instruction, the cache block data DATA corresponding to the address included in the designated address area can be invalidated, so that the number of instructions to be executed is reduced. Operation efficiency can be increased. The invalidation command may accompany the operation of the unlock command. At this time, if the data to be invalidated is stored in any one of the cache blocks in the cache memory 10, the cache block is unlocked and the data is Disable. According to such an instruction, the unlocking of the cache block and the invalidation of the data are realized by executing one instruction and scanning one address, so that the time required for data processing can be reduced and the operation efficiency can be improved. .

Here, the above-mentioned instruction may be an instruction that can be forcibly designated to ignore the lock flag L and invalidate the lock flag L. That is, as shown in FIG.
In the form of an instruction, a force specification field FORCE indicating whether or not to specify force is further provided. If data to be invalidated is stored in any cache block in the cache memory 10, the force specification field FORCE is set. When specified, the data is not written back to the main memory 7,
The valid flag V is set to 0, and the lock flag L is set to 0 (unlocked). In this case, when the forcible designation is not made, invalidation is not executed in the locked state. On the other hand, the data to be invalidated is the cache memory 10.
If not, the corresponding action is not taken.

Here, the operation of the above instructions is summarized as follows.
Table 1 below.

[0053]

[Table 1]

In Table 1 above, 動作 indicates operation, and × indicates no operation. In Table 1, “A1” is an operation when the cache block is not locked, and indicates that either an operation of executing an invalid operation (NOP) instruction or loading into another cache block may be performed. . “A2” is an operation for setting (locking) the lock flag L of the cache block to 1 and performing either an invalid operation (NOP) instruction or loading to another cache block. Show good things.

Finally, means for solving the problems of the present invention will be additionally described. (1) A method for controlling a cache memory connected to a main memory and configured from a cache block, wherein data having an address included in a designated address area and stored in the main memory is transmitted to a supplied instruction. A method of controlling a cache memory, wherein a cache block is loaded in response to a request. According to such means, data having addresses included in the designated address area can be loaded collectively. (2) The method of controlling a cache memory according to (1), wherein the cache block is set in a state in which replacement with another address data is prohibited after loading according to the instruction.
According to such means, the operation speed can be improved. (3) A method for controlling a cache memory connected to a main memory and configured from a cache block, wherein data having an address included in a specified address area and stored in the cache block is transmitted to a supplied instruction. A method for controlling a cache memory, wherein the cache memory is stored in a main memory in response to the request. (4) The method of controlling a cache memory according to (3), wherein the state in which the replacement of the cache block with another address data is prohibited is released after the storage in response to the instruction. (5) A control method for a cache memory connected to a main memory and configured from a cache block, wherein data having an address included in a designated address area and stored in the cache block is supplied. A method of controlling a cache memory, wherein a method of copying to a main memory according to an instruction. According to such a means, it is possible to copy only necessary data to the main memory to improve the operation efficiency. (6) The cache memory control method according to (5), wherein the prohibition of replacement of the cache block storing data after copying with another address data is released in response to the instruction. According to such means, the operation speed can be improved. (7) A method for controlling a cache memory including a cache block, wherein a cache block storing data having an address included in a specified address area is invalidated uniformly according to a supplied instruction. A method of controlling a cache memory. By such means, useless write-back operation can be avoided and operation efficiency can be increased. (8) A computer including a cache memory composed of cache blocks, in which a cache block storing data having an address included in a designated address area is converted to another address data in accordance with a supplied instruction. A computer which is provided with a control unit for making the replacement prohibited state or canceling the prohibited state. (9) The control unit further includes a lock flag provided corresponding to each of the cache blocks, and the control unit sets a lock flag corresponding to the cache block storing data having an address included in the designated address area. ,
The computer according to (8), wherein the computer is set or reset according to a supplied instruction. According to such a means, by setting the lock flag, only the desired cache block can be collectively set to the replacement prohibition state with another address data, so that the cache memory is used more efficiently and the operation is performed. Speed can be improved. (10) A computer which is connected to a main memory and includes a cache memory composed of a cache block, and which has an address included in a designated address area and is supplied with data stored in the main memory. A computer comprising: a control unit that loads a cache block according to the condition. (11) The control unit further includes a lock flag provided corresponding to each of the cache blocks, and the control unit sets a lock flag corresponding to the cache block loaded after loading according to the supplied instruction. The computer according to (10), which is characterized in that: (12) A computer including a cache memory connected to a main memory and configured from a cache block, the data having an address included in a designated address area and being stored in the cache block,
A computer comprising a control unit for storing data in a main memory according to a supplied instruction. (13) A lock flag provided corresponding to each of the cache blocks is further provided, and the control unit resets the lock flag corresponding to the cache block after storing according to the supplied instruction. (1
The computer according to 2). (14) A computer which is connected to a main memory and includes a cache memory constituted by a cache block. The computer has an address included in a designated address area and is supplied with data stored in the cache block. And a control unit for copying to a main memory in accordance with an instruction. (15) A lock flag corresponding to each cache block is further provided, and the control unit resets a lock flag corresponding to a cache block in which data is stored after copying in accordance with a supplied instruction. The computer according to (14).

[0056]

As described above, according to the present invention, replacement of a cache block storing data having an address included in a specified address area with another address data in accordance with a supplied instruction is prohibited. In order to improve the access speed as a whole, the cache hit is assured by reliably avoiding a cache miss to the data having the address included in the specified address area in order to set the state or to cancel the prohibited state. be able to.

Further, the cache block storing the data having the address included in the designated address area is set to a state in which replacement with another address data is prohibited according to the supplied instruction, or the prohibited state is released. By providing the control unit, it is possible to reliably avoid a cache miss to data having an address included in the specified address area, guarantee a cache hit, and improve the access speed as a whole.

Also, a control unit having an address included in a specified address area and loading data stored in the main memory into the cache block in accordance with a supplied instruction is provided. Data having addresses included in the address area can be loaded at a time, so that the speed and efficiency of data processing can be improved.

Further, a control unit having an address included in a specified address area and storing data stored in the cache block in the main memory in accordance with a supplied instruction is provided. Data having addresses included in the address area can be stored collectively, so that high-speed and efficient data processing can be achieved.

Further, by providing a control unit for copying data stored in a cache block having an address included in a designated address area to a main memory in accordance with a supplied instruction, operation efficiency is improved. Can be improved. Further, by providing a control unit for uniformly invalidating a cache block storing data having an address included in a designated address area in accordance with a supplied instruction, the operation efficiency can be improved. .

[Brief description of the drawings]

FIG. 1 is a diagram showing an overall configuration of a computer according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration of a cache control unit illustrated in FIG. 1;

FIG. 3 is a diagram showing a configuration of a conventional cache control unit.

FIG. 4 is a diagram showing an instruction format such as a lock / unlock instruction according to the embodiment of the present invention.

FIG. 5 is a diagram showing an instruction format having a lock designation field according to the embodiment of the present invention.

FIG. 6 is a diagram showing an instruction format having a compulsory designation field according to the embodiment of the present invention.

FIG. 7 is a diagram showing an instruction format such as a single register load / store instruction according to the embodiment of the present invention;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 CPU 3 Cache part 5 Bus control device 7 Main memory 9 Peripheral system 10 Cache memory 11 Fetch part 12, 42 Comparator 13 Execution part 15, 17 Cache way 19, 21, 45, 59 Address register 23, 25, 27, 29 Data register 30, 50 Cache control unit 31, 51 Load control unit 32, 52 Store control unit 33, 53 Preload control unit 34 Post store control unit 35, 55 Flash control unit 36, 56 Invalidation control unit 37, 57 Lock / Unlock Lock control unit 38, 58 Decoding unit 40 Address area control unit 41 Cache block size defining unit 43 Addition unit 44 Subtraction unit 47 Size register

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hideo Miyake 4-1-1, Kamidadanaka, Nakahara-ku, Kawasaki-shi, Kanagawa F-term within Fujitsu Limited (Reference) 5B005 JJ11 JJ13 KK12 MM01 NN12 NN22 NN42 NN43 NN45 PP03 PP21 QQ00

Claims (6)

[Claims] 1. A method for controlling a cache memory including a cache block, wherein the cache block storing data having an address included in a designated address area is separated according to a supplied instruction. A method for controlling a cache memory, wherein a replacement with address data is prohibited or the prohibited state is released. 2. A computer including a cache memory constituted by cache blocks, wherein said cache block storing data having an address included in a designated address area is separated according to a supplied instruction. A computer comprising: a control unit that sets a state in which replacement with address data is prohibited or cancels the prohibited state. 3. A computer including a cache memory connected to a main memory and configured from a cache block, and supplies data having an address included in a specified address area and stored in the main memory. A control unit for loading the cache block in response to an instruction to be executed. 4. A computer which is connected to a main memory and includes a cache memory constituted by a cache block, and supplies data having an address included in a specified address area and stored in the cache block. And a control unit for storing the data in the main memory in accordance with a command to be executed. 5. A computer including a cache memory connected to a main memory and configured from a cache block, the computer having an address included in a designated address area and storing data stored in the cache block. And a control unit for copying to the main memory in accordance with a supplied instruction. 6. A computer including a cache memory constituted by a cache block, wherein the cache block storing data having an address included in a designated address area is uniformly stored in accordance with a supplied instruction. A computer comprising a control unit for invalidating a computer.