JP2001119201A - Circuit ic for switching high frequency - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the isolation characteristic of a two input-two output high frequency switching circuit IC. SOLUTION: Switching means 1 to 4 connecting input-output terminals (Ant1, Ant2, Tx and Rx) are constituted of a serial connection circuit of two MESFETs (e.g. the switching mean 1 is formed of Q11 and Q12), and a parallel transistor (Q5) connecting its connection point to a ground line is arranged.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an I / O circuit used for switching an antenna circuit in mobile communication.
More particularly, the present invention relates to a two-input two-output switch IC having improved isolation characteristics when transmitting a large signal to an antenna terminal.

[0002]

2. Description of the Related Art Conventionally, for example, a circuit shown in FIG. 4 has been used as a microwave switch IC. The switch IC 30 includes, as external terminals, first and second antenna terminals Ant1 and Ant2, a transmission signal terminal Tx, a reception signal terminal Rx, and first and second control terminals Vc1 and Vc2. The first transistor Q1 connects the first antenna terminal Ant1 to the transmission signal terminal Tx, and the second transistor Q1 connects the transmission signal terminal Tx to the second antenna terminal Ant2.
A third transistor Q3 connects between the second antenna terminal Ant2 and the reception signal terminal Rx, and a fourth transistor Q4 connects between the reception signal terminal Rx and the first antenna terminal Ant1. And the first
And the gates of the third and fourth transistors Q1 and Q3 are connected to the first control terminal Vc1 via respective gate resistors Rg, and the gates of the second and fourth transistors Q2 and Q4 are connected to the second gate via respective gate resistors Rg. Control terminal Vc2
Connected to

These elements are formed on a GaAs substrate, and each of the transistors Q1 to Q4 is a junction gate type field effect transistor. In this case, an N-channel normally ON type Schottky junction gate type FET (ME) is used.
SFET).

When using this switch IC 30,
First antenna terminal Ant1, second antenna terminal An
At t2, a first antenna circuit (not shown), a second antenna circuit (not shown), and a transmission circuit (not shown) are respectively connected to a transmission signal terminal Tx and a reception signal terminal Rx via an external DC cut capacitor C. (Not shown) and receiving circuit (not shown)
Is connected. Then, a high-low signal is supplied to the first control terminal Vc1 and the second control terminal Vc2 in a complementary manner to connect the first antenna terminal Ant1 to the transmission signal terminal Tx and to connect the second antenna terminal Ant2 to the transmission signal terminal Tx. The state is switched between a state where the antenna is connected to the transmission signal terminal Rx and a state where the first antenna terminal Ant1 is connected to the reception signal terminal Rx and the second antenna terminal Ant2 is connected to the transmission signal terminal Tx.

Next, the operation of the switch circuit will be described. For example, a high signal (eg, 3
V) is supplied to the second control terminal Vc2 with a low signal (for example, 0
When V) is applied, the gate junctions of the second and fourth transistors are reverse-biased, and those transistors are turned off. Conversely, the first and third transistors are ON.
As a result, the first antenna terminal Ant1 is connected to the transmission signal terminal Tx, and the second antenna terminal Ant2 is connected to the reception signal terminal Rx. Similarly, when 0V is applied to the first control terminal Vc1 and 3V is applied to the second control terminal Vc2, the first antenna terminal Ant1 is connected to the reception signal terminal Rx, and the second antenna terminal Ant2 is connected to the transmission signal terminal Tx Connect to

[0006]

SUMMARY OF THE INVENTION
In C, if a large signal (especially a transmission signal) is to be processed, for example, the first transistor Q1 is turned on and the second and fourth transistors are turned on.
When the transistors Q2 and Q4 are turned off, the ability of the second and fourth transistors Q2 and Q4 to block the signal passage is insufficient, and leaks to the second antenna terminal Ant2 or the reception signal terminal Rx, and in some cases may be harmful there. There is a problem that causes noise.

Therefore, as a first plan, the same transistors as the transistors Q1 to Q4 in the switch IC of FIG. 4 suitable for processing a relatively small signal are replaced with a plurality of (for example, two) transistors connected in series. A method of increasing the ability to block the signal passage at the time of OFF can be considered. However, in this method, since the ON resistance is doubled, a loss occurs due to this, and for example, a loss of a signal transmitted from the transmission signal terminal Tx to the first antenna terminal Ant1 increases.

Therefore, as a next plan, a method using a plurality of (for example, two) transistors having a large channel width connected in series in order to reduce the ON resistance is considered. However, even in this method, since the channel width of the transistor is large, the source at the time of OFF-
Since the drain-to-drain capacitance is large, especially at higher frequencies, the ability to block signal passage is insufficient, causing signal leakage.

[0009]

In order to solve the above-mentioned problems, the present invention provides first and second one-side high-frequency terminals, first and second other-side high-frequency terminals, and first and second high-frequency terminals. A control terminal, first switch means for connecting between the first one-side high-frequency terminal and the first other-side high-frequency terminal, and a switch between the first other-side high-frequency terminal and the second one-side high-frequency terminal. A second switch means for connecting, a third switch means for connecting between the second one-side high-frequency terminal and the second other-side high-frequency terminal, a second other-side high-frequency terminal and a first one-side high-frequency terminal And a fourth switch means for connecting the first and third switch means to ON-O with a control signal given to the first control terminal.
In addition to performing FF control, the second and fourth switch means are turned ON / OFF by a control signal given to the second control terminal, and a control signal is given complementarily to these control terminals. In a switch IC that connects one high-frequency terminal to one other high-frequency terminal and switches a combination that connects the remaining one high-frequency terminal and the other high-frequency terminal to the other, a first, second, and third switch IC is provided. , The fourth switch means is constituted by connecting a plurality of junction gate type FETs in series, and the connection point is connected to the ground line in a high frequency manner in accordance with ON-OFF of the switch means.
A switch IC provided with a parallel transistor connected to ON is provided. According to such a means, the first, second, third, and fourth switch means are each formed by connecting a plurality of junction gate type FETs in series, so that the OFF operation is reliably performed even for a large signal. . Then, in order to sufficiently reduce the resistance at the time of ON, the junction gate type FETs constituting the switch means have a large channel width, and the capacitance between the source and the drain at the time of OFF becomes large. Since the parallel transistor is ON, the leakage is not released to the ground line. Therefore, the isolation characteristics are improved.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram thereof. The same parts as those of the conventional switch IC shown in FIG. The switch IC 10 includes first and second antenna terminals Ant as first and second one-side high-frequency terminals.
1 and Ant2 as external terminals, and a transmission signal terminal Tx and a reception signal terminal R as first and second other high-frequency terminals.
x as an external terminal, and first and second control terminals Vc
1 and Vc2 as external terminals are the same as the conventional switch IC shown in FIG. And this switch I
C10 includes a ground terminal Gnd as an external terminal. A transistor Q1 as the first switch means 1 is connected between the first antenna terminal Ant1 and the transmission signal terminal Tx.
1, the series connection circuit of Q12 is connected. The transistors Q21 and Q2 as the second switch means 2 are connected between the transmission signal terminal Tx and the second antenna terminal Ant2.
Two series connection circuits are connected. Then, a series connection circuit of the transistors Q31 and Q32 as the third switch means 3 is connected between the second antenna terminal Ant2 and the reception signal terminal Rx. The series connection circuit of the transistors Q41 and Q42 as the fourth switch means 4 connects between the reception signal terminal Rx and the first antenna terminal Ant1. Then, the first switch means 1 and the third switch means
Transistors Q1 respectively constituting the switch means 3
1 and Q12 and the gates of Q31 and Q32 are connected to the first control terminal Vc1 via respective gate resistors Rg.
And the gates of the transistors Q21, Q22 and Q41, Q42 constituting the second switch means 2 and the fourth switch means 4, respectively, are connected to the second control terminal Vc2 via respective gate resistors Rg. The ON / OFF control of the first and third switch means 1 and 3 is performed by a control signal supplied to a first control terminal Vc1, and the first and third switch means 1 and 3 are controlled by a control signal supplied to a second control terminal Vc2. 2, the fourth switch means 2 and 4 are turned on and off, and a control signal is supplied to these control terminals in a complementary manner, and the control signal causes one antenna terminal, the transmission signal terminal Tx, and the reception signal terminal Rx to be connected. One of them is connected, and the combination of connecting the remaining antenna terminal and the remaining one of the transmission signal terminal Tx and the reception signal terminal Rx is switched.

Then, in this switch IC 10,
As a main feature, a high-frequency OFF-ON connection is made between the series connection point of the transistors constituting the first, second, third, and fourth switch means 1, 2, 3, and 4 and the ground terminal Gnd. Is provided. That is, the fifth transistor Q5 is connected between the connection point between the transistors Q11 and Q12 and the ground terminal Gnd, the sixth transistor Q6 is connected between the connection point between the transistors Q21 and Q22 and the ground terminal Gnd, Connection point between transistor Q31 and transistor Q32 and ground terminal G
nd, a seventh transistor Q7, a connection point between the transistor Q41 and the transistor Q42 and the ground terminal Gn.
An eighth transistor Q8 is provided between the first and second transistors Q and d.
The gates of the fifth and seventh transistors Q5 and Q7 are connected to the second control terminal V via respective gate resistors Rg.
c2, and the gates of the sixth and eighth transistors Q6 and Q8 are connected to the first control terminal Vc1 via respective gate resistors Rg (not shown for easy understanding of the drawing). .

These elements are formed on a GaAs substrate, and each transistor (Q11 to Q42 and Q5
To Q8) are junction gate type field effect transistors, here, N channel normally ON type MESFETs.
It is.

When using this switch IC 10,
First antenna terminal Ant1, second antenna terminal An
At t2, a first antenna circuit (not shown), a second antenna circuit (not shown), and a transmission circuit (not shown) are respectively connected to a transmission signal terminal Tx and a reception signal terminal Rx via an external DC cut capacitor C. (Not shown) and receiving circuit (not shown)
Is connected. The ground terminal Gnd is connected to a ground line. Then, a negative high-low signal is supplied to the first control terminal Vc1 and the second control terminal Vc2 complementarily to connect the first antenna terminal Ant1 to the transmission signal terminal Tx, and to connect the second antenna A first state in which the terminal Ant2 is connected to the reception signal terminal Rx, and a second state in which the first antenna terminal Ant1 is connected to the reception signal terminal Rx and the second antenna terminal Ant2 is connected to the transmission signal terminal Tx. Switch.

Next, the operation of the switch circuit will be described.
For example, a high signal (for example, 0 V) is applied to the first control terminal Vc1.
Is supplied to the second control terminal Vc2 with a low signal (for example, -3V).
, The fifth (seventh) transistor Q5 (Q7) of the parallel transistors is off, and the sixth (eighth) transistor Q6 (Q8) is on. Therefore, the gate junctions of the transistors Q21 and Q22 (Q41 and Q42) are reverse-biased, and the transistors {ie, the second (fourth) switch means 2 (4)} are turned off.
F. Conversely, transistors Q11 and Q12 (Q31,
Q32) {That is, the first (third) switch means 1
(3)｝ is ON. As a result, the first antenna terminal Ant1 is connected to the transmission signal terminal Tx, and the second antenna terminal Ant2 is connected to the reception signal terminal Rx. Similarly, the first control terminal Vc1 has -3V and the second control terminal Vc1 has
When 0V is applied to c2, the first antenna terminal Ant1 is connected to the reception signal terminal Rx, and the second antenna terminal Ant is connected.
2 is connected to the transmission signal terminal Tx.

According to this embodiment, for example, when the first antenna terminal Ant1 is connected to the transmission signal terminal Tx and the second antenna terminal Ant2 is connected to the reception signal terminal Rx, the transmission signal is large. However, since the second and fourth switch means 2 and 4 for blocking the passage are constituted by a series connection circuit of the transistor Q21 and the transistor Q22 (the transistor Q41 and the transistor Q42), the second and fourth switch means 2 and 4 are more compared with the prior art. It is completely turned off. The turned-off transistor Q21 (Q42) acts as a parasitic capacitance and the leaked signal is released to the ground line by the turned-on sixth transistor (eighth transistor), so that the second antenna terminal Ant2 and the reception signal Terminal Rx
To reduce harmful noise from leaking.

According to the above usage method, the control terminal Vc
1, because the control signal given to Vc2 is a negative voltage, there is an inconvenience in actual use. Therefore, if the external connection is changed as shown in FIG. 2, it can be driven by a positive control signal, which is convenient. 2, the only difference from FIG. 1 is that the ground terminal Gnd is connected to the ground line via the DC cut capacitor C. Therefore, the description of the other connection relations will be omitted and the operation will be omitted.

For example, when a high signal (for example, 3 V) is applied to the first control terminal Vc 1 and a low signal (for example, 0 V) is applied to the second control terminal Vc 2, the transistors Q 21 and Q 2
2, Q41 and Q42 have transistors Q12,
Through the gates of Q31, Q32 and Q11, a positive voltage (3
(V-gate junction voltage) is applied, and the gate is OFF because it is 0 V (that is, the second and fourth switch means 2 and 4 are OFF), and the transistor Q1 is turned on.
1, Q12, Q31, Q32 (that is, the first and third switch means 1, 3) are ON. Here, since the positive voltage is applied to the fifth and seventh transistors Q5 and Q7 and 0 V is applied to the gates, the transistors are OFF, and the sixth and eighth transistors Q6 and Q8 apply 3 V to the gates. Since the drain is pulled by the gate reverse bias leakage current of the transistors Q21 and Q22 or the transistors Q41 and Q42, the drain has a voltage lower than 3V by the gate junction voltage, so that the drain is ON. As a result, the first antenna terminal A
nt1 is connected to the transmission signal terminal Tx, and the second antenna terminal Ant2 is connected to the reception signal terminal Rx. Similarly, 0V is applied to the first control terminal Vc1, and 3V is applied to the second control terminal Vc2.
When V is applied, the first antenna terminal Ant1 is connected to the reception signal terminal Rx, and the second antenna terminal Ant2 is connected to the transmission signal terminal Tx.

In the first embodiment, first and second high-frequency terminals (first antenna terminal and second antenna terminal) and first and second other high-frequency terminals (transmission signal terminal,
The reception signal terminal), the first and second control terminals, and the ground terminal are external terminals, respectively.
However, the present invention is not limited to such a configuration. This includes those having points corresponding to those terminals inside. For example, a capacitor having all or a part of the DC cut capacitor C therein, or a DC power terminal provided separately as an external terminal, a single control signal terminal serving as an external terminal, and a high-low signal And may create a complementary signal internally.

Particularly, the fifth. The DC cut capacitors that connect the sixth, seventh, and eighth transistors to the ground line in a high frequency manner are the fifth DC cut capacitors. In cooperation with the sixth, seventh, and eighth transistors, their characteristics and arrangement affect the signal leakage when the switch means is turned off. Therefore, it is better to optimize the internal configuration. Such a second embodiment will be described with reference to FIG. This switch IC 20 differs from the first embodiment shown in FIG. 2 in that the fifth, sixth, seventh and eighth transistors Q
5, Q6, Q7, and Q8 are connected to the ground line in high frequency and cut off in DC. Instead of the external DC cut capacitor C, a built-in DC cut capacitor C1 is used. Are the same as those in the first embodiment, and a description thereof will be omitted. The operation is the same as in the case of the external connection shown in FIG.

In the above embodiment, the DC cut capacitor C1 for connecting the fifth, sixth, seventh, and eighth transistors to the ground line at high frequency and the ground terminal Gnd as an external terminal are one set. (4 sets) may be provided for each parallel transistor or may be combined into 2 sets. Of course, it can be changed to incorporate a DC cut capacitor of another high frequency terminal.

In each of the first and second embodiments, each switch means is constituted by a series connection circuit of two transistors. However, three or more transistors may be connected in series.
In this case, a parallel transistor may be provided at each connection point. 1
Only a single location can be provided.

In the first and second embodiments, a single parallel transistor is used. However, the transistor may be connected in multiple stages in series.

In the first and second embodiments, the first
Although the junction gate type FETs constituting the switching means and the parallel transistors of (1) to (4) are MESFETs, the present invention
It may be an N-junction gate type or hetero-junction gate type FET.

[0024]

As described above, according to the switch IC of the present invention, the switch means is constituted by connecting a plurality of transistors in series, and a parallel transistor for connecting the connection point to the ground line ON-OFF. Since the switch is provided, it is possible to reduce signal leakage when the switch is turned off, thereby reducing noise.

[Brief description of the drawings]

FIG. 1 is a circuit diagram including an external connection of a switch IC according to an embodiment of the present invention.

FIG. 2 is a circuit diagram in which the external connection of the IC is changed.

FIG. 3 is a circuit diagram including an external connection of a switch IC according to another embodiment of the present invention.

FIG. 4 is a circuit diagram including an external connection of a conventional switch IC.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 1st switch means 2 2nd switch means 3 3rd switch means 4 4th switch means 10,20 switch IC (high frequency switching circuit IC) Ant1 1st antenna terminal (1st one side high frequency terminal) Ant2 Second antenna terminal (second one-side high-frequency terminal) Gnd ground terminal Q11, Q12, Q21, Q22, Q31, Q32, Q
41, Q44 Transistor (junction gate type FET) Q5, Q6, Q7, Q8 Transistor (parallel transistor) Tx Transmission signal terminal (first other high-frequency terminal) Rx Receive signal terminal (second other high-frequency terminal) Vc1 1 control terminal Vc2 2nd control terminal

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (reference) // H04B 7/02 H04B 7/02 A 5K062 F term (reference) 5J012 BA03 BA04 5J055 AX06 AX28 AX56 BX06 CX03 CX26 DX13 DX23 DX24 DX61 DX72 DX73 EY01 GX01 5J098 AA03 AA11 AC05 AC10 AC14 AC20 AD11 EA01 5K011 DA02 DA21 FA01 GA04 JA01 KA05 5K059 DD01 DD27 5K062 AA01 AB06 AB09 AC01 AE05 BA02 BB01 BB16

Claims (5)

[Claims] And a first and second one-side high-frequency terminals;
A second other high-frequency terminal, first and second control terminals,
A first switch for connecting between the first one-side high-frequency terminal and the first other-side high-frequency terminal; and a second switch for connecting between the first other-side high-frequency terminal and the second one-side high-frequency terminal. A switch means, a third switch means for connecting between the second one-side high-frequency terminal and the second other-side high-frequency terminal, and a connection between the second other-side high-frequency terminal and the first one-side high-frequency terminal. And a fourth switch means for turning on and off the first and third switch means by a control signal given to the first control terminal.
At the same time, the second and fourth switch means are turned ON / OFF by a control signal given to the second control terminal, and a control signal is given to these control terminals in a complementary manner. A first, second, and a second high-frequency switching circuit IC for connecting a high-frequency terminal to one other high-frequency terminal and switching a combination for connecting the remaining one high-frequency terminal to the other high-frequency terminal on the other side. Third, the fourth switch means is constituted by connecting a plurality of junction gate type FETs in series, and the connection point is connected to a ground line at high frequency in accordance with ON-OFF of the switch means.
A high-frequency switching circuit IC comprising a parallel transistor connected to FF-ON. 2. The high-frequency switching circuit according to claim 1, wherein each of said first, second, third and fourth switch means comprises two junction gate type FETs connected in series.
C. 3. The high frequency switching circuit IC according to claim 1, wherein the parallel transistor comprises a plurality of transistors connected in series. 4. The parallel transistor is a junction gate type FE.
4. The high-frequency switching circuit IC according to claim 1, wherein T is T. 5. The high-frequency switching circuit IC according to claim 4, wherein said junction gate type FET constituting said switch means and said parallel transistor is a Schottky junction gate type FET.