JP2001103224A - Image processing circuit and image forming device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow an image processing circuit to self-check its image processing system with an inexpensive configuration. SOLUTION: Test image data produced from a 1st test image generating circuit are given to the image processing system in place of input image data from a scanner section, the data pass through each image processing block in a through mode and data of a check object are selected among respective outputs. Each output is compared with an output of a 2nd test image generating circuit whose start is delayed against the 1st test image generating circuit by a delay of the selected check object data to discriminate whether or not data transfer timing and a bit check of a data line are acceptable.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing circuit for performing image processing in a plurality of processing stages, and an image forming apparatus having the image processing circuit and printing out an image read by a scanner by a printer.

[0002]

2. Description of the Related Art Generally, a digital copying machine such as an image forming apparatus for printing out an image read by a scanner by a printer is provided with an image processing circuit for performing image processing in a plurality of processing stages on an image read by the scanner. ing.

In such a copying machine, a CCD of a scanner is used.
The image data input from is amplified by an analog amplifier,
After being converted into a digital signal by the A / D converter, the image signal enters the image processing circuit.

In an image processing circuit, first, shading correction is performed by a shading correction circuit, and then smoothing processing is performed by an LPF (low-pass filter). Thereafter, the edge is emphasized by an HPF (high-pass filter), and then the image is enlarged / reduced by an enlargement / reduction unit. Thereafter, tone processing such as error diffusion and dither processing is performed by a tone processing unit, and then temporarily recorded in a buffer memory, read out again, and output to a printer engine (printer).

Further, the image processing circuit is provided with a test image generating circuit.

The test image generating circuit is a circuit for generating test image data. For example, the test image generating circuit generates image data in which the gradation changes every plural lines, and this data is used instead of a signal from the CCD. By inputting to the shading correction circuit of the image processing circuit, passing or executing each image processing block in the same manner as the image processing for the signal from the CCD, and outputting the test image to the printer engine, the test image is printed. Mainly used for adjusting the printer engine.

Since these processes are executed in synchronization with the image transfer clock CLK, the image data is delayed in clock units with respect to the input timing each time the signal passes through the processing block. Has become.

However, in a conventional image processing circuit,
If an attempt is made to check whether the circuit is operating normally in a manner such as a self-check of the circuit inside the device, for example, test data for checking the image processing circuit is prepared in a memory or the like. Data is input to the image processing circuit,
There is a method of comparing the output with expected value data prepared in a memory or the like in advance to check whether a mismatch occurs.

However, in this case, a storage device such as a large-capacity memory is required to hold the test data and the expected value data, which causes a problem that the cost is considerably increased.

Also, when inputting data using a test image generation circuit, a large-capacity memory or the like is required to prepare expected value data, and the output of the test image generation circuit is used as expected value data. There is also a method of using a delayed data, but a large-capacity memory or a delay circuit or the like is similarly required for delaying the data, so that there has been a problem of a significant increase in cost as described above. .

[0011]

SUMMARY OF THE INVENTION It is an object of the present invention to provide an image processing circuit capable of performing a self-inspection with an inexpensive configuration, and an image forming apparatus using the image processing circuit.

[0012]

An image processing circuit according to the present invention, which performs image processing in a plurality of processing stages, comprises: first output means for outputting predetermined image data;
Supply means for supplying the image data outputted from the output means in order through the processing steps, and second output means for outputting the image data from each processing step by supplying the image data by the supply means. Selecting means for selecting image data from the second output means corresponding to a processing step of judging whether the image data is normal, and selecting the image data from the first output means by the selecting means. A third output unit for outputting the predetermined image data at a timing when the image data is output from the processing stage;
And a judgment unit for judging whether or not the processing at the processing stage selected by the selection unit is normal by comparing the image data output by the output unit with the image data selected by the selection unit.

An image processing circuit according to the present invention, which performs image processing in a plurality of processing stages, includes: first output means for outputting predetermined image data; and image data output from the first output means. Supply means for supplying the image data from the processing steps in sequence, a supply means for supplying the image data by the supply means, and a second output means for outputting the image data from each processing step. Selecting means for selecting image data from the second output means corresponding to a step; and outputting image data from the processing step selected by the selecting means with respect to the output from the first output means. A third output unit that outputs the predetermined image data with a delay of a time, and an image data output by the third output unit and an image data selected by the selection unit. By comparison, and a determination means for processing of the processing steps that have been selected by the selection means determines whether normal or not.

An image processing circuit according to the present invention, which performs image processing in a plurality of processing stages, comprises: first output means for outputting predetermined image data; and image data output from the first output means. Supplying means for supplying the image data from each processing step by supplying the image data by the supplying means in order through the processing steps in a through state; Selecting means for selecting image data from the second output means corresponding to the processing step of judging, and outputting the image data from the processing step selected by the selecting means to the output from the first output means. A third output means for outputting the predetermined image data at a timing when
Determining means for determining whether or not the processing of the processing stage selected by the selection means is normal, based on whether or not the image data output by the output means and the image data selected by the selection means match Consists of

An image forming apparatus according to the present invention includes an image processing circuit for performing image processing in a plurality of processing stages, wherein the image data from the image processing circuit is formed on an image forming medium. A first output unit for outputting predetermined image data, a supply unit for supplying the image data output from the first output unit in order through the processing steps, and an image data output by the supply unit. A second output means for respectively outputting image data from each processing stage, and a selection means for selecting image data from the second output means corresponding to the processing step for determining whether or not the image data is normal. A third output unit that outputs the predetermined image data at a timing at which image data is output from the processing stage selected by the selection unit with respect to the output from the first output unit. And comparing the image data output by the third output means with the image data selected by the selection means to determine whether or not the processing of the processing stage selected by the selection means is normal. And an execution unit that executes the abnormality determination function of the image processing circuit every time a predetermined number of images are formed on the image forming medium.

An image forming apparatus according to the present invention includes an image processing circuit for performing image processing in a plurality of processing stages, wherein the image data from the image processing circuit is formed on a medium on which an image is to be formed. A first output unit for outputting predetermined image data, a supply unit for supplying the image data output from the first output unit in order through the processing steps, and an image data output by the supply unit. A second output means for respectively outputting image data from each processing stage, and a selection means for selecting image data from the second output means corresponding to the processing step for determining whether or not the image data is normal. A third output unit that outputs the predetermined image data at a timing at which image data is output from the processing stage selected by the selection unit with respect to the output from the first output unit. And comparing the image data output by the third output means with the image data selected by the selection means to determine whether or not the processing of the processing stage selected by the selection means is normal. And an execution unit that executes the abnormality determination function of the image processing circuit each time the operation time of forming an image on the image forming medium reaches a predetermined time.

An image forming apparatus according to the present invention includes an image processing circuit for performing image processing in a plurality of processing stages, wherein the image data from the image processing circuit is formed on an image forming medium. A first output unit for outputting predetermined image data, a supply unit for supplying the image data output from the first output unit in order through the processing steps, and an image data output by the supply unit. A second output means for respectively outputting image data from each processing stage, and a selection means for selecting image data from the second output means corresponding to the processing step for determining whether or not the image data is normal. A third output unit that outputs the predetermined image data at a timing at which image data is output from the processing stage selected by the selection unit with respect to the output from the first output unit. And comparing the image data output by the third output means with the image data selected by the selection means to determine whether or not the processing of the processing stage selected by the selection means is normal. And an execution unit for executing the abnormality determination function of the image processing circuit between the image formation on the image forming medium and the image formation on the next image forming medium. Having means.

[0018]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view showing a schematic configuration of a digital copying machine 1 as an example of the image forming apparatus of the present invention.

As shown in FIG. 1, the digital copying machine 1 includes an apparatus main body 2, in which a scanner section 4 as image reading means and a printer section 6 functioning as image forming means are provided. Have been.

On the upper surface of the apparatus main body 2, there is provided an original mounting table 8 made of transparent glass on which an object to be read, that is, an original D is mounted. An automatic document feeder 9 (hereinafter, referred to as an ADF) for automatically feeding the document D onto the document table 8 is provided on the upper surface of the apparatus main body 2.

The scanner unit 4 provided in the apparatus main body 2
The exposure lamp 10 includes, for example, a halogen lamp as a light source for illuminating the document D placed on the document table 8, and the first mirror 12 that deflects reflected light from the document D in a predetermined direction. These exposure lamps 10
The mirror 12 is provided with a first mirror disposed below the document table 8.
It is attached to the carriage 14.

The first carriage 14 is arranged so as to be movable in parallel with the original table 8, and is reciprocated below the original table 8 by a scanner motor (drive motor) 16 via a toothed belt or the like (not shown). You. Scanner motor 16
Is constituted by a stepping motor or the like.

A second carriage 18 that can move in parallel with the document placing table 8 is provided below the document placing table 8. A second carriage 18 sequentially deflects the reflected light from the document D deflected by the first mirror 12.
And third mirrors 20, 22 are mounted at right angles to each other. The second carriage 18 receives the rotational force from the scanner motor 16 by a toothed belt or the like that drives the first carriage 14 and is driven by the first carriage 14. 1
The document is moved in parallel along the document table 8 at a speed of / 2.

An image forming lens 24 for converging the light reflected from the third mirror 20 on the second carriage 18 and a light receiving the light condensed by the image forming lens 24 are provided below the document table 8. And a CCD sensor (line sensor) 26 for performing photoelectric conversion. The imaging lens 24 is movably disposed via a drive mechanism in a plane including the optical axis of the light deflected by the third mirror 20, and moves the reflected light to a desired magnification ( An image is formed in the main scanning direction). The CCD sensor 26 is connected to a main CP (described later).
In accordance with the image processing clock given from U, the reflected light incident on the original is subjected to photoelectric conversion, and an electric signal corresponding to the read original D is output. The magnification in the sub-scanning direction can be handled by changing the moving speed of the first carriage 14.

On the other hand, the printer section 6 includes a laser exposure device 28 which functions as a latent image forming means. The peripheral surface of the photosensitive drum 30 is scanned by the laser light from the laser exposure device 28 to form an electrostatic latent image on the peripheral surface of the photosensitive drum 30.

The printer section 6 has a rotatable photosensitive drum 30 serving as an image carrier disposed substantially at the center of the apparatus main body 2. And a desired electrostatic latent image is formed. On the peripheral surface of the photosensitive drum 30, a charging charger 32 for charging the peripheral surface of the photosensitive drum to a predetermined charge, and a toner as a developer is supplied to the electrostatic latent image formed on the peripheral surface of the photosensitive drum 30 by supplying toner. A developing unit 34 for developing at an image density of the image forming medium, and a peeling charger 36 for separating the image forming medium fed from a paper cassette described later, that is, the copy paper P from the photosensitive drum 30, A transfer charger 38 for transferring the toner image formed on the drum 30 to the paper P, a peeling claw 40 for peeling the copy paper P from the peripheral surface of the photosensitive drum 30, and a cleaning device for cleaning the toner remaining on the peripheral surface of the photosensitive drum 30 42, and
A static eliminator 43 for neutralizing the peripheral surface of the photosensitive drum 30 is arranged in order.

A cassette and a large-capacity feeder which can be pulled out from the apparatus main body 2 are provided at a lower portion and a side portion in the apparatus main body 2, respectively.

In the apparatus main body 2, the photosensitive drum 30 and the transfer charger 38 from each cassette and a large capacity feeder are provided.
A conveyance path 44 extending through the transfer section located between the conveyance path 44 and the fixing section 46 having a fixing lamp is provided at the end of the conveyance path 44. An outlet 48 is formed in the side wall of the apparatus main body 2 facing the fixing device 46.
Is equipped with a finisher 50.

In the transfer section, the developer image formed on the photosensitive drum 30, that is, the toner image is transferred onto the paper P by the transfer charger 38. The copy paper P on which the toner image has been transferred is separated from the peripheral surface of the photosensitive drum 30 by the action of the separation charger 36 and the separation claw 40,
The sheet is conveyed to the fixing device 46 via a conveyance belt 52 constituting a part of the conveyance path 44. After the developer image is fused and fixed to the copy paper P by the fixing device 46, the copy paper P is discharged onto the finisher 50 through the discharge port 48 by the pair of paper feed rollers 54 and the pair of discharge rollers 56.

Below the transport path 44, there is provided an automatic double-sided device 56 for reversing the copy sheet P which has passed the fixing device 46 and sending it to the transport path 44 again.

The finisher 50 is for stapling and storing the discharged partially structured documents in a unit.

An operation panel (to be described later) for instructing various copying conditions such as a copy magnification and the start of copying is provided on the upper front part of the apparatus main body 2.

FIG. 2 is a block diagram schematically showing a signal flow for electrical connection and control of digital copying machine 1 in FIG.

As shown in FIG. 2, in the digital copying machine 1, the main CPU 61 in the main control unit 60 and the scanner unit 4
Printer CP of the printer unit 6 with the scanner CPU 70
It is composed of three CPUs U80. Main CPU 61
The main CPU 61 performs bidirectional communication (asynchronous serial communication) with the scanner CPU 70 and the printer CPU 80 via a serial interface.
Gives an operation instruction and returns a status status.

The main control unit 60 includes a main CPU 61, an RO
M62, RAM 63, NVM 64, image processing circuit 65,
A page memory control unit 66 and a page memory 67 are provided.

The main CPU 61 controls the entire main control section 60. The ROM 62 stores various control programs and control data such as a control program for reading a document with respect to the temperature detected in the scanner unit 4.
The RAM 63 temporarily stores data.

NVM (lasting random access memory: n)
The on-volatile RAM (64) is a non-volatile memory backed up by a battery (not shown), and retains data on the NVM 64 when the power is turned off.

The image processing circuit 65 performs shading correction, smoothing processing, edge enhancement, enlargement / reduction processing, gradation processing, and the like based on an image processing clock CLK supplied from the main CPU 61.

The page memory control unit 66 stores and reads out image data in the page memory 67, and synthesizes characters such as page fonts with the image data in the page memory 67.

The scanner unit 4 includes a scanner CPU 70 for controlling the entire scanner unit 4, a ROM 71 for storing a control program, a RAM 72 for data storage, a CC
A CCD driver 73 for driving the D sensor 26; a scanner motor driver 7 for controlling the rotation of the scanner motor 16 for moving the first and second carriages 14 and 18 on which the exposure lamp 10 and the mirrors 12, 20 and 22 are mounted.
4. An image correction unit 75 that amplifies an output signal from the CCD sensor 26 with an analog amplifier (not shown) and converts the signal into a digital signal by an A / D converter (not shown). An exposure lamp control unit 76 controls the amount of power of the exposure lamp 10 by controlling the amount of power applied to the exposure lamp 10.

The RAM 72 stores the image scan magnification (speed) designated by the main CPU 61.

The ROM 71 previously stores pre-scanning sub-scanning speed error data for macro identification for all image scan magnifications. This allows
The scanner CPU 70 retrieves the sub-scanning speed error data of the magnification (speed) designated by the main CPU 61 from the ROM 71 and transmits the data to the main CPU 61.

The printer unit 6 controls a printer CPU 80 for controlling the entire printer unit 6, a ROM 81 storing a control program and the like, a RAM 82 for data storage, and a semiconductor laser (not shown) of the laser exposure device 28 to emit light. A laser driver 83 for turning on / off, a polygon motor driver 84 for controlling the rotation of the polygon motor of the laser exposure device 28, a paper transport unit 85 for controlling the transport of the paper P by the transport path 44, the charger 32, the developing device 34,
The image forming apparatus includes a developing process unit 86 that performs charging, development, and transfer using the transfer charger 38, a fixing control unit 87 that controls the fixing device 46, and an option unit 88.

The image processing circuit 65 and the page memory 6
7. The image correction unit 75 and the laser driver 83 are connected by an image data bus 68.

The operation panel 90 has a panel CPU 91 connected to the main CPU 61, to which a print key 92 and a liquid crystal display section 93 are connected, and controls the display contents of the liquid crystal display section 93 and the whole control such as processing of input contents. Done.

As a result, the operation states of the printer CPU 80 and the scanner CPU 70 are set to the main CP as the status.
The main CPU 61 always returns to the printer CP
The state of the U 70 and the scanner CPU 70 can be grasped, and the contents of the input from the operation panel 90 can be determined to control the entire copying machine.

As shown in FIG. 3, the image processing circuit 65 includes a switching unit 100, a shading correction circuit 101,
PF (low-pass filter) 102, HPF (high-pass filter) 103, enlargement / reduction unit 104, gradation processing unit 10
5, buffer memory 106, delay / comparison control unit 107,
It comprises a first test image generation circuit 108, a second test image generation circuit 109, a selection unit 110, and a data comparison unit 111.

Here, the shading correction circuit 101,
LPF (low pass filter) 102, HPF (high pass filter) 103, enlargement / reduction unit 104, gradation processing unit 1
05, the buffer memory 106 is an image processing block (each constituted by an IC chip). As a result, image processing in a plurality of processing stages is performed by each of the image processing blocks 101 to 106. Each of the image processing blocks 101 to 106 has a through circuit in addition to the processing circuit, and is switched to a processing circuit side or a through circuit (in a through mode or a pass mode) by a switching signal from the main CPU 61. Has become.

That is, the image data input from the CCD sensor 26 is amplified by an analog amplifier in an image correction unit 75 and converted into a digital signal by an A / D converter before entering an image processing circuit 65. At this time, the main CPU
The switching unit 100 is switched to the image correction unit 75 by 61.

Thus, in the image processing circuit 65, shading correction is first performed by the shading correction circuit 101, and then smoothing processing is performed by the LPF (low-pass filter) 102. Thereafter, the edge is emphasized by an HPF (high-pass filter) 103, and then the image is enlarged / reduced by an enlargement / reduction unit 102. Thereafter, tone processing such as error diffusion and dither processing is performed by the tone processing unit 105, and then the buffer memory 1
After being recorded in 06, it is read out again and output to the laser driver 83 of the printer unit 6.

The first test image generating circuit 108
A circuit for generating test image data (test image (1)) generates, for example, image data in which the gradation changes for each of a plurality of lines, and outputs this data from the CCD sensor 26 (image correction unit 75). Switching unit 100 instead of image data
After being input to the shading correction circuit 101 via the main CPU 61 (controlled by the main CPU 61), the image data is passed (through) or processed through each of the image processing blocks 101 to 106 in the same manner as the image processing for the image data from the CCD sensor 26. , To the printer unit 6.

Each of the image processing blocks 101 to 106
Are input to the selection unit 110, and one of them is used as a test output depending on the content of the search output selection signal SEL from the delay / comparison control unit 107.
11 is output.

The second test image generation circuit 109
The same test image is generated by a circuit configuration similar to that of the first test image generation circuit 108, and the test image (2), which is the output image, is sent to the data comparison unit 111. As a result, the data comparison unit 111 sets the delay / comparison control unit 1
The selection unit 110 within a period determined by the enable signal CPEN from 07 (corresponding to one line to the last line of the test image for each of the image processing blocks 101 to 106).
And the second test image generation circuit 109
Are compared with each other, and the result is output to the main CPU 61 as a determination flag.

The first test image generation circuit 108 and the second test image generation circuit 109 are reset by clear signals CL1 and CL2 from the delay / comparison control unit 107, respectively. Is not output.

The delay / comparison control unit 107 is a main CPU 6
The register setting for selecting the inspection position from 1 and the start setting for controlling the start of the inspection are possible.
Based on the image transmission clock CLK supplied from U61, the inspection output selection signal SEL to the selection unit 110, the clear signals CL1 and CL2 of the first test image generation circuit 108 and the second test image generation circuit 109, and data comparison Part 11
1 to output an enable signal CPEN.

Each of the image processing blocks 101 to 106
The first test image generation circuit 108 and the second test image generation circuit 109 are synchronized with the image transmission clock CLK supplied from the main CPU 61.

Here, each of the image processing blocks 101 to 101
Reference numeral 106 designates a pass-through mode for passing data without changing data contents. In the present invention, the pass-through mode is used.

FIG. 4 shows the first test image generating circuit 108.
3 shows a block configuration of a (second test image generation circuit 109).

The first test image generating circuit 108
H counter (horizontal direction counter) 112, V counter (vertical direction counter) 113, horizontal synchronization signal generation unit 11
4. Output data generation unit 115, inhibit circuit 116
It consists of.

The H counter (horizontal direction counter) 112 and the V counter (vertical direction counter) 113 are both synchronized with the image transfer clock CLK from the main CPU 61, and the H counter 112 counts the total number of pixels in the horizontal scanning direction. When the value is counted, it returns to the initial value, and at the same time, the V counter 113 counts up by one (one line addition).

The contents of the H counter 112 are sent to the horizontal synchronizing signal generator 114, which generates a horizontal synchronizing signal indicating a valid period during which data is actually output in one line. The output data generation unit 115 outputs output data corresponding to the value of the V counter 113.

However, during the period when the horizontal synchronizing signal is “L”,
The inhibit circuit 116 controls the output data from the output data generator 115 so that the output data becomes “0”.
Since these are basically composed of a small number of counters, they can be realized at low cost.

The horizontal synchronizing signal from the horizontal synchronizing signal generator 114 is supplied to the shading correction circuit 101 together with the test image, and thereafter, the LPF (low-pass filter) 102, HPF (high-pass filter) 103, the enlargement / reduction unit 104, The data is supplied to the buffer memory 106 via the gradation processing unit 105 sequentially. The horizontal synchronizing signal is delivered to the next part after being delayed by each part.

FIG. 5 shows the first test image generating circuit 108.
(A) to (d) of FIG. 6 and (a) to (d) of FIG. 7 show timing charts of generation of the image pattern. ing.

The image pattern used in the present invention is a pattern in which the density of the first image data is 55 (H) and the density is increased for each of a plurality of lines as shown in the image on the original in FIG. .

As shown in the timing charts of FIGS. 6 (a) to 6 (d) and FIGS. 7 (a) to 7 (d), the horizontal synchronizing signal is output four clocks after the clear signal CL becomes "H". It is enabled and data output is started. Here, AB indicates the first line from which the output of the image data starts, and among them, the image data (55H) is actually output during A'-B '. On the other hand, CD indicates the timing of the portion where the image data changes from 55 (H) to AA (H).

FIGS. 8A to 8E show the test image (1) in the embodiment of FIG. 3 and this test image (1) is the switching unit 100, the shading correction circuit 101, and the LPF1.
02 shows the timing relationship with the output (a) of the enlargement / reduction unit 104 when passing through the HPF 103. Here, the enlargement / reduction unit 1 for the test image (1) is used.
The output (a) of No. 04 is delayed by 4 CLK (T).

FIGS. 9A to 9I are timing charts for checking the data content and output timing of the output (a) of the enlargement / reduction unit 104 in the embodiment of FIG.

The inspection is performed by comparing the output of the enlargement / reduction unit 104 with the data of the test image (2). Here, the test image (1) is switched by the switching unit 100 and the shading correction circuit 10.
1, it is known in advance that a delay of 4 CLK (T) occurs before passing through the LPF 102 and the HPF 103 to reach the output (a) of the enlargement / reduction unit 104, so that the first test image generation circuit 108 4C after starting
The delay / comparison control unit 107 is configured such that the timing when the clear signal CL2 of the second test image generation circuit 109 becomes “H” is delayed by 4 CLK so that the second test image generation circuit 109 starts with a delay of LK. The settings are made in.

FIG. 10 shows the configuration of the data comparison unit 111 for comparing the image data to be inspected (here, the output (a) of the enlargement / reduction unit 104) with the test image (2) which is the expected value. (A) to (e) of FIG. 11 show timing charts of the inspection.

As shown in FIG. 10, the data comparing section 111 is composed of an exclusive OR circuit 121 and a comparison result holding section 122. The exclusive OR circuit 121 performs an exclusive OR operation on the test image (2) from the second test image generation circuit 109 and the output (a) of the enlargement / reduction unit 104 from the selection unit 110, and when they match, “ L ”and“ H ”when they do not match are output to the comparison result holding unit 122. The comparison result holding unit 122 operates while the enable signal CPEN from the delay / comparison control unit 107 is “H”.
When an “H” signal is supplied from the exclusive OR circuit 121, “H” is held as a determination flag. This determination flag is output to the main CPU 61.

In the present invention, each image processing block 101
Since the outputs of .about.106 are set to the pass mode, the data comparison unit 111 has a difference since the output (a) of the enlargement / reduction unit 104 and the content of the test image (2) should be the same when the contents are normal. If the enable signal CP
If EN is in the period of “H”, it is determined that an error has occurred, and the determination flag is held.

The inspection is started by setting the register of the main CPU 61. Here, since a difference occurs in the third line, "H" is held in the judgment flag at that time. The inspection is performed for a plurality of lines. When the enable signal CPEN becomes “L” (until the last line), the comparison is completed, and the main CPU 61 checks the determination flag of the comparison result by register access.

As a result, when it is determined that the output (a) of the enlargement / reduction unit 104 is different from the content of the test image (2), one of the image processing blocks 101 to 104 generates an error (a simple through Can not be determined).

According to the above method, each image processing block 10
Regarding the operations 1 to 106, it is possible to check the coincidence between the horizontal synchronization timing and the bit data of the data content.

A check is made for all lines for each of the image processing blocks 101-106.

FIG. 12 shows the main CPU 6 for performing an inspection.
3 is a flowchart of control by No. 1. The inspection can be started by an instruction from the user, but a method of performing an inspection each time the number of copies reaches a prescribed number of sheets, a method of conducting an inspection every time a prescribed operation time is reached by a timer, or the like can be adopted. Here, the inspection is performed every time the number of copies reaches a specified number.

First, when the number of copies reaches a prescribed number (ST1), the output to be inspected is set to the first block (ST2). After that, the test start is set in the register (ST3), and the end of the data comparison is waited (ST4). When the data comparison is completed, the determination flag is checked (ST5), and if there is a data mismatch (ST6), an error status is returned to the main CPU 61 to end the inspection (ST7). If there is no data mismatch (ST6), it is determined whether there is a next inspection target (ST8). If there is a next inspection target, the output of the block is set as the inspection target (ST9). Set (ST3).

As described above, the test image data (the pattern in which the density changes in units of a plurality of lines) generated by the first test image generation circuit is input to the image processing system instead of the input image data from the scanner unit. Then, each block of the image processing is passed in the through mode, and data to be inspected is selected from the respective outputs. At this time, the output of each image processing block is delayed with respect to the output timing of the first test image generation circuit.

As a result, the second test image generation circuit whose start is delayed from the first test image generation circuit by the delay of the selected data to be inspected (the generation pattern is the same as that of the first test image generation circuit) By comparing with the output of the data line, it is possible to determine whether the data transfer timing and the bit check of the data line are OK.

Thus, the self-inspection of the image processing system (each image processing block) can be performed with an inexpensive configuration.

[0083]

As described in detail above, according to the present invention, it is possible to provide an image processing circuit capable of performing a self-inspection with an inexpensive configuration and an image forming apparatus using this image processing circuit.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a schematic configuration of a digital copying machine according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a schematic configuration of a digital copying machine.

FIG. 3 is a block diagram illustrating a schematic configuration of an image processing circuit.

FIG. 4 is a block diagram illustrating a schematic configuration of a test image generation circuit.

FIG. 5 is a diagram showing an image pattern generated from a test image generation circuit.

FIG. 6 is a diagram showing a timing chart of generation of an image pattern in a test image generation circuit.

FIG. 7 is a diagram showing a timing chart of generation of an image pattern in a test image generation circuit.

FIG. 8 shows a test image (1) and an output of an enlargement / reduction unit (a).
FIG. 6 is a diagram showing a timing relationship with the timing chart.

FIG. 9 is a diagram showing a timing chart when inspecting the content and output timing of data of output (a) of the enlargement / reduction unit.

FIG. 10 is a block diagram illustrating a schematic configuration of a data comparison unit.

FIG. 11 is a diagram showing a timing chart of an inspection in a data comparing unit.

FIG. 12 is a flowchart illustrating the operation.

[Explanation of symbols]

 Reference Signs List 4 scanner unit 6 printer unit 26 CCD sensor 60 main control unit 61 main CPU 65 image processing circuit 75 image correction unit 100 switching unit 101 shading correction circuit 102 LPF 103 HPF 104 enlargement / Reduction section 105 ... Grayscale processing section 106 ... Buffer memory 107 ... Delay / comparison control section 108 ... First test image generation circuit (first output means) 109 ... Second test image generation circuit (Third output means) 110: selection section (selection means) 111: data comparison section (judgment means)

Claims (6)

[Claims] An image processing circuit for performing image processing in a plurality of processing stages, a first output means for outputting predetermined image data, and an image data output from the first output means, And a second output unit for outputting image data from each processing stage by supplying the image data by the supplying unit, respectively, and a processing stage for determining whether the image data is normal or not. Selecting means for selecting image data from the second output means; and outputting the image data from the processing stage selected by the selecting means with respect to the output from the first output means, A third output unit that outputs predetermined image data; and a comparison between the image data output by the third output unit and the image data selected by the selection unit.
Determining means for determining whether or not the processing of the processing stage selected by the selecting means is normal. 2. An image processing circuit for performing image processing in a plurality of processing stages, wherein: first output means for outputting predetermined image data; and image data output from the first output means, And a second output unit for outputting image data from each processing stage by supplying the image data by the supplying unit, respectively, and a processing stage for determining whether the image data is normal or not. Selecting means for selecting image data from the second output means; and delaying the output from the first output means by a time corresponding to the time when the image data is output from the processing stage selected by the selecting means. A third output unit that outputs the predetermined image data; and a comparison between the image data output by the third output unit and the image data selected by the selection unit.
Determining means for determining whether or not the processing of the processing stage selected by the selecting means is normal. 3. An image processing circuit for performing image processing in a plurality of processing stages, wherein: first output means for outputting predetermined image data; and image data output from the first output means being passed through. Supply means for sequentially supplying the image data from the processing steps, second output means for outputting the image data from each processing step by supplying the image data by the supply means, and processing for determining whether the image data is normal or not. Selecting means for selecting image data from the second output means corresponding to a step; and outputting image data from the processing step selected by the selecting means with respect to the output from the first output means. A third output unit that outputs the predetermined image data at the timing; and an image data output by the third output unit and an image data selected by the selection unit. Determining means for determining whether or not the processing at the processing stage selected by the selecting means is normal, based on whether or not they match, an image processing circuit comprising: 4. An image forming apparatus having an image processing circuit for performing image processing in a plurality of processing stages and forming an image on the image forming medium from the image data from the image processing circuit, wherein the image processing circuit First output means for outputting image data of the following; supply means for sequentially supplying the image data output from the first output means through the processing steps; supply of image data by the supply means; A second output unit for outputting image data from each processing stage, a selection unit for selecting image data from the second output unit corresponding to a processing stage for determining whether or not the image data is normal; A third output unit that outputs the predetermined image data at a timing when the image data is output from the processing stage selected by the selection unit with respect to the output from the output unit; By comparison with the image data selected by the third image data and the selection means output by the output means,
An abnormality determination function including a determination unit configured to determine whether or not the processing of the processing stage selected by the selection unit is normal; wherein the number of images formed on the image forming medium is a predetermined number, An image forming apparatus comprising: an execution unit that executes an abnormality determination function of an image processing circuit. 5. An image forming apparatus having an image processing circuit for performing image processing in a plurality of processing stages and forming an image of image data from the image processing circuit on an image forming medium, the image processing circuit comprising: First output means for outputting image data of the following; supply means for sequentially supplying the image data output from the first output means through the processing steps; supply of image data by the supply means; A second output unit for outputting image data from each processing stage, a selection unit for selecting image data from the second output unit corresponding to a processing stage for determining whether or not the image data is normal; A third output unit that outputs the predetermined image data at a timing when the image data is output from the processing stage selected by the selection unit with respect to the output from the output unit; By comparison with the image data selected by the third image data and the selection means output by the output means,
A determination unit configured to determine whether or not the processing of the processing stage selected by the selection unit is normal; and when the operation time of image formation on the image forming medium reaches a predetermined time. And an execution unit for executing an abnormality determination function of the image processing circuit. 6. An image forming apparatus having an image processing circuit for performing image processing in a plurality of processing stages and forming an image of the image data from the image processing circuit on an image forming medium, the image processing circuit comprising: First output means for outputting image data of the following; supply means for sequentially supplying the image data output from the first output means through the processing steps; supply of image data by the supply means; A second output unit for outputting image data from each processing stage, a selection unit for selecting image data from the second output unit corresponding to a processing stage for determining whether or not the image data is normal; A third output unit that outputs the predetermined image data at a timing when the image data is output from the processing stage selected by the selection unit with respect to the output from the output unit; By comparison with the image data selected by the third image data and the selection means output by the output means,
A determination unit for determining whether or not the processing of the processing stage selected by the selection unit is normal; and forming an image on the image formation medium and performing the next image formation on the image formation medium. An image forming apparatus comprising: an execution unit that executes an abnormality determination function of the image processing circuit during image formation.