JP2001102592A - Thin film transistor and method for fabrication thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To fabricate a thin film transistor for use in liquid crystal display LCD or memory integrated circuit having a large area and good characteristics at low cost, and to provide a fabrication method thereof. SOLUTION: High temperature annealing can be carried out for homogenizing a poly-Si semiconductor layer by employing an Ag alloy in the gate electrode and Ta or SiNX in an underlying film thus fabricating a thin film transistor having good transistor characteristics at a high yield.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an active matrix type liquid crystal display (LCD) and a thin film transistor (Thin Film Transistor) used for a memory integrated circuit.
or: hereinafter abbreviated as TFT) and its manufacturing method.

[0002]

2. Description of the Related Art A TFT using amorphous silicon (a-Si) and a polycrystalline silicon (p-S) are used for a TFT used for driving an image display of a liquid crystal TV or a personal computer.
Some use i). p-Si TFT is a-Si TFT
It is expected that a higher definition can be achieved in terms of characteristics than a TFT, and a driver circuit can be formed on a substrate, so that a reduction in cost can be realized.

There are a high temperature type and a low temperature type p-Si TFT depending on the temperature at which Si is polycrystallized. Since a low-temperature type uses a glass substrate, it is possible to increase the area. In order to realize the large area, a low-resistance wiring material is required, and Al, Cu, and the like correspond thereto. A gate wiring structure of a TFT array when Al is used as a wiring material will be described with reference to a cross-sectional view of the TFT array shown in FIG.

[0004] SiO 2 is formed on a light-transmitting substrate 1 such as glass._TwoOr
A base insulating film 2 made of
Using an excimer laser
Crystallization to form polysilicon 3 to be a semiconductor layer
Have been. SiO on top _TwoGate insulating film 4 made of
Is formed by atmospheric pressure CVD, and a conductive film made of Al
The gate electrode 5 is processed into a predetermined shape. Polysilico
Is implanted into the impurity layer 3 by ion doping.
As a result, the channel region 31 is formed in the polysilicon layer 3.
Source region 32 and drain region 33 are formed
Have been. An interlayer insulating film 6 made of SiO2 is formed thereon.
A film is formed, and a contact hole 7 is opened and made of Al
Source / drain electrodes 8 and 9 are formed.

[0005]

However, in the above-mentioned conventional structure, since the gate electrode is formed and impurities are ion-implanted by the ion doping method, the Si film is damaged at the time of the implantation and the original TFT characteristics can be obtained. There was no problem. Further, there is a problem that the implanted impurity does not show a function as a dopant as it is.

In order to solve these problems, after performing ion implantation, heat treatment at 500 ° C. or more and 620 ° C. or less is performed from above the gate wiring to release Si damage at the time of ion implantation and activate the dopant. When Al is used for the gate wiring material, the melting point of Al is low.
It was difficult to perform a heat treatment at a temperature of 00 ° C. or higher. As a high melting point metal having a heat resistance of 500 ° C. or more, T
When a or Ti is used as a gate electrode, annealing at 620 ° C. is possible, but since the resistance is about one digit higher than that of Al, it is not possible to create a high-resolution large-area TFT array of 10 inches or more. It was difficult. Further, when Ag or Ag-Pd having a high melting point and a low resistance is used, there is a problem that adhesion to SiO2 as a gate insulating film is poor.

SUMMARY OF THE INVENTION An object of the present invention is to solve the problems of the prior art and to provide a gate wiring structure of a thin film transistor capable of forming a large-area display having good operation characteristics and high stability, that is, a high yield. .

[0008]

In order to achieve the above object, a thin film transistor according to the present invention has a Si semiconductor layer comprising an active layer and a source / drain region, a gate insulating film comprising SiO _2, and a source / aluminum comprising Al as a main component. In a thin film transistor having a drain electrode, a conductive thin film material containing Ag as a main component is used as a gate electrode, and a gate insulating film SiO ₂ exists below the gate electrode via an intermediate layer such as Ta or SiN _x. Have a configuration. By using a conductive thin film containing Ag as a main component, it is possible to form a gate electrode which has low resistance and is not deteriorated by annealing at 620 ° C. Also,
The presence of the intermediate layer improves the adhesion between the conductive thin film containing Ag as a main component and the gate insulating film.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A gate wiring of a TFT array according to claim 1 of the present invention comprises an active layer containing almost no impurities,
A thin film transistor including a semiconductor layer including a source / drain region containing an impurity serving as a donor or an acceptor, a gate electrode, a gate insulating layer, and a source / drain electrode, wherein Ta, Ti, or the like is formed on the gate insulating layer SiO _2. And a conductive thin film containing Ag as a main component is formed thereon. The conductive thin film material containing Ag as a main component is Zn, Cu,
It is characterized in that it contains at least two kinds of additives, that is, one or more kinds selected from Ni, Co, Fe, Cr, Mn, and Ti, and Pd as a second additive.

[0010] The gate wiring of a TFT array according to a second aspect of the present invention, SiN _x or SiO is formed on the gate insulating film SiO ₂
An insulating film such as N is laminated, and a conductive thin film mainly composed of Ag is formed thereon. With the above wiring structure, a thin film transistor with a high yield can be obtained.

According to a third aspect of the present invention, in the gate wiring of the TFT array, the conductive thin film mainly composed of Ag contains Cu as a first additive in an amount of 0.5 at% to 2.0 at%, Pd is added as an additive of 0.5 at% or more to 1.0 at%.
at% or less.

According to a fourth aspect of the present invention, the gate wiring of the TFT array has an electric resistance of 4% by a heat treatment at 500 ° C. or more and 620 ° C. or less.
4. The method for manufacturing a gate wiring structure according to claim 1, wherein the resistance is set to μΩ · cm or less. By performing the annealing at 600 ° C., the activation of the doping material and the doping damage are removed, and the low-temperature polysilicon T having high mobility is removed.
An FT array can be created.

According to a fifth aspect of the present invention, there is provided a liquid crystal display device having a TFT array having the above-mentioned wiring structure.

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a process sectional view of Embodiments 1 and 2, and FIG. 3 is a sectional view of a TFT array showing a conventional embodiment. FIG. 2 shows current-voltage characteristics of a thin-film transistor manufactured by a conventional method and current-voltage characteristics of thin-film transistors manufactured in Embodiments 1 and 2 of the present invention.
In the present embodiment, the source / drain electrodes have A
An example using l has been shown. Therefore, the heat treatment was performed before forming the source / drain electrodes. However, the present invention
The material is not limited to this, and a high melting point metal can be used for the source / drain electrodes. In that case, the heat treatment may be performed after the source / drain electrodes are formed.

(Embodiment 1) A method of manufacturing a thin film transistor according to an embodiment of the present invention will be described below with reference to the drawings.

After a base insulating film 2 made of SiO _{2 is} formed on a light-transmitting substrate 1 such as glass by a normal pressure CVD method so as to have a thickness of 200 nm at 450 ° C., a-Si: H
Is formed at 270 ° C. with a plasma CVD apparatus so as to have a film thickness of 50 nm, and is etched and patterned into a predetermined shape. Crystallization is performed using a XeCl excimer laser having a wavelength of 308 nm, and polysilicon 3 serving as a semiconductor layer is
Is formed (FIG. 1A).

Next, a gate insulating film 4 made of SiO _{2 is} formed on the polycrystalline silicon semiconductor layer 3 at 300 ° C. to a thickness of 100 nm by ECR-CVD. After a Ta film 5 is formed to a thickness of 50 nm by sputtering, Ag-1%
A Pd-1% Cu film is formed to a thickness of 150 nm. The Ag electrode and the base film Ta are formed into a predetermined shape by photolithography and etching to form the gate electrode 6 (FIG. 1).
(B)).

Impurities such as phosphorus and boron are ion-implanted into the polycrystalline silicon layer 3 by ion doping using the gate electrode 6 as a mask, so that the source region 32 and the source region 32 are sandwiched between the polycrystalline silicon layer 3 with the channel region 31 interposed therebetween. A drain region 33 is formed. Then 600 ℃ in nitrogen atmosphere
Heat treatment is performed for one hour (FIG. 1C).

Thereafter, an interlayer insulating film 7 made of SiO _{2 is} formed to a thickness of 400 nm by a normal pressure CVD method. A contact hole 8 is opened (FIG. 1 (d)). Finally, a Ti film and an Al film are formed to have a thickness of 80 nm and 350 nm, respectively. The Ti and Al films are formed into a predetermined shape by dry etching and wet etching, respectively, to form source / drain electrodes 9, thereby completing a polycrystalline silicon TFT (FIG. 1E).

Various modifications of the present invention are possible. For example, although polycrystalline silicon is used as the semiconductor, single crystal silicon, a polycrystal of an Si—Ge compound, or a single crystal may be used. Although the film thickness is set to 50 nm, the thickness is not limited to this and may be 10 nm or more for forming a channel. However, considering film forming stability and photoconductivity, 20n
m to 150 nm is desirable.

Further, as a method of forming a gate insulating layer, EC is used.
Although the R-CVD method was used, SiO ₂ can be deposited by normal pressure CVD, sputtering, low pressure CVD, plasma CVD, or the like. In addition, as the source / drain electrodes, in addition to the above, Al alloy, Ta, Cr, Ti, Mo, Mo-Ta
Alloys, Mo-W alloys, Cu, various metals such as silicide, and their laminated films may be used, but from the viewpoint of resistance value, A
It is desirable to contain an alloy and Cu.

Although Ta was used as a base film of the gate electrode this time, TiN or Cr may be used.

For comparison, as a conventional configuration, the gate electrode was made of Al, the gate electrode was made of Ag, and the gate electrode was made of SiO.
Those directly laminated on ₂ were also prepared. The former is 600
After annealing at ℃, Al of the gate electrode was deteriorated on the surface or cracked, and could not be used as an electrode. Therefore, it was necessary to lower the annealing temperature to 450 ° C. to manufacture a TFT array. In the latter case, the underlying film is made of Si.
Because of O ₂ , the Ag alloy film of the gate electrode peeled off during the TFT array process. On the other hand, in the case of manufacturing with the configuration of this example, even after annealing at 600 ° C., the TFT array could be completed without the surface deterioration or cracking of the Ag—Pd—Cu film of the gate electrode. Therefore, the transistor characteristics in the substrate were stabilized, and the yield was improved. Also, there was almost no deterioration in transistor characteristics due to the reliability test.

Table 1 shows the evaluation results of various Ag alloys after the vacuum heat treatment at 600 ° C.

[0025]

[Table 1]

As apparent from Table 1, when the content of Pd is 0.5 at% or more and 1.5 at% or less and the content of Cu is 0.5 at% or more and 2.0 at%, 600
After the heat treatment step at a temperature of not less than ° C., the electric resistance is 4 μΩ · cm or less, and the corrosion resistance and workability are good.

In the present invention, the reason why the heat treatment temperature is limited to 500 ° C. or more and 620 ° C. or less is that if the heat treatment temperature is less than 500 ° C., the effect of the heat treatment is hardly observed.
If the temperature is higher than ° C., the heat resistance of the glass substrate becomes a problem.

(Embodiment 2) A method of manufacturing a thin film transistor according to an embodiment of the present invention will be described below with reference to the drawings.

After a base insulating film 2 made of SiO _{2 is} formed on a light-transmitting substrate 1 such as glass by a normal pressure CVD method so as to have a thickness of 200 nm at 450 ° C., a-Si: H
Is formed at 270 ° C. with a plasma CVD apparatus so as to have a film thickness of 50 nm, and is etched and patterned into a predetermined shape. Crystallization is performed using a XeCl excimer laser having a wavelength of 308 nm, and polysilicon 3 serving as a semiconductor layer is
Is formed (FIG. 1A).

Next, a gate insulating film 4 made of SiO _{2 is} formed on the polycrystalline silicon semiconductor layer 3 by ECR-CVD at 100 ° C. to a thickness of 100 nm. After forming a SiN _x film 5 to a thickness of 50 nm by plasma CVD,
A g-1% Pd-1% Cu film is formed to a thickness of 150 nm. The Ag electrode and the SiN _x film are formed into a predetermined shape by photolithography and etching to form the gate electrode 6 (FIG. 1B).

Impurities such as phosphorus and boron are ion-implanted into the polycrystalline silicon layer 3 by ion doping using the gate electrode 6 as a mask, so that the source region 32 and the source region 32 are sandwiched between the polycrystalline silicon layer 3 with the channel region 31 interposed therebetween. A drain region 33 is formed. Then 600 ℃ in nitrogen atmosphere
Heat treatment is performed for one hour (FIG. 1C).

After that, an interlayer insulating film 7 made of SiO _{2 is} formed to a thickness of 400 nm by a normal pressure CVD method. A contact hole 8 is opened (FIG. 1 (d)). Finally, a Ti film and an Al film are formed to have a thickness of 80 nm and 350 nm, respectively. The Ti and Al films are formed into a predetermined shape by dry etching and wet etching, respectively, to form source / drain electrodes 9, thereby completing a polycrystalline silicon TFT (FIG. 1E).

In the present invention, SiN _x is used as the base film of the gate electrode in this case, but SiON may be used.

When a thin film transistor is manufactured by the manufacturing method of the present invention, as shown in FIG. 2, the current when the n-channel portion is turned on (gate voltage 10 V) is improved by one digit as compared with that manufactured by the conventional method of FIG. And the angle of the rising curve was steep.

[0035]

According to the present invention, since an Ag alloy is used for the gate electrode, it has low resistance and heat resistance.
Annealing can be performed at a temperature around 00 ° C. Further, the yield of the process is improved by using a base film of an Ag alloy such as Ta or SiN _x to improve the adhesion to the base. By performing the annealing, the damage at the time of doping of the semiconductor layer can be recovered and activated, and the interface between the polysilicon film and the gate insulating film SiO ₂ can be improved. Therefore, transistor characteristics and reliability can be improved.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view of each of main processes for describing Embodiments 1 and 2 of the present invention.

FIG. 2 is a diagram showing current-voltage characteristics of a thin film transistor according to a conventional example and the present invention.

FIG. 3 is a schematic cross-sectional view of each main process for explaining a conventional technique.

[Explanation of symbols]

1 translucent glass substrate 2 underlying insulating film 3 poly-Si semiconductor layer 4 a gate insulating film (SiO ₂₎ 5 base film Ta and SiN _x, etc. 6 gate electrode (Ag-Pd-Cu or Ag-Pd-
Ti) 7 Interlayer insulating film (SiO ₂ ) 8 Contact hole 9 Source / drain electrode (Al / Ti) 31 Channel region 32 Source region 33 Drain region

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2H092 GA17 GA25 GA29 GA34 HA28 JA24 JA32 JA37 JA41 JA46 KA04 KA10 KB25 MA05 MA07 MA13 MA17 MA19 MA27 MA29 MA30 NA18 NA21 NA29 4M104 AA09 AA10 BB02 BB04 BB05 BB06 BB18 BB18 BB18 BB17 BB25 BB26 BB27 BB28 BB30 CC01 DD02 DD06 DD37 DD43 EE17 GG09 GG14 HH09 HH16 5F110 AA03 AA17 BB01 CC02 DD02 DD13 DD24 EE01 EE02 EE04 EE05 EE14 EE44 FF02 FF03 FF28 FF29 GG01 FF30 GG30 NN04 NN23 NN25 PP03 PP04

Claims (6)

[Claims] 1. An active layer and a source / drain region
Si semiconductor layer and SiO _TwoGate insulating film consisting of
Thin film transistor with source and drain electrodes as main components
A metal film laminated on the gate insulating film.
Then, on the metal film, Ag is used as a main component,
Zn, Cu, Ni, Co, Fe, Cr, Mn,
At least one selected from Ti and Pd as a second subcomponent
The conductive thin film material containing at least
Thin film transistor characterized by being laminated as
Ta. 2. An active layer and a source / drain region
Si semiconductor layer and SiO _TwoGate insulating film consisting of
Thin film transistor with source and drain electrodes as main components
An insulating film laminated on the gate insulating film.
Then, on the insulating film, a first sub-product
Zn, Cu, Ni, Co, Fe, Cr, Mn,
At least one selected from Ti and Pd as a second subcomponent
The conductive thin film material containing at least
Thin film transistor characterized by being laminated as
Ta. 3. Cu is 0.5 at% or more and 2.0 at% or less as a first subcomponent, and Pd is 0.5 a as a second subcomponent.
The thin film transistor according to claim 1, wherein the content of the thin film transistor is not less than t% and not more than 1.5 at%. 4. An electric resistance of a conductive thin film material containing Ag as a main component is set to 4 μΩ · by heat-treating the gate wiring of the thin film transistor according to claim 1 at 500 ° C. or more and 620 ° C. or less. cm or less. 5. A liquid crystal display device comprising the thin film transistor according to claim 1. 6. A method of manufacturing a liquid crystal display device comprising the thin film transistor according to claim 1, wherein the gate wiring of the thin film transistor is subjected to a heat treatment at 500 ° C. or more and 620 ° C. or less to form Ag. A method for manufacturing a liquid crystal display device, characterized in that the electrical resistance of a conductive thin film material mainly composed of: 4 μΩ · cm or less.