JP2001102576A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an insulated-gate type semiconductor device where its cells per unit area can be integrated highly densely and the electrical characteristics of the portions of its cells activated as channels can be also made uniform. SOLUTION: A semiconductor wafer having a crystalline-plane orientation of (111) is prepared. Trenches 32 are formed in its surface portion. The plan view of sidewalls 33 of the semiconductor layer of the wafer, which are sectioned by each trench 32, is a hexagonal pattern 30. A gate electrode is formed in each trench 32 to constitute a MOSFET element by using the pattern 30 as a unit cell. The crystalline planes of the sidewalls 33 of the trench 32 are, so selected that they are equivalent to each other in six planes. The typical example of each crystalline plane is the crystalline plane of (110) or the approximated one thereto.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device,
In particular, the present invention relates to an insulated gate semiconductor device having a trench structure.

[0002]

2. Description of the Related Art In recent vertical MOSFETs, a so-called trench type having a structure in which a gate electrode is buried in a trench is attracting attention because low on-resistance characteristics are easily obtained structurally. The outline of the structure and the manufacturing process of such a vertical MOSFET having a trench structure is disclosed in, for example, Japanese Patent Application Laid-Open Nos. 4-146,674 and 5-335,582.

An example of the structure of such a vertical MOSFET will be described with reference to FIG. A P-type channel region 12 is provided on the surface, and an N-type drain layer 11a, N +
A large number of trenches 13 are formed in the semiconductor substrate having the p-type drain layer 11b so as to reach the N-type drain layer 11a beyond the P-type channel region 12. A gate oxide film 14 is formed on the surface of the trench 13, and a gate electrode 15 made of polycrystalline silicon or the like is buried inside the gate oxide film 14. An N + source region 16 is provided. An insulating layer 17 is provided on the gate electrode 15,
A metal electrode 18 such as aluminum is provided on the entire surface of the cell region,
This insulating layer 17 insulates and separates the gate electrode 15 and the metal electrode 18. Then, the metal electrode 18 is connected to the source region 1.
6 and the channel region 12.

In a vertical MOSFET having such a structure,
By applying a voltage equal to or higher than a predetermined threshold to the gate electrode 15, N
Forming an inversion layer of the type, and forming a drain layer 11 of the N-type semiconductor substrate.
A current path is formed between a, 11b and the N + type source region 16. As a result, the source and the drain of the vertical MOSFET are turned on, and the voltage of the gate electrode 15 is set to be equal to or lower than the threshold value, thereby eliminating the N-type inversion layer in the channel region 12 and turning off the source and the drain of the vertical MOSFET. State. According to such a vertical MOSFET, since there is no junction type FET effect peculiar to the planar type vertical MOSFET, there is an advantage that its on-resistance can be reduced.

In the semiconductor industry, semiconductor wafers 19 having a plane orientation (100) as shown in FIG. 14 are frequently used for manufacturing semiconductor devices. Since the plane orientation is defined by the reciprocal of the coordinate value at which the plane intersects the coordinate axis, the plane orientation (100)
Means a crystal plane that intersects the x axis = (100) axis at “1” and intersects the y and z axes at infinity, ie, does not intersect.
Therefore, this silicon wafer 19 has a crystal face (1
00) is exposed, and a large number of semiconductor chips 2 are
0 is formed. Usually, the crystal orientation of OF (orientation flat) is the <100> direction. The semiconductor chips 20 each have a rectangular shape, and are arranged at equal intervals with a region to be a scribe line interposed therebetween. Also,
A number of semiconductor chips 20 are arranged so that the scribe lines are parallel to the OF (see the drawing).

FIG. 15 is an enlarged perspective view showing a state when a trench type MOSFET is manufactured on the semiconductor chip 20 of the (100) wafer 19.

The channel region 12 has a substantially square shape, and a large number of square channel regions 12 are arranged vertically and horizontally at regular intervals. Each channel region 12 is surrounded by a trench 13 having a constant width. That is, the trench 13 has a lattice shape. In each channel region 12, the source region 1
6 annularly surrounds the peripheral portion of the channel region 12. The source region 16 is exposed on the side wall of the trench 13.
Note that a region defined by the shape of one channel region 12 is referred to as a “unit cell”. The “pattern shape of the unit cell” means a shape formed by the sidewall of the trench 13. In this way, the OF surface is set to (100) on the (100) wafer,
When the unit cell has a rectangular shape, the channel region 1
The four side walls surrounding 2 are all crystal planes (100). Further, the bottom surface of the trench 13 is also a crystal plane (100). Reference numeral 11 denotes a semiconductor substrate.

[0008]

First Objective The on-resistance Rds (on) of a vertical MOSFET is inversely proportional to the number of cells per unit area. Therefore, increasing the number of cells that can be accommodated per unit area is an important issue in reducing the on-resistance Rds (on). However, there is a disadvantage that there is naturally a limit depending on the processing accuracy of the photoetching process. Accordingly, a first object of the present invention is to dramatically increase the number of unit cells that can be stored per unit area in a semiconductor device having a trench.

In order to achieve the first object, the inventor of the present application has studied a pattern arrangement as shown in FIG. This means that the unit cell pattern shape 21 is 6
The pattern 21 is a square (preferably a regular hexagon), and the patterns 21 are arranged at a cell interval a. The cell interval a is the distance from the point center of the hexagon to the point center, and a line connecting the point centers to the point center forms an equilateral triangle.

A regular hexagonal pattern arrangement is shown in FIG.
(1) enables a higher density cell arrangement than the conventional pattern arrangement shown in FIG. In the conventional pattern arrangement, the pattern shape 21 of the unit cell is a square, and the cell interval (cell pitch) a
This is the pattern arranged in. The line connecting the center of the point to the center of the point forms a square. The gate length GW is equal to the peripheral length of the pattern 21 (the sum of the lengths of the sides). When the area per unit cell (pattern 21) is simply compared with the same cell pitch a, the area of a regular hexagon is about 0.86 times that of a square. As a result, when the cell interval a is the same, the number of cells per unit area is about 1.1.
It can be increased 6 times.

Second Objective However, the hexagonal trench 13 is formed in the plane orientation (10
When formed on the semiconductor wafer 19 of 0), new crystallographic problems arise. That is, since the silicon single crystal crystallographically forms a cubic lattice, the crystal plane of the side wall of the trench 13 does not match the (100) plane. In addition, FIG.
The crystal plane of the side wall of the trench 13 located on each side 21a to 21f of the pattern 21 shown in FIG.

Since the electrical and electronic characteristics of the silicon surface are greatly dependent on the crystal orientation, the non-uniformity of the crystal planes on the side walls of the trench 13 is caused by the MOSFET.
This means that the electrical characteristics of the device become non-uniform with each side wall. For this reason, a side wall in which the drain current easily flows and a side wall in which the drain current hardly flows are generated.

Further, when the gate oxide film 14 is formed on the side wall of the trench 13 by thermal oxidation, the thickness of the gate oxide film 14 becomes uneven because the growth rate of the oxide film varies depending on the crystal orientation. The problem described above occurs. As a result, the threshold value Vt of the MOSFET is different on each side wall, and as shown in FIG. 9, the gate voltage Vg-drain current Id characteristic is deteriorated, the switching time is increased, and destruction due to current concentration occurs. There was a drawback that it was easier to do.

Therefore, a second object of the present invention is to eliminate crystallographic nonuniformity on the side wall of the trench 13 in the insulated gate semiconductor device in which the hexagonal trench 13 is formed.

[0015]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional disadvantages, and is directed to a semiconductor device in which a pattern is formed in a semiconductor substrate by trenches, in which the pattern is hexagonal. .

Further, the pattern is formed so that the electrical characteristics of the side walls of the trench are equal to each other, starting from the semiconductor substrate having the plane orientation (111).

[0017]

Embodiments of the present invention will be described below with reference to the drawings.

The first gist of the semiconductor device of the present invention is that a substantially hexagonal pattern is formed by the trench. The second gist is to use a semiconductor wafer having a plane orientation of (111). First, an example of a crystal orientation and a hexagonal pattern will be described.

First Pattern: FIG. 1 shows a first example of a hexagonal pattern 30 formed by trenches.
(A) is a top view, (B) is a perspective view.

On the surface of a silicon semiconductor substrate 51, a number of patterns 30 having the same shape and the same dimensions are arranged vertically and horizontally. The pattern 30 is a hexagon having an angle θ of 120 degrees plus or minus 10 degrees, and preferably a regular hexagon having an angle θ of 120 degrees. Multiple patterns 30
Are arranged such that the distance a from the center of the pattern 30 to the center is constant. When the pattern 30 is a regular hexagon, the lines connecting the centers are arranged to form a regular triangle 31. Each side of the hexagon is parallel to the side of the adjacent hexagon, and the distance b is all constant.

A trench 32 is formed on the surface of the substrate 51. The trench 32 is a groove dug vertically from the surface of the substrate 51. The trench 32 has a constant width (distance b)
It has a certain depth and is continuous in a lattice or honeycomb shape. Sidewalls 33 of the semiconductor layer 34 are formed along six sides of the pattern 30. The side wall 33 of the semiconductor layer is also the side wall of the trench 32. Each of the patterns 30 is independent in the shape of an island, and each of the islands is surrounded by a trench 32. Accordingly, the shape of the pattern 30 is formed by a portion 32 a where the surface of the semiconductor layer 34 and the trench 32 intersect. These trenches 32 can be obtained by selectively anisotropically etching silicon single crystal substrate 51.

Second pattern: FIGS. 2A and 2B are a plan view and a perspective view, respectively, for explaining the second pattern.
A first pattern is formed around trenches 32 around pattern 30.
The second pattern differs from the second pattern in that a trench 32 is formed inside the pattern 30. The trenches 32 are scattered in an island shape, and the periphery of each pattern 30 has a constant width.
A semiconductor layer 34 having a constant height surrounds the semiconductor layer. The depth of the trench 32 is constant. Similarly, the side wall 33 of the semiconductor layer 34 forms the hexagonal pattern 30. Since the shape, arrangement, intervals a, b, etc. of the pattern 30 are the same as those of the first pattern, description thereof will be omitted.

By these arrangements, the number of patterns 30 that can be stored per unit area can be greatly increased. The comparison between the square pattern and the hexagonal pattern 30 is shown in FIG.
6, the description is omitted.

Therefore, when a semiconductor device is formed such that a channel current flows along the side wall 33 of the semiconductor layer 34, the device can be made a large current device.

In the first and second patterns described above, a more suitable semiconductor device can be obtained by selecting the crystal plane of the side wall 33 of the semiconductor layer 34.
That is, the plane orientation of the substrate 51 is set to (111) corresponding to the hexagonal pattern 30. Note that the plane orientation (11
1) means that the x-axis = <100> axis intersects at 1 and the y-axis = <
It means a crystal plane that intersects the 010> axis at 1 and also intersects the z axis = <001> axis at 1.

FIG. 3 is a plan view of a cubic three-dimensional model of silicon single crystal observed from a direction perpendicular to the (111) plane. In this state, the (111) plane forms a horizontal plane, the surrounding six sides 35 to 40 form side walls perpendicular to the paper surface, and the others form surfaces inclined with respect to the paper surface. Each of the sides 35 to 40 forms a regular hexagon, and all of the side walls exposed to the sides 35 to 40 are formed of crystal faces (110).
It should be noted that the surface is an equivalent surface (mirror surface). For example, {110}, {101}, {011}
Are all crystal planes equivalent to the (110) plane. Equivalent crystal planes have the same electrical characteristics such as electron mobility, interface state, and silicon oxide film growth rate on the silicon surface.

FIG. 4 is a perspective view showing a hexagonal prism when a hexagonal prism is formed along each of the sides 35-40. The upper and lower surfaces of the hexagonal prism are (111) or its equivalent surface, and each side 35
The six vertical sidewalls corresponding to ~ 40 are all (110)
Is equivalent to

By utilizing such crystallographic characteristics, it becomes possible to form the crystal planes of the side walls 33 of the semiconductor layer 34 with the same plane. For example, in the example of FIG. 1B, if the hexagonal prism shown in FIG. 4 is arranged for each pattern 30, the (110) plane can be exposed on each side wall 33 of the semiconductor layer 34. It is possible. FIG.
In the example of (B), the (110) plane can be similarly exposed on each side wall 33.

In the actual manufacture of a semiconductor device, FIG.
The semiconductor wafer 41 having the plane orientation (111) shown in FIG. The wafer 41 has the (111) plane exposed on the surface, and has a large number of semiconductor chips formed on the surface. Although the orientation flat OF is set to the crystal orientation <110>, other orientations may be used. And
Each side 35 to 40 of the hexagonal pattern 30 has a crystal orientation <1
The pattern 30 is formed so as to be orthogonal to 10>. Thereby, the six side walls 33 of the semiconductor layer 34
Can be constituted by all (110) crystal planes (mirror planes). The fact that the crystal planes of the side walls 33 are equal to each other means that the mobility of electrons and the interface state in silicon are the same. This means that the same channel current can flow through all the three side walls 33.

The sides 35 to 40 of the pattern 30 need not necessarily be orthogonal to the crystal axis <110> direction. As shown by reference numeral 80 in FIG. 5, even when rotated in the range of 60 degrees left and right about the <111> axis, the side 35
The electrical characteristics of the crystal planes appearing along ４０40 are equal to each other.

The side wall 33 of the trench 32 may be inclined or bent in the depth direction in addition to a vertical flat surface. The condition is that all the six side walls 41 are processed into the same shape, that is, all the six side walls 33 have the same crystallographic electrical characteristics. Here, the crystallographic electrical characteristics refer to electron mobility, interface states, growth rate of a silicon oxide film, and the like on the silicon surface exposed on the side wall. Further, the bottom surface of the trench 32 may be a flat surface or a curved surface.

Third pattern: FIG. 6 shows a third pattern. The hexagon of the pattern 30 is not a regular hexagon but a hexagon in which the distance x in the horizontal direction in the drawing is longer than the distance y in the vertical direction in the drawing. In this case, the triangle 31 connecting the centers of the patterns 30 is an isosceles triangle, and the distance c between the two sides is equal. The distance a of the triangle is equal to the distance a in FIG. The side of the pattern 30 is parallel to the side of the adjacent pattern 30, and the distance b is constant. Even in such a shape, the electrical characteristics of all six surfaces can be made equal.

Hereinafter, an insulated gate semiconductor device using the above-described pattern will be described.

First Embodiment FIG. 7 is a plan view (A) and a cross-sectional view (B) showing a power MOSFET device using the first pattern of FIG. There is no fundamental change in the cross-sectional structure from the conventional one. The basic pattern arrangement shown in FIG. 1 is used.

That is, on one main surface side of the silicon semiconductor substrate 51 having the N-type drain layer 51a and the N + -type drain layer 51b, the P-type channel region 52 and the trench 32 extend beyond the P-type channel region 52 to the N-type. It is formed to a depth reaching the drain layer 51a. A gate oxide film 54 is formed on the surface of the trench 32 by thermal oxidation, and a gate electrode 55 made of polycrystalline silicon or the like is buried inside the gate oxide film 54. An N + type source region 56 is provided on the surface of the semiconductor layer partitioned by the trench 32. The source region 56 surrounds the inside of the peripheral end of the channel region 52 with a constant width. The surface of the channel region 52 surrounded by the source region 56 has a P + type contact region 5.
7 is formed.

On the gate electrode 55, an insulating layer 58 is formed by a CVD method or the like. 33 of the trench 32, that is, the outer periphery of the channel region 52 (equal to the outer periphery of the source region 56) defines a unit cell, and a region where a number of unit cells are arranged is called a cell region. At this time, the unit cell has the same shape and arrangement as the pattern 30 shown in FIG. That is, each unit cell has a hexagonal shape in plan view, and the periphery thereof is surrounded by the trench 32. The trench 32 has a constant width and a constant depth and is continuous. Further, the plurality of unit cells are arranged such that the cell pitch from the center to the center becomes uniform. These trenches 32 and patterns 30 are arranged in a honeycomb shape like a "honeycomb" as a whole.

A metal electrode 59 made of aluminum or the like is provided on the entire surface of the cell region.
And the metal electrode 59 are insulated and separated. The metal electrode 59 is electrically connected to the source region 56 and is also electrically connected to the channel region 52 via the contact region 57. The gate electrode 55 buried inside the trench 32 is continuous along the groove of the trench 32 and is connected to an electrode pad to which a gate potential can be externally applied at a location (not shown). A drain electrode (not shown) is formed on the back side of the N + type drain layer 51b. Also,
The metal electrode 59 is in contact with both the source region 56 and the contact region 57 via the contact hole 60 formed in the insulating film 58. Thus, each unit cell is connected to the metal electrode 5.
9 are connected in parallel to form a power element as a whole.

In this trench MOSFET, an N-type inversion layer is formed along the trench 32 in the P-type channel region 52 by applying an electric field to the gate electrode 55.
The drain layers 51a and 51b of the N-type semiconductor substrate 51 and N +
A current path is formed with the source region 56 of the mold. This current path is formed on all six surfaces.

By arranging hexagonal cells in this way, the cell density per unit area can be greatly improved. Accompanying this, the overall length of the gate width GW is greatly increased, so that the current capacity per unit area can be increased. Specifically, the same chip size as the conventional one (for example, 1.0 mm ×
1.0 mm), tens of thousands to hundreds of thousands of unit cells can be integrated.

In addition, the electron mobility in the channel region 32 can be made uniform by selecting the crystal planes of the side walls 33 so as to be equivalent to each other (for example, the (110) plane or a plane in the vicinity thereof). This means that the value of the current flowing through the channel region 32 can be equalized in all six crystal planes. Therefore, a MOSFET device having a high output and a small on-resistance Rds (on) can be obtained.

Further, by increasing the number of unit cells that can be stored per unit area, the number of contact holes 60 arranged for each unit cell can be increased. Therefore, the contact area between the metal electrode 59 and the source region 56 can be increased, and the contact resistance can be reduced. This produces an effect of further reducing the on-resistance Rds (on).

Such an apparatus can be manufactured, for example, by the following manufacturing method.

First Step: See FIG. 8A First, a silicon semiconductor substrate 51 having an N layer 51a to be a drain layer is prepared. A P-type diffusion layer serving as a channel region 52 is formed on the entire surface of the cell region of the N layer 51a by, for example, boron ion implantation.

Second Step: See FIG. 8B Next, the trench 32 is formed by etching the semiconductor substrate 51 to a depth that penetrates the channel region 52 and reaches the drain layer 51a. In this method, an opening is formed in an oxide film formed on the entire surface of the cell region by a photolithography process, and anisotropic gas etching is performed from the opening to form a trench 32.

Then, an oxide film layer is formed inside the trench 32 by dummy oxidation, and the defect layer on the surface of the silicon layer accompanying the formation of the trench 32 is removed by removing the oxide film layer. Thereafter, by performing gate oxidation, the trench 3
2, a gate oxide film 54 is formed.

Third Step: See FIG. 8C Next, a polycrystalline silicon film is deposited on the entire surface by CVD, so that the inside of the trench 32 is filled with polycrystalline silicon. Then, the polycrystalline silicon film is doped with phosphorus or boron, and the polycrystalline silicon film is turned into a conductive layer. Next, the polycrystalline silicon is etched back by, for example, isotropic gas etching. The etching of the polycrystalline silicon is stopped when the surface of the oxide film 54 on the channel region 52 is exposed, so that the gate electrode 55 embedded in the trench 32 is formed.

Fourth Step: See FIG. 8D Next, a P + type contact region 57 is formed. This is formed by forming an opening of a resist mask in a portion to be the contact region 57 by a photolithography process and implanting boron ions, for example. Next, an opening of a resist mask is formed in a portion to be a source region again by a photolithography process, and an N + type source region 56 is formed by ion-implanting, for example, arsenic (As). Since the source region 56 is formed by ion implantation using the upper end of the gate electrode 55 embedded in the trench 32 as a mask, a diffusion layer is formed in a self-aligned manner with respect to the gate electrode. This can reduce variations in characteristics such as the threshold voltage. Next, an insulating film such as NSG / BPSG is applied to the entire surface of the substrate 51, and an opening is formed by etching the insulating film so as to expose the source region and the contact region on the surface of the substrate 51 by a photolithography process. A layer 58 is formed.

Then, a metal material such as aluminum is sputtered to cover the entire surface of the substrate 51 with the metal material.
The source electrode 59 is formed on the entire surface of the cell region by photoetching and alloying. Further, a passivation film is applied to the entire surface of the chip, and a backing electrode (drain electrode) is formed on the back surface of the semiconductor substrate 51, whereby a vertical MOSFET at the wafer stage is completed (see FIG. 7B). The order in which the trenches 32 are formed after the channel region 52 and the source region 56 are formed may be used.

In the above manufacturing method, the gate oxide film 5
4 is formed by thermal oxidation of silicon. At this time, if the side walls 33 of the trench 32 are all formed of the (110) crystal plane or a crystal plane in the vicinity thereof, the growth rates of the gate oxide film 54 are equal on all six planes and uniform on all six planes. The gate oxide film 54 having the thickness t1 can be formed. This means that the threshold value Vt in the channel region 52 can be made equal in six planes. Therefore, since the mobility of electrons is uniform and the threshold value is uniform, there is no difference in the current value between the side walls 33, so that a high output can be obtained, and as shown in FIG. Thus, the effect that the rising characteristic of the threshold value Vt of the MOSFET element can be improved is produced.

Further, when the bottom surface of the trench 32 is constituted by the (111) plane, the following effects are produced. This is because the growth rate of the thermal oxide film when forming the gate oxide film 54 greatly depends on the crystal plane.

For example, a comparison of the growth rate of the thermal oxide film on each crystal plane under the conditions of dry oxidation at 1000 ° C. is as follows. (111)>(110)>(311)>(511)>
That is, the growth rate of the (111) plane is slightly higher than that of the (110) plane. Therefore, by performing a heat treatment at 900 ° C. or higher, preferably 1000 ° C. or higher as a condition for forming the gate oxide film, the thickness of the trench 32 becomes larger than the oxide film thickness t1 of the sidewall 33 in the trench 32 (see FIG. 7B).
The oxide film thickness t2 (FIG. 7B) on the bottom surface can be formed to be about 10% thicker. For example, when the thickness of the oxide film thickness t2 of the side wall 33 is 500 °, the oxide film thickness t2 of the bottom surface is 5 °.
It can be formed to about 50 °. The atmosphere may be oxidizing or non-oxidizing.

As described above, the oxide film thickness t on the bottom surface of the trench 32
2, that is, by increasing the thickness of the gate oxide film 54 at the position where the gate electrode 55 and the N layer 51a are opposed to each other, the capacitance Cgd between the gate and the drain can be reduced.
2 the breakdown voltage Vgd between the gate and the drain determined by
Can be increased. On the other hand, the oxide film thickness t1, ie, the gate electrode 5
Reducing the thickness of the gate oxide film 54 where the channel region 5 and the channel region 52 face each other means increasing the current driving capability of the MOSFET element. Therefore, these conflicting requirements can be satisfied at the same time.

In addition, by applying such a high-temperature treatment, the shoulder portion of the trench 32 (reference numeral 100 in FIG. 8B), that is, the shape in contact with the source region 56 can be processed into a rounded shape. Therefore, the coverage of the oxide films 54 and 58, the gate electrode 55, and the oxide film 58 is improved. It should be noted that even when a silicon nitride film SiN is used instead of the silicon oxide film, a difference in film thickness can be obtained similarly.

FIG. 10 shows a second embodiment of FIG.
FIGS. 3A and 3B are a plan view and a cross-sectional view illustrating a power MOSFET element using the pattern arrangement of FIGS. This is an example in which a gate electrode 55 is formed inside a hexagonal pattern 30.
The manufacturing method is the same as in FIG.

That is, in the silicon semiconductor substrate 51 having the P-type channel region 52 on the surface and the N-type drain layer 51a and the N + -type drain layer 51b under the P-type channel region 52, a large number of trenches 32 form the P-type channel region 52. It is formed to a depth that reaches the N-type drain layer 51a beyond that. A gate oxide film 54 is formed on the surface of the trench 32 by thermal oxidation, and a gate electrode 55 made of polycrystalline silicon or the like is buried inside the gate oxide film 54. An N + type source region 56 is provided on the surface of the semiconductor layer partitioned by the trench 32. Source region 56 surrounds gate electrode 55 near the periphery of channel region 52. On the surface of the channel region 52 surrounded by the source region 56, a P + type contact region 57 is formed.

On the gate electrode 55, an insulating layer 58 is formed by a CVD method or the like. The side walls 33 (equal to the inner periphery of the source region 56) around each gate electrode 55 define a unit cell, and a region where a number of unit cells are arranged is called a cell region.
The unit cell is equal to the shape and arrangement of the pattern 32. Also,
The side walls 33 of the channel region 52 are formed of crystal planes equivalent to each other as represented by the (110) plane. The channel region 52 is continuous like a honeycomb.

A contact hole 60 exposing P + contact region 57 and N + source region 56 is formed in insulating layer 58.
Is provided. Metal electrode 5 such as aluminum on the surface of the cell area
9 are provided and connected to the source region 56 and the contact region 57 via the contact hole 60.

The gate electrodes 55 are scattered inside the trench 32 and are connected in parallel by an aluminum electrode (not shown). Each gate electrode 55 is surrounded by a channel region 52, and the channel region 52 is continuous. On the surface of the channel region 52, source regions 56 each surrounding the gate electrode 55 are provided.
Is formed. Note that a configuration in which the P + contact region 57 is partially exposed at the contact hole 60 may be employed.

Third Embodiment The present invention in which a gate electrode is buried in a trench 32 is not limited to a vertical MOSFET. For example, an IGBT (Insulate Gate Bipolar)
Transistor).

FIG. 11 shows an example in which the present invention is applied to an IGBT device. The pattern 32 can be applied to both the examples shown in FIGS. N + layer 7 on P-type substrate 70
1 and an N-type layer 72, a P-type channel region 73 is formed on the surface of the N-type layer 72, a trench 74 is formed from the surface of the channel region 73 to the N-type layer 72, and a gate oxide film is formed inside the trench 74. 75 and a gate electrode 76, an annular N + source region 77 is formed on the surface of the channel region 73, and a P + contact region 7 is formed on the surface of the channel region 73.
8, a metal electrode 79 made of aluminum or the like is in electrical contact with the source region and the P + contact region.

In this device, a channel is formed in the channel region 73 on the inner wall of the trench groove 74 by a voltage applied to the gate electrode 76, a channel current flows from the source region 77 to the N-type layer 72, and the channel current is reduced to a P-type. It is configured to supply as a base current of a PNP transistor formed by the channel region 73, the N / N + layers 71 and 72, and the P + substrate 70. The IGBT uses the P
Since conductivity modulation occurs in the NP transistor, MOSF
ON resistance can be reduced as compared with the ET element. The relationship between the crystal planes is the same as in the first and second embodiments.

Fourth Embodiment: FIG.
2 shows a trench type MOSFET device in a case where the shape of a second side wall 33 is curved. The pattern arrangement of FIG. 1A is used for the trench 32 and the pattern. The side wall 33 on the side of the trench 32 is curved in a V-shape. In this case, although the (110) plane is not exposed on the side wall 33, all hexagonal side walls have a uniform crystal plane. The other parts are the same as those in FIG.

In each of the above embodiments, the six corners of the pattern 30 may be slightly rounded. Furthermore,
In addition to the plane orientation of the surface of the wafer 41 (FIG. 5) being exactly perpendicular to the (111) plane, the crystal plane is inclined at several degrees, preferably within 5 degrees with respect to the <111> crystal axis. Is also good. The essence is to equalize the electrical characteristics of the side walls 33 on all six sides.

Further, without departing from the spirit of the present invention,
In addition, various modified semiconductor devices such as a semiconductor device that controls a channel current by a gate potential, such as an electrostatic induction thyristor (SIT), a gate turn-off thyristor (GTO), and a MOS control thyristor (MCT). It is needless to say that the embodiment can be considered. Also, the first
Needless to say, any of the third to third patterns may be combined with the first to fourth embodiments.

[0065]

As described above, the present invention reduces the number of unit cells that can be accommodated per unit area by forming a substantially hexagonal pattern 30 by the side walls 33 of the semiconductor layer defined by the trenches 32. Can be significantly increased. This makes it possible to increase the current capacity and reduce the on-resistance of the trench-type insulated gate semiconductor device.

In addition, by increasing the number of unit cells, the contact area between the metal electrode 59 and the source region 56 can be increased at the same time, so that the contact resistance between them can be reduced and the on-resistance can be reduced.

Further, by using the (111) plane orientation substrate, the electric crystallographic characteristics of each side wall 33 of the trench 32 can be made uniform. The most typical example is a form in which the (110) plane is exposed on each side wall 33. As a result, the current flowing through each side wall 33 can be made uniform, so that the withstand voltage deterioration due to local current concentration can be prevented.

Further, depending on the selection of the plane orientation and the heat treatment,
Since the gate oxide film thickness t2 on the bottom surface of the trench 32 can be formed to be large, the gate oxide film thickness t1 can be reduced and the MOS
The driving capability of the FET element can be further increased.

[Brief description of the drawings]

FIG. 1A is a plan view and FIG. 1B is a cross-sectional view for explaining a first pattern.

FIGS. 2A and 2B are a plan view and a cross-sectional view illustrating a second pattern.

FIG. 3 is a plan view for explaining the present invention.

FIG. 4 is a perspective view for explaining the present invention.

FIG. 5 is a plan view for explaining the present invention.

FIG. 6 is a plan view for explaining a third pattern.

FIG. 7A is a plan view and FIG. 7B is a cross-sectional view for explaining the first embodiment of the present invention.

FIG. 8 is a cross-sectional view for explaining the manufacturing method.

FIG. 9 is a characteristic diagram for explaining the present invention.

FIG. 10A is a plan view and FIG. 10B is a cross-sectional view for explaining a second embodiment of the present invention.

FIG. 11 is a cross-sectional view for explaining a third embodiment of the present invention.

FIG. 12 is a cross-sectional view for explaining a fourth embodiment of the present invention.

FIG. 13 is a sectional view showing a trench type MOSFET device.

FIG. 14 is a plan view showing a conventional (100) wafer.

FIG. 15 is a perspective view for explaining a conventional example.

FIG. 16 is a diagram showing a pattern of a unit cell.

[Explanation of symbols]

 Reference Signs List 30 pattern 32 trench 33 side wall 54 gate oxide film 55 gate electrode 56 source region

 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Eiichiro Kuwako 2-5-5 Keihanhondori, Moriguchi-shi, Osaka F-term (reference) 5F102 FA02 FB01 GB04 GC08 GD10 GJ03 GL03 GR01

Claims (25)

[Claims] 1. A semiconductor device, comprising: a semiconductor layer having a hexagonal pattern, wherein crystal planes of sidewalls of the semiconductor layer are equivalent to each other. 2. A semiconductor device according to claim 1, wherein said semiconductor layer is partitioned into a hexagonal pattern by a trench formed on one main surface of the semiconductor layer, and crystal faces of side walls of said partitioned semiconductor layer are equivalent to each other. Characteristic semiconductor device. 3. The semiconductor layer partitioned into a hexagonal pattern by a trench formed on one main surface of the semiconductor layer, and the crystal planes of sidewalls of the partitioned semiconductor layer are made equivalent to each other, and A semiconductor device comprising an insulating film provided on a side wall of a layer. 4. The semiconductor layer partitioned by a trench formed on one main surface of the semiconductor layer into a hexagonal pattern, and crystal faces of side walls of the partitioned semiconductor layer are made equivalent to each other. An insulating film is provided on a side wall of the layer, a control electrode made of a conductive material is provided in the trench, and an insulated gate semiconductor device is configured by the control electrode, the insulating film, and a side wall of the partitioned semiconductor layer. Characteristic semiconductor device. 5. A semiconductor layer partitioned into a hexagonal pattern by a trench formed on one main surface of a semiconductor layer, wherein crystal faces of side walls of the partitioned semiconductor layer are made equivalent to each other, An insulating film formed on a side wall of the layer, a gate electrode made of a conductive material buried in the trench, a source region formed on one main surface of the semiconductor layer, and opposite to one main surface of the semiconductor layer A drain region provided on a side surface, a gate region provided on the gate electrode, the insulating film, and a side wall of the semiconductor layer to form an insulated gate semiconductor element. 6. A semiconductor layer of one conductivity type serving as a drain,
A channel region of the opposite conductivity type formed on the surface of the semiconductor layer, a source region of the opposite conductivity type formed on the surface of the channel region, and the semiconductor layer penetrating the channel region and partitioned into a hexagonal pattern Forming a trench on the side wall of the divided semiconductor layer as an equivalent plane, forming an insulating film on the side wall of the semiconductor layer, and forming a gate electrode made of a conductive material in the trench. A semiconductor device, comprising: an insulated gate semiconductor element including the gate electrode, the insulating film, and the channel region. 7. A first semiconductor layer of one conductivity type;
A second semiconductor layer of opposite conductivity type formed on the second semiconductor layer, and a third semiconductor layer of opposite conductivity type formed on the second semiconductor layer.
A semiconductor layer, a channel region of one conductivity type formed on the surface of the third semiconductor layer, a source region of the opposite conductivity type formed on the surface of the channel region, and a hexagonal shape penetrating the channel region. A trench for forming the semiconductor layer partitioned into patterns; providing crystal planes of sidewalls of the partitioned semiconductor layer as equivalent planes; forming an insulating film on sidewalls of the semiconductor layer; A semiconductor device, comprising: forming a gate electrode made of a material; and forming an insulated gate semiconductor element with the gate electrode, the insulating film, and the channel region. 8. The semiconductor device according to claim 1, wherein the main surface has a crystal plane of (11).
1) a surface or a surface in the vicinity thereof,
8. The semiconductor device according to claim 1, 2, 3, 4, 5, 6, or 7. 9. The method according to claim 1, wherein the crystal plane of the side wall is a (110) plane or a plane in the vicinity thereof.
The semiconductor device according to any one of 3, 4, 5, 6, 7, and 8. 10. The semiconductor device according to claim 1, wherein a plurality of the hexagonal patterns or the divided semiconductor layers are arranged at a predetermined interval. 9
The semiconductor device according to any one of the above. 11. The semiconductor device according to claim 3, wherein the insulating film is a film including at least a silicon oxide film.
The semiconductor device according to any one of 5, 6, and 7. 12. The semiconductor device according to claim 3, wherein the thickness of the insulating film formed on the six sidewalls of the semiconductor layer is substantially uniform. 3. The semiconductor device according to claim 1. 13. The insulated gate semiconductor device formed on six side walls of the semiconductor layer, wherein each threshold value on each side wall is substantially equal.
The semiconductor device according to any one of 5, 6, and 7. 14. A semiconductor device comprising a semiconductor layer having a honeycomb pattern, wherein crystal planes of sidewalls of the semiconductor layer are equivalent to each other. 15. A semiconductor device according to claim 1, wherein the semiconductor layer is formed in a honeycomb shape and formed in one main surface of the semiconductor layer, the semiconductor layer being continuous in a honeycomb shape, and the crystal planes of the side walls of the semiconductor layer are made to be equivalent to each other. Semiconductor device. 16. A hexagonal trench formed on one main surface of a semiconductor layer, the semiconductor layer being continuous in a honeycomb shape is provided, and crystal faces of side walls of the semiconductor layer are made equivalent to each other;
A semiconductor device, wherein an insulating film is provided on a side wall of the semiconductor layer. 17. A hexagonal trench formed on one main surface of a semiconductor layer, the semiconductor layer being continuous in a honeycomb shape is provided, and crystal faces of side walls of the semiconductor layer are made equivalent to each other;
An insulating film is provided on a sidewall of the semiconductor layer, a control electrode made of a conductive material is provided in the trench, and an insulated gate semiconductor device is configured by the control electrode, the insulating film, and a sidewall of the semiconductor layer. Semiconductor device. 18. A semiconductor device having a hexagonal trench formed on one main surface of a semiconductor layer, the semiconductor layer being continuous in a honeycomb shape, wherein crystal faces of side walls of the semiconductor layer are equivalent to each other, and a side wall of the semiconductor layer is provided. A gate electrode made of a conductive material buried in the trench; a source region formed on one main surface of the semiconductor layer; and a surface opposite to the one main surface of the semiconductor layer. And a channel region provided on a side wall of the semiconductor layer, comprising a drain region provided in the semiconductor device, and a gate region provided on a side wall of the semiconductor layer. 19. A semiconductor device, comprising: a semiconductor layer of one conductivity type serving as a drain; a channel region of a reverse conductivity type formed on a surface of the semiconductor layer; and a source region of a reverse conductivity type formed on a surface of the channel region. With a hexagonal trench penetrating the channel region,
Providing the semiconductor layer continuous in a honeycomb shape, making crystal planes of sidewalls of the semiconductor layer equivalent planes, forming an insulating film on sidewalls of the semiconductor layer, and forming a gate electrode made of a conductive material in the trench. A semiconductor device comprising an insulated gate semiconductor element including the gate electrode, the insulating film, and a channel region provided on a sidewall of the semiconductor layer. 20. A first semiconductor layer of one conductivity type, a second semiconductor layer of a reverse conductivity type formed on the first semiconductor layer, and a reverse semiconductor layer formed on the second semiconductor layer. Third of conductivity type
A semiconductor layer, a channel region of one conductivity type formed on the third semiconductor layer, and a source region of the opposite conductivity type formed on the surface of the channel region. Providing the semiconductor layer continuous in a honeycomb shape by the trench, making the crystal planes of sidewalls of the semiconductor layer equivalent planes, forming an insulating film on the sidewall of the semiconductor layer, and forming a gate made of a conductive material in the trench. A semiconductor device comprising: an electrode; and an insulated gate semiconductor element including the gate electrode, the insulating film, and a channel region provided on a sidewall of the semiconductor layer. 21. A crystal plane of one principal surface of the semiconductor layer is (1)
The semiconductor device according to any one of claims 14, 15, 16, 17, 18, 19, and 20, wherein the semiconductor device is a surface or a surface in the vicinity thereof. 22. The crystal according to claim 14, wherein the crystal plane of the side wall is a (110) plane or a plane in the vicinity thereof.
The semiconductor device according to any one of 15, 16, 17, 18, 19, 20, and 21. 23. The semiconductor device according to claim 16, wherein the insulating film is a film including at least a silicon oxide film.
The semiconductor device according to any one of 7, 18, 19, and 20. 24. The semiconductor device according to claim 16, wherein the thickness of the insulating film formed on the six side walls of the semiconductor layer is substantially uniform. 13. A semiconductor device according to claim 1. 25. The insulated gate semiconductor device formed on six side walls of the semiconductor layer, wherein each threshold value on each side wall is substantially equal.
The semiconductor device according to any one of 6, 17, 18, 19, and 20.