JP2001101899A - Semiconductor memory and its control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory in which the stress level applied to each memory cell is not affected by a defective cell. SOLUTION: This device is provided with an address baffer 1, a first pre- decoder 2, a register circuit 3, a fuse data storing section 4, a first multiplexer 5, a second pre-decoder 6, an inverter 7, a second multiplexer 8, and a memory cell array 9. In order to store a result to which an address of a defective part is pre-decoded as fuse data corresponding to a result to which an address signal externally inputted is pre-decoded, the fuse data storing section 4 can not only replace a defective part by a spare cell, but can set a state in which a defect does not exist in fuse data. Therefore, desired stress applied to all memory cells excluding a defective part at the time of a burn-in test by utilizing fuse data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device capable of selecting all memory cells in a memory cell array.
In particular, the present invention is directed to a semiconductor memory device capable of performing a burn-in test for applying a desired stress to all the memory cells in a state where all the memory cells are selected.

[0002]

2. Description of the Related Art One of the techniques for schooling (inspection) a semiconductor memory is a so-called burn-in test. In the burn-in test, the operating condition of the memory cell is measured under the condition that the conditions are severely accelerated by raising the temperature and the power supply voltage.
For example, the state of destruction of a memory cell is inspected by applying stress in a write state.

In the burn-in test, it is necessary to apply a stress for a much longer time than a normal memory access. Therefore, if the test is performed for each address while incrementing the address, it takes an enormous test time. It is impossible. For this reason, it is common to apply stress to each memory cell simultaneously with all memory cells selected simultaneously.

FIG. 6 is a schematic circuit diagram of a conventional selection control circuit for selecting all memory cells in a semiconductor memory. The address buffer 31 buffers the address signal input from the outside in the input first-stage circuit 32, and then generates two types of positive and negative signals Ai and / Ai in the NAND gates G1 and G2. These two types of signals are input to the decoding circuit 33 and decoded.

The NAND gates G1 and G2 are supplied with an all-cell test signal which goes low during a burn-in test. When this signal goes low, the outputs of the NAND gates G1 and G2 both go high, and all memory cells are selected.

FIG. 7 is a diagram showing a schematic configuration of a memory cell array in an SRAM. Each memory cell is connected between a word line and a bit line pair.
The transfer gate 34 is connected. The column transfer gate 34 is on / off controlled by a column decoder 35.

At the time of normal writing of the SRAM, only one of the word lines and one set of the column transfer gates 34 are selected, and the data of the data line pair Din, / Din is written only to a specific memory cell. On the other hand, during the burn-in test, all word lines and all column transfer gates 34
Is selected, and the data of the data line pair Din, / Din is written to all the memory cells.

Meanwhile, in recent years, many semiconductor memories have a spare cell which can be replaced with a defective cell in advance in order to improve the yield. In this type of memory, a defective cell in which a defect such as a short circuit has occurred is replaced with a spare cell in units of rows or columns.

An address indicating a defective portion is stored in the chip by cutting the fuse element. During normal operation of the memory, when an address is input from the outside, this address is compared with the address of a defective portion stored in the chip, and if they match, replacement with a spare cell is performed.

[0010]

However, when a burn-in test is performed on a memory having a defective cell,
Since all the memory cells are forcibly selected by the above-described circuit of FIG. 6, a defective cell is also selected. For this reason,
For example, when a short-circuit (short) failure of a bit line occurs, a leak current flows from the data line Din to the ground terminal via the bit line as shown by a thick line path in FIG. The voltage will drop. When the high-level voltage of the data line Din decreases, the stress level supplied to other normal cells also decreases, so that normal screening cannot be performed.

Such a problem can occur not only when a short-circuit failure to the ground level occurs but also when a short-circuit failure to the power supply voltage level occurs. In this case, the low level voltage rises, and the low level stress level becomes insufficient.

[0012] These problems can occur not only when the memory cell itself is defective but also when a column-related defect or a row-related defect occurs.

The present invention has been made in view of such a point, and an object of the present invention is to provide a semiconductor memory in which a stress level applied to each memory cell when all cells are selected is not affected by a defective cell. It is to provide a device.

[0014]

According to a first aspect of the present invention, there is provided a defect information storage unit for storing an address corresponding to a defective cell, and the defect information storage unit stores the address. A spare cell replacing means for replacing a memory cell within a predetermined range including a defective cell with a spare cell based on an address, in a semiconductor memory device, when an all memory cell selection signal instructing selection of all memory cells is input, A selection unit for selecting all of the memory cells other than the memory cells within the predetermined range;

According to the first aspect of the present invention, when all the memory cell selection signals are inputted, a defective cell is not selected, so that a desired stress is not applied to other normal memory cells due to the influence of the defective cell. Will not happen.

According to the second aspect of the present invention, the result of pre-decoding an address corresponding to a defective cell in units of a plurality of address bits is stored as defect information. Information that there is no information can also be stored. Therefore, if this defect information is used, it becomes easy to select all the other memory cells except for the defective cell.

According to the third and fourth aspects of the present invention, defective cells can be replaced in units of columns or rows, and columns or rows containing defective cells can be excluded from the burn-in test.

Further, even when a memory cell is configured in units of blocks and a defective cell is replaced in units of blocks, the problem that a desired stress is not applied to other normal memory cells due to the influence of the defective cell can be solved.

According to a sixth aspect of the present invention, in the method of controlling a semiconductor memory device capable of selecting all memory cells in a memory cell array, an externally input address signal is pre-decoded in units of a plurality of address bits. A second step of pre-decoding and storing an address for replacing a defective cell in units of the plurality of address bits; and a first step of storing the first and second addresses.
A third step of selecting and outputting any of the pre-decoding results of the step, a fourth step of performing final address decoding based on the output of the third step,
A fifth step of selecting and outputting one of the decoding result of the fourth step and an inverted signal of the decoding result, wherein an all memory cell selection signal instructing selection of all memory cells is input; And the third step selects the pre-decoding result of the second step,
The fifth step selects an inverted signal of the decoding result of the fourth step, and in a normal cell access, the third step selects the pre-decoding result of the first step, and the fifth step selects the inversion signal of the first step. Select the decoding result of 4 steps.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor memory device according to the present invention will be specifically described with reference to the drawings. Hereinafter, a semiconductor memory device capable of performing a burn-in test by simultaneously applying stress to all the memory cells in a state where all the memory cells are in a selected state will be described.

FIG. 1 is a block diagram of one embodiment of a semiconductor memory device according to the present invention. FIG. 1 mainly shows a portion for performing address decoding, and omits other portions.

The semiconductor memory device shown in FIG. 1 includes an address buffer 1, a first predecoder (first predecoding means) 2, a register circuit 3, a fuse data storage section (defective information storage means) 4, A first multiplexer (first selection means) 5, a second predecoder (second predecoding means) 6, an inverter (inversion means) 7, and a second multiplexer (selection means, second selection means) Means) 8
And a memory cell array 9.

The address buffer 1 is constructed in the same manner as in FIG. 6, and buffers two types of address signals after buffering an externally input address signal. The first predecoder 2 includes address signals A0 to An
Is pre-decoded in m (m <n) bit units. FIG. 2 shows an example in which an address signal is pre-decoded in units of 3 bits. Decoding in 3-bit units yields 8
Bit outputs B0 to B7 are obtained. Of these 8 bits, only one bit becomes “1”.

The decoding result of the first predecoder 2 is as follows.
The data is latched by the register circuit 3 at a common timing. Thereby, the predecode result of the first predecoder 2 can be synchronized with the clock.

On the other hand, the fuse data storage section 4 stores an address corresponding to a defective portion using a fuse element. Specifically, similarly to the first predecoder 2, a result obtained by predecoding an address corresponding to a defective portion in units of m bits is stored. The fuse data storage unit 4 stores data of 2 ^m bits in total.

If a defective portion exists, the bit corresponding to the defective portion is set to "1". Therefore, if there is no defective portion, the fuse data storage unit 4 stores all “0” data.

Conventionally, since a fuse element is provided for each bit of the address of a defective portion, a state where no defective portion exists cannot be expressed by the fuse element. For example, when none of the fuse elements is blown, the address is all “0” or all “1”.
Was considered to match.

On the other hand, in the present embodiment, since a fuse element is assigned to the result of pre-decoding the address signal, a state where no defective portion exists can be expressed as all "0".

According to the present embodiment, the number of fuse elements is increased as compared with the prior art.
Since decoding is performed in a plurality of stages, if a fuse element is provided corresponding to the predecode result of the first stage, the number of fuse elements can be suppressed to about two to three times the conventional number,
There is no fear that the circuit configuration becomes complicated.

In recent high-speed synchronous memories, the result of pre-decoding an address is generally stored in a register in advance to shorten the time required for memory access. It is more natural to store the result of pre-decoding of the fuse data, so that the system can be unified.

The first multiplexer 5 of FIG. 1 selects one of the output of the fuse data storage unit 4 and the output of the first predecoder 2 according to the logic of the all memory cell selection signal test. Specifically, during normal operation of the memory (when test is at a low level), the output of the first predecoder 2 is selected. At the time of a burn-in test (when test is at a high level), fuse data is stored. The output of the unit 4 is selected.

The second predecoder 6 performs decoding based on the output of the first predecoder 2 or the output of the fuse data storage unit 4, and outputs a final decoded signal.

The second multiplexer 8 selects one of the output of the second predecoder 6 and its inverted output according to the logic of the all memory cell selection signal test. Specifically, during normal operation of the memory (when test is at low level)
, The output of the second predecoder 6 is selected, and at the time of a burn-in test (when test is at a high level), the inverted output of the second predecoder 6 is selected.

The output of the second multiplexer 8 is supplied to a column transfer gate in the memory cell array 9. As a result, one of the column transfer gates is turned on, and the data of the data line pair Din, / Din is supplied to the bit line pair connected to the gate.

Although omitted in FIG. 1, a circuit similar to that of FIG. 1 is provided on the row side. On the row side, one of the word lines is driven by the output of the second multiplexer 8.

FIG. 3 is a circuit diagram showing the internal configuration of the second multiplexer 8. The second multiplexer 8 includes transfer gates 11 and 12 and inverters 13 to 15. The output of the second predecoder 6 is input to the transfer gate 12, and a signal obtained by inverting the output of the second predecoder 6 by the inverter 7 in FIG. 1 is input to the transfer gate 11.

When the all memory cell selection signal test is at a high level, the transfer gate 11 is turned on and the output of the inverter 7 is selected. When the all memory cell selection signal test is at a low level, the transfer gate 12 is turned on. Thus, the output of the second predecoder 6 is selected.

Next, FIG. 1 shows a case where a burn-in test is performed.
The operation of the semiconductor memory device will be described. When performing the burn-in test, all the memory cells in the memory cell array 9 are selected, and the all-memory-cell selection signal test goes high. Therefore, the first multiplexer 5 of FIG.
Selects the output signal of the fuse data storage unit 4. As described above, the address of the defective portion is predecoded and stored in the fuse data storage unit 4.

More specifically, the fuse data storage unit 4
Stores "1" only in the bit corresponding to the address of the defective part. If no defective part exists, the fuse data storage unit 4 stores all “0”.

The output of the fuse data storage unit 4 is input to the second predecoder 6 via the first multiplexer 5, and the final address decoding is performed. As a result, only the address corresponding to the defective part is selected. If no defective part exists anywhere, the output of the second predecoder 6 deselects all addresses.

Further, the second multiplexer 8 selects the output of the inverter 7 because the all memory cell selection signal test is at the high level. That is, the second multiplexer 8 deselects the address selected by the second predecoder 6 and selects an address not selected.

As a result, only the address corresponding to the defective portion is deselected, and all other addresses are selected. Therefore, except for the column where the failure occurred,
The desired stress can be applied to all other columns.

If a burn-in test is performed in this state, the problem that a desired stress cannot be applied to a normal memory cell due to the influence of a column or a word line in which a short-circuit failure or the like has occurred does not occur.

FIG. 4 is a diagram showing memory access during normal operation of the memory. FIG. 4A shows an example in which a defective cell is replaced with a spare cell due to an attempt to access the defective cell. (B) shows an example in which the memory cell of the access destination is a non-defective product. FIG. 5 is a diagram showing a memory access at the time of a burn-in test. FIG. 5A shows an example in which all cells except for a defective cell are selected.
(B) shows an example in which there is no defective cell.

As described above, according to the present embodiment, the result of pre-decoding the address of the defective part is stored as fuse data in correspondence with the result of pre-decoding the address signal input from the outside. Can be replaced with a spare cell, and a state in which no defect exists can be set by the fuse data. Therefore, by using the fuse data, a desired stress can be applied to all the memory cells except for the defective part at the time of the burn-in test.

In this embodiment, the all-cell selection signal te
Since the selection of the first and second multiplexers 8 is controlled by st, there is no need to separately provide a signal for selecting these multiplexers.

Further, in FIG. 1, the second predecoder 6
Has been shown as an example in which the output of
The address may be decoded by using a pre-decoder of more than one stage. In this case, among the three or more stages of predecoders, the fuse data storage unit 4 of FIG. 1 is provided corresponding to any one of the predecoders other than the last stage, and the inverter 7 of FIG. Just connect.

Incidentally, in recent large-capacity memories, the memory cell array 9 is often divided into a plurality of array blocks. In this case, since a spare cell (spare column or spare row) and a fuse element are provided for each array block, the fuse data storage unit 4 of FIG. 1 may be provided for each block.

[0049]

As described above in detail, according to the present invention, when the all memory cell select signal is input, all the memory cells except for the memory cells in a predetermined range including a defective cell are selected. Therefore, screening such as a burn-in test can be performed except for defective cells. As a result, a problem that a desired stress is not applied to other normal memory cells due to the influence of the defective cell does not occur, and the reliability of the screening is improved.

Further, since the result of pre-decoding the address corresponding to the defective cell in units of a plurality of address bits is stored as defect information, not only the address of the defective cell but also information indicating that there is no defective portion is stored. It can be stored. Therefore, if this defect information is used, it becomes easy to select all the other memory cells except for the defective cell.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of a semiconductor memory device according to the present invention.

FIG. 2 is a diagram showing an example in which an address signal is pre-decoded in units of 3 bits.

FIG. 3 is a circuit diagram showing an internal configuration of a second multiplexer 8;

FIG. 4 is a diagram showing memory access during normal operation of the memory.

FIGS. 5A and 5B are diagrams showing memory access during a burn-in test.

FIG. 6 is a schematic circuit diagram of a conventional selection control circuit for selecting all memory cells in a semiconductor memory.

FIG. 7 is a diagram showing a schematic configuration of a memory cell array in an SRAM.

FIG. 8 is a diagram showing an example of a leak path.

[Description of Signs] 1 Address buffer 2 First predecoder 3 Register circuit 4 Fuse data storage unit 5 First multiplexer 6 Second predecoder 7 Inverter 8 Second multiplexer 9 Memory cell array

Claims (6)

[Claims] 1. A failure information storage means for storing an address corresponding to a defective cell, and a spare cell for replacing a memory cell within a predetermined range including the defective cell with a spare cell based on the address stored in the failure information storage means. And a replacement unit, wherein when the all memory cell selection signal instructing selection of all the memory cells is input, the selection unit that selects all the memory cells except for the memory cells within the predetermined range is provided. A semiconductor memory device comprising: 2. A semiconductor memory device capable of selecting all memory cells in a memory cell array, wherein: first predecoding means for predecoding an externally input address signal in units of a plurality of address bits; A failure information storage means for predecoding and storing an address corresponding to the plurality of address bits as a unit, a predecoding result of the first predecoding means, and a predecoding result of the failure information storage means. First selecting means for selecting and outputting any one of them; second predecoding means for performing address decoding based on the output of the first selecting means; and an output signal of the second predecoding means. Inverting means for inverting and outputting; selecting one of an output signal of the second predecoding means and an output signal of the inverting means; And a second selection means for inputting a signal. When an all memory cell selection signal instructing selection of all memory cells is input, the first selection means selects a predecode result of the failure information storage means. Together with the second
The selecting means selects the output signal of the inverting means, and at the time of normal cell access, the first selecting means selects the pre-decoding result of the first pre-decoding means, and the second selecting means A semiconductor memory device, wherein a decoding result of the second pre-decoding means is selected. 3. The semiconductor device according to claim 2, wherein said defect information storage means pre-decodes and stores an address for replacing a defective cell in a column unit in units of said plurality of address bits. Storage device. 4. The semiconductor device according to claim 2, wherein said defect information storage means pre-decodes and stores an address for replacing a defective cell in a row unit in units of said plurality of address bits. Storage device. 5. The memory device according to claim 2, further comprising a memory cell array divided into a plurality of blocks, wherein said defect information storage means stores an address for replacing a defective cell for each block. The semiconductor memory device according to any one of the above. 6. A method of controlling a semiconductor memory device capable of selecting all memory cells in a memory cell array, comprising: a first step of pre-decoding an externally input address signal in units of a plurality of address bits. A second step of pre-decoding and storing an address for replacing a defective cell in units of the plurality of address bits; and a step of selecting and outputting one of the pre-decoding results of the first and second steps. A third step of performing final address decoding based on the output of the third step; and selecting and outputting one of a decoding result of the fourth step and an inverted signal of the decoding result. And when the all memory cell selection signal instructing the selection of all the memory cells is inputted, The third step selects the pre-decoding result of the second step, the fifth step selects an inverted signal of the decoding result of the fourth step, and at the time of normal cell access, the third step performs the first step. Wherein the pre-decoding result is selected and the decoding result of the fourth step is selected in the fifth step.