JP2001197378A - Solid-state image pickup element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid-state image pickup element provided with a current source array for suppressing the influence of the wiring resistance of a power bus line and realizing the stable operation of a line amplification series. SOLUTION: The solid-state image pickup element has a pixel array where pixels which can realize photoelectric conversion are two-dimensionally arranged, a vertical scanning circuit for selecting the reading row of the pixel array, a plurality of amplification circuits for amplifying the signals of the pixels for one selected row in parallel and comprising analog amplifiers, a plurality of bias current supply circuits which are provided to the respective analog amplifiers and comprise MOS transistors for supplying bias currents to the respective analog amplifiers, and a scanning circuit which sequentially selects and scans the output of the amplification circuit. The source terminal of the MOS transistor is connected to a power voltage supply line. The substrate terminal of the MOS transistor is connected to the source terminal of the MOS transistor. The gate terminal of the MOS transistor is connected to the power voltage supply line through a capacity element and is connected to the bias voltage supply line through a switch element.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device, and more particularly to an improvement in a current source array of a solid-state imaging device formed by integrating MOS (including CMOS) circuits.

[0002]

2. Description of the Related Art Conventionally, an image sensor (solid-state image sensor)
In order to improve the S / N ratio, a technique of amplifying and outputting a signal inside an image sensor is known.

[0003] For example, as disclosed in Japanese Patent Publication No. H8-24352, an electric charge output from a pixel is converted into an amplifier provided for each vertical signal line (hereinafter referred to as a line amplifier).
Output as a signal amplified by S / N
There is a method for improving fixed pattern noise (FPN).

[0004] The prior art will be described below by taking the image sensor disclosed in Japanese Patent Publication No. H8-24352 as an example.

FIG. 2 is a simplified illustration of a conventional image sensor having a line amplifier.

In FIG. 2, reference numeral 2-1 denotes photodiodes D1, D2,..., Dj and switches S1, S2.
2,..., Sj in a two-dimensional array.

Reference numeral 2-2 denotes a pixel array 2-.
This is a vertical scanning circuit that selects one readout row.

Reference numeral 2-3 denotes a line amplifier array for amplifying signal charges output from the pixels in a column-parallel manner, and a plurality of amplifier circuits 2-3 by analog amplifiers.
.., 2-3-3-j are provided in parallel.

Reference numeral 2-4 denotes a horizontal selection switch array for outputting each output of the line amplifier array 2-3 to the output signal line 2-5.

Reference numeral 2-6 denotes a horizontal scanning circuit for sequentially selecting and scanning the horizontal selection switch array 2-4.

Next, the operation of the image sensor thus configured will be described.

The photodiode D of the pixel array 2-1
1, D2,..., Dj are switched by the row selection pulse φ _ROW i output from the scanning circuit 2-2 to the switches S1, S2, S2 of the pixels in the i-th row of the pixel array 2-1.
, Sj are turned on, so that the line amplifier row 2-
3 and amplified in column parallel.

Thereafter, the horizontal scanning circuit 2-6 generates scanning pulses φ _COL1 , _φCOL2 ,..., _ΦCOLj , and sequentially turns on and off the horizontal selection switch array 2-4.
The output of the selected line amplifier array 2-3 is connected to the output signal line 2-
5 is output.

As described above, a two-dimensional image can be output by sequentially reading out the signals of the respective pixels of the pixel array 2-1 while selecting the addresses in the vertical and horizontal (XY) directions of the pixels.

Incidentally, in order to operate the line amplifier array 2-3, it is necessary to supply a bias current.

Generally, in such a MOS analog circuit, a bias current is generated by utilizing the saturation characteristics of a P-type MOS transistor.

As described in the configuration of the image sensor shown in FIG. 2, the line amplifier array 2-3 used in the image sensor includes a plurality of amplifier circuits 2-3-1, 2-3-2, and .., 2-3-j are provided in parallel.

Accordingly, each of the amplifier circuits 2-3-1, 2-3-2,..., 2-3 constituting the line amplifier array 2-3 is provided.
A bias current generating circuit for independently supplying a bias current to −j is required.

Hereinafter, each of the amplifier circuits 2-3-1, 2-3-2,..., 2-3-3 constituting the line amplifier array 2-3 will be described.
A bias transistor array arranged to supply a bias current to j is referred to as a current source array.

Hereinafter, a current source array used in a conventional solid-state imaging device will be described.

FIG. 3 shows the configuration of a commonly used bias current source array.

In FIG. 3, reference numerals 3-3 denote bias MOS transistors Q1 and Q corresponding to the number of horizontal pixels.
, Qn.

Reference numeral 3-1 denotes the current source array 3
-3 constituting bias MOS transistors Q1, Q
Power supply bus wiring for supplying a power supply voltage to each source of 2,.

Reference numeral 3-2 denotes a bias MO.
A bias voltage supply line for supplying a bias voltage to each gate of the S transistors Q1, Q2,..., Qn.

The bias MOS transistor Q
, Q2,..., Qn to line amplifier train 2
-3, each amplifier circuit 2-3-1, 2-3-3-
2,..., 2-3-3-j are connected so as to independently supply a bias current.

Approximately, the saturation characteristic of a MOS transistor is expressed by equation (1).

I_D= Α (V_GS-V_T)^Two ... (1) where I_DIs the bias current, α is the device size and
Coefficient of mobility, V _GSIs the gate-source voltage, V_T
This is the threshold voltage.

In the saturation characteristics of the MOS transistor,
Since the output current does not depend on the drain voltage approximately, the MO is obtained by supplying a constant voltage between the gate and the source.
By operating the S transistor in the saturation region, a constant bias current can be generated from the drain.

The bias MOS transistor Q
, Q2,..., Qn are respectively supplied to the amplifier circuits 2 constituting the line amplifier rows 2-3.
-3-1, 2-3-2, ..., 2-3-j.

Thus, each of the amplifier circuits 2-3-1, 2-3-2,..., 2-
3-j can be operated independently.

[0031]

However, in the conventional bias current source array shown in FIG. 3, it is actually difficult to ensure the uniformity of the bias current due to the following reasons.

That is, in the conventional bias current source array shown in FIG. 3, a plurality of bias MOS transistors Q1, Q2,...
In order to supply the current, a large amount of current flows through the power supply bus line 3-1.

Here, if there is a wiring resistance in the power supply bus line 3-1, a large amount of current flows to the power supply bus line 3-1.
-1, a potential gradient is generated, and non-uniformity occurs in the voltage of each source electrode of each bias MOS transistor Q1, Q2,..., Qn.

On the other hand, since no current flows through the bias voltage supply line 3-2, the bias MOS transistor Q
The potential of each gate electrode of Q1,..., Qn is kept constant.

As a result, the potential difference between the gate and source of each of the bias MOS transistors Q1, Q2,..., Qn changes, and the bias current _ID generated according to the equation (1) changes.

The non-uniformity of the bias current _ID due to this phenomenon also depends on the wiring layout. For example, the power supply bus wiring 3-1 and the power supply terminal for supplying the power supply voltage AVDD are connected at both ends of the bias current source array. In the case of connection, the current at the end of the bias current source array is large, and decreases at the center.

In order to suppress such non-uniformity,
There is a need to reduce the power supply wiring resistance sufficiently.

However, as a recent trend, particularly in digital still cameras and the like, there is an increasing demand for a solid-state image pickup device having a large number of pixels. The bus wiring length becomes longer, and the power supply voltage inside the power supply bus wiring is seriously reduced.

Therefore, the non-uniformity of the bias current input to the line amplifier array 2-3 becomes strong, and it becomes difficult to obtain the uniform operation of the amplifier.

Also, when the voltage of the substrate terminal is
Independently taken by S transistors Q1, Q2,..., Qn
The threshold voltage fluctuation represented by the following equation (2)
ΔV _TOccurs.

ΔV _T = β ｛(2φ _B + V _BS ) ^1/2 − (2φ _B ) ^1/ 2… (2) where β is a constant, φ _B is a Schottky barrier voltage, V _BS
Is a voltage between the substrate and the source terminal of the bias MOS transistor.

[0042] Then, the threshold voltage V _T, the variation depending on the substrate and source terminal voltage VBS as shown in equation (2) occurs, resulting in the bias current I _D as can be seen from equation (1) This causes non-uniformity.

In view of this point, the present invention provides a solid-state imaging device having a current source array which suppresses the influence of wiring resistance of a power supply bus line and enables a stable line amplifier operation. As an issue.

[0044]

According to the present invention, in order to solve the above-mentioned problems, (1) a pixel array in which photoelectrically convertible pixels are two-dimensionally arranged, and a readout row of the pixel array And a vertical scanning circuit for selecting
A plurality of amplifying circuits including an analog amplifier for amplifying signals of pixels in a row in parallel, and a MOS transistor for bias current supply which is provided corresponding to each of the analog amplifiers and supplies a bias current to each analog amplifier including,
In a solid-state imaging device having a plurality of bias current supply circuits and a scanning circuit for sequentially selecting and scanning the output of the amplification circuit, a source terminal of the MOS transistor is connected to a power supply voltage line, and a substrate terminal of the MOS transistor Is connected to the source terminal of the MOS transistor,
A solid-state imaging device is provided, wherein a gate terminal of the transistor is connected to the power supply voltage supply line via a capacitor, and connected to a bias voltage supply line via a switch element.

According to the present invention, in order to solve the above-mentioned problems, (2) means for cutting off the output current of the bias current generating circuit, and Means for turning on a switch element to store the voltage of the bias voltage supply line in the gate terminal of the MOS transistor, the solid-state imaging device according to (1), being provided.

According to the present invention, in order to solve the above problems, (3) a pixel array in which pixels capable of photoelectric conversion are two-dimensionally arranged, and a vertical array for selecting a readout row of the pixel array. A scanning circuit, a plurality of amplifier circuits including an analog amplifier for amplifying signals of the selected one row of pixels in parallel, including an analog amplifier, and a bias current provided to each of the analog amplifiers. In a solid-state image pickup device having a plurality of bias current supply circuits including MOS transistors for supplying a bias current to be supplied and a scanning circuit for sequentially selecting and scanning the output of the amplifier circuit,
A power supply voltage supply line for supplying a power supply voltage to the source terminal of the S transistor, a bias voltage supply line for supplying a bias voltage to the gate terminal of the MOS transistor via a first switch, and a gate terminal of the MOS transistor. A capacitance element connecting between the source terminals, an output line for supplying a bias current from the drain of the MOS transistor to the analog amplifier via the second switch means, the first switch means and the second switch means Means for exclusively turning on the MOS transistor, wherein the substrate terminal of the MOS transistor is connected to the source terminal of the MOS transistor.

Here, to be exclusively turned on means that the first switch means and the second switch means are not simultaneously turned on, and the first switch means and the second switch means are not simultaneously turned on. There may be a case where only one of the two switch means is turned on and a case where both are turned off.

[0048]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a configuration of a current source array of a solid-state imaging device according to an embodiment of the present invention.

The configuration of the solid-state imaging device according to one embodiment of the present invention is the same as that of the conventional solid-state imaging device shown in FIG.

The current source array of the solid-state imaging device according to one embodiment of the present invention is configured as follows.

In FIG. 1, reference numeral 1-0 denotes a unit circuit for generating a bias current.
By providing 0 in parallel by the number of amplifiers in the line amplifier array 2-3, a bias current source array is formed.

The unit circuit 1-0 is a P-type MO
.., 1-1-j formed by bias current generating transistors 1-1-1, 1-1-2,...
The bias current generating transistors 1-1-1 and 1-1
−2,..., 1-1-j and power supply bus wiring 1
-6, and capacitive elements 1-2-1 and 1-2 provided between
, 1-2-j, between each gate electrode of the bias current generating transistors 1-1-1, 1-1-2, ..., 1-1-j and the bias voltage supply wiring 1-8. , 1-3-1,..., 1-3-3-
j and an inverter 1 provided for inverting a pulse input to the first switch control pulse supply line 1-7.
-4, and the bias current generating transistor 1-1-
, 1-1-j, and the respective amplifier circuits 2-3-1, 2-3 in the line amplifier array 2-3.
,..., 2-3-j, and switch elements 1-5-1, 1-5-2,..., 1-5-j.

Here, the bias current generating transistor 1
.., 1-1-j are connected to their respective source terminals.

Further, the switching elements 1-3-1 and 1-3-3-
,..., 1-3-j are commonly connected by a switch control pulse supply line 1-7, and control pulses φ
_MEM is input respectively.

The switch elements 1-5-1 and 1-5-
Each of the control electrodes 2,..., 1-5-j is commonly connected by a second switch control pulse supply line 1-9, and an inverted pulse of _φMEM is input.

That is, each switching element 1-3
-1, 1-3-2, ..., 1-3-j and 1-5-1, 1-
The operations of 5-2,..., 1-5-j are configured such that the on / off operations are performed in opposite directions.

Next, the operation of the thus configured current source array will be described.

First, the pulse voltage from φ _{MEM is set} to the high level, and the switching elements 1-3-1, 1-3-2,.
-3-j is turned on, and the potential V _REF applied to the bias voltage supply wiring 1-8 is applied to the bias current generating transistor 1
.., 1-1-j are held by the respective gate electrodes.

At this time, the switching elements 1-5-1, 1-
5-2,..., 1-5-j are applied with the pulse whose [phi] _MEM is inverted by the inverter 1-4, so that the switch elements 1-5-1, 1-5-2,. -5-j is off.

Thereafter, the pulse voltage from φ _{MEM is changed} to a low level, and the switch elements 1-5-1, 1-5-2,.
1-5-j is turned on, and the bias generating transistor 1-
.., 1-1-j, each amplifier circuit 2-3-1, 2-3-2,.
..., 2-3-3-j is supplied with a bias current.

Thus, even if the power supply voltage AVDD drops due to the wiring resistance of the power supply bus wiring 1-6, the switches 1-3-1, 1-3-2,..., 1-3-j are turned off in this state. , The voltage drop of the power supply bus line 1-6 is caused by the power supply bus line 1-6 and the bias current generating transistor 1
, 1-1-1, 1-2-2,..., 1-1-j provided between the respective gate electrodes.
.., 1-1-j is transmitted to each gate electrode of the bias current generating transistors 1-1-1, 1-1-2,..., 1-1-j.

In this state, the substrate potential and the substrate terminal are also the bias current generating transistors 1-1-1 and 1-1-1.
2,..., 1-1-j are connected to the respective source terminals, so that they are kept equal to the source potential, so that the bias current generating transistors 1-1-1, 1-1-2,
, 1-1-j are kept constant.

Thus, it is possible to suppress a change in the bias current supplied to each of the amplifier circuits 2-3-1, 2-3-2,..., 2-3-j of the line amplifier array 2-3. Thus, a stable bias current is supplied to the line amplifier array 2-3, and the operation uniformity of the line amplifier array 2-3 can be ensured.

[0065] Incidentally, in this embodiment, for simplicity of explanation, the inversion pulse phi _MEM generated by the inverter 1-4 switching element 1-5-1,1-5-2, ...,
1-5-j, the bias current is not supplied when the bias voltage is stored. However, as long as the bias voltage storage timing and the bias current supply timing do not overlap, the bias voltage is not supplied. The storage timing and the timing for supplying the bias current may be set independently.

That is, the switching elements 1-3-n and 1-5-n are exclusively turned on.

Here, being exclusively turned on means that both the switch element 1-3-n and the switch element 1-5-n are not simultaneously turned on.

That is, there is a case where only one of the switch elements 1-3-n and the switch elements 1-5-n is turned on, and a case where both are turned off.

As the timing for storing the bias voltage, for example, by utilizing a blanking period in the video signal output sequence, the bias voltage can be set without affecting the video signal output.

Further, it is obvious that the MOS transistor includes a CMOS transistor, and furthermore,
The P-type MOS transistor used for the bias current generating transistor of the current source array according to the present embodiment is an N-type MOS transistor.
The same effect can be obtained by simply changing the polarity of the S transistor.

Further, in the present specification described in the above embodiments, in addition to claims 1 to 3 described in the claims, the inventions described as additional notes 1 and 2 below are described. include.

(Supplementary Note 1) A pixel array formed by two-dimensionally arranging pixels capable of photoelectric conversion, a vertical scanning circuit for selecting a row to be read out from the pixel array, and A plurality of amplifying circuits for amplifying signals in parallel, a scanning circuit for sequentially selecting and scanning the output of the amplifying circuit, and an amplifying circuit for amplifying the signal of the pixel in parallel are constituted by a plurality of analog amplifiers. A plurality of bias current generating circuits for supplying a bias current to the plurality of analog amplifiers, wherein the bias current generating circuit is constituted by a bias current generating MOS transistor, and a source terminal of the bias current generating MOS transistor is provided. Is connected to a power supply voltage supply line, and the substrate terminal of the bias current generating MOS transistor is connected to the bias current generating MOS transistor. Is connected to the source terminal of Njisuta,
A solid-state device characterized in that a gate terminal of the bias current generating MOS transistor is connected to the power supply voltage supply line via a capacitor, and is connected to the bias voltage supply line via a switch. Imaging device.

(Supplementary Note 2) A pixel array in which photoelectrically convertible pixels are two-dimensionally arranged, a vertical scanning circuit for selecting a row to be read out from the pixel array, and a pixel for at least one row of pixels simultaneously selected. It has a plurality of amplifier circuits for amplifying signals in parallel, and a scanning circuit for sequentially selecting and scanning the output of the amplifier circuit. The amplifier circuit for amplifying the signal of the pixel in parallel is constituted by a plurality of analog amplifiers. And a plurality of bias current generating circuits for respectively supplying a bias current to the plurality of analog amplifiers, wherein the bias current generating circuit is constituted by a bias current generating MOS transistor, and the bias current generating MOS transistor Is connected to a power supply voltage supply line, and the substrate terminal of the bias current generating MOS transistor is connected to the bias current generating M transistor. The MOS transistor for generating a bias current is connected to the source terminal of the S transistor, and the gate terminal of the MOS transistor for generating the bias current is connected to the power supply voltage supply line via a capacitor, and is connected to the bias voltage supply line via a switch. Means for cutting the output current of the bias current generation circuit, and turning on the switch in a state where the output current of the bias current generation circuit is cut to change the voltage of the bias voltage supply line to the gate of the MOS transistor. A solid-state imaging device having means for storing data in a terminal.

Thus, even if the bias current flows and the voltage of the power supply bus line drops, the voltage drop of the power supply bus line reduces the capacitance provided between the power supply bus line and the gate electrode of the bias current generating transistor. Through the gate electrode of the bias current generating transistor, and the substrate potential is also kept equal to the source potential by connecting the substrate terminal to the source terminal. Is kept constant.

As a result, the influence of the voltage drop at the source terminal is canceled out for both V _GS and V _BS shown in the equation (1), and it becomes possible to suppress the change in the bias current. Can be secured.

[0076]

Therefore, as described above, according to the present invention, the solid-state imaging device having the current source array which suppresses the influence of the wiring resistance of the power supply bus line and enables the stable operation of the line amplifier. An element can be provided.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a current source array used in a solid-state imaging device according to an embodiment of the present invention.

FIG. 2 is a simplified configuration diagram of an image sensor having a conventional line amplifier.

FIG. 3 is a simplified configuration diagram showing a conventional bias current source array generally used in the image sensor of FIG. 2;

[Explanation of symbols]

1-0: Unit circuit 1-1-1, 1-1-2,..., 1-1-j: Bias current generating transistor 1-6: Power bus wiring, Capacitance element: 1-2-1, 1 1-2-2,..., 1-2j, 1-8... Bias voltage supply wiring, switch elements 1-3-1, 1-3-2,.
j, 1-7: first switch control pulse supply wiring, 1-4: inverter, 1-5-1, 1-5-2, ..., 1-5-j: switch element, 2-1: pixel array D1, D2,..., Dj photodiode, S1, S2,..., Sj switch, 2-2 vertical scanning circuit, 2-3 line amplifier array, 2-3-1, 2-3-2, ..., 2-3-j ... each amplifier circuit, 2-4 ... horizontal selection switch array, 2-5 ... output signal line, 2-6 ... horizontal scanning circuit.

Claims (3)

[Claims] 1. A pixel array in which pixels capable of photoelectric conversion are two-dimensionally arranged, a vertical scanning circuit for selecting a readout row of the pixel array, and a signal of the selected one row of pixels. A plurality of amplifier circuits including an analog amplifier that amplifies in parallel; and a plurality of bias currents including a MOS transistor for bias current supply provided for each of the analog amplifiers and supplying a bias current to each analog amplifier. In a solid-state imaging device having a supply circuit and a scanning circuit for sequentially selecting and scanning the output of the amplifier circuit, a source terminal of the MOS transistor is connected to a power supply voltage supply line, and a substrate terminal of the MOS transistor is connected to the MOS transistor.
A solid-state device characterized in that the source terminal of the transistor is connected to the source terminal of the MOS transistor, and the gate terminal of the MOS transistor is connected to the power supply voltage supply line via a capacitive element and connected to the bias voltage supply line via a switch element. Imaging device. 2. A means for cutting off the output current of the bias current generation circuit, and in a state where the output current of the bias current generation circuit is cut off, turning on the switch element to change the voltage of the bias voltage supply line to the MOS. And means for storing data in a gate terminal of the transistor.
The solid-state imaging device according to any one of the preceding claims. 3. A pixel array in which pixels capable of photoelectric conversion are arranged two-dimensionally, a vertical scanning circuit for selecting a readout row of the pixel array, and a signal of the selected one row of pixels. A plurality of amplifier circuits including an analog amplifier that amplifies in parallel; and a plurality of bias currents including a MOS transistor for bias current supply provided for each of the analog amplifiers and supplying a bias current to each analog amplifier. A power supply voltage supply line for supplying a power supply voltage to a source terminal of the MOS transistor, and a power supply voltage supply line for supplying a power supply voltage to a source terminal of the MOS transistor. A bias voltage supply line for supplying a bias voltage via the first switch means, and a gate line and a source terminal of the MOS transistor. An output line for supplying a bias current from the drain of the MOS transistor to the analog amplifier through a second switch means; and exclusively connecting the first switch means and the second switch means. Means for turning on the MOS transistor, wherein a substrate terminal of the MOS transistor is connected to a source terminal of the MOS transistor.