JP2001186114A - Wireless communication terminal and its control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wireless communication terminal that attains transmission reception using a plurality of slots using a simple configuration and to provide its control method. SOLUTION: A reception system 30 is provided with a reception data I/F section 33, that converts recovered clock synchronization reception data into fixed phase synchronization reception data, a transmission system 40 is provided with a transmission data I/F section 42 that converts fixed phase synchronization transmission data into recovered clock synchronization transmission data, and the reception data I/F section 33 and the transmission data I/F section 42 are controlled, so that the sum of the processing delay of the section 42 and the processing delay of the section 33 is constant.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a TDMA (Time
Division Multiple Access) -TDD (Time Division Du
The present invention relates to a wireless communication terminal that performs digital wireless communication by a plex method and a control method thereof, and more particularly to a wireless communication terminal that performs wireless communication with a base station using two or more time slots and a control method thereof.

[0002]

2. Description of the Related Art Conventionally, a PHS (PHS) has been used as a radio communication terminal for performing digital radio communication by the TDMA-TDD system.
2. Description of the Related Art A personal handyphone system (hereinafter referred to as a PHS terminal) is known.

FIG. 10 shows a TDMA used in a PHS terminal.
It is a figure showing a frame.

As shown in FIG. 10, in a TDMA frame used in a PHS terminal, TDMA-TDD using four time slots for each of transmission and reception is used.
The method is adopted.

That is, for one channel, time slots having the same number, such as a transmission first slot for transmission and a reception first slot for reception, are assigned to transmission and reception, respectively. Use to communicate.

FIG. 11 is a block diagram showing a configuration of a transmission / reception system of a conventional PHS terminal.

[0007] The PHS terminal performs communication using one time slot for transmission and reception, respectively. Here, it is assumed that frame synchronization between the PHS terminal and the base station has already been established. The operation will be described.

In FIG. 11, a reception signal received by an antenna 10 is transmitted to a reception system 3 via a radio unit (RF unit) 20.
The signal is added to 0, demodulated and decoded by the demodulation unit 31 and the decoding unit 32 of the reception system 30 and converted into 384 kHz reception data. This 384 kHz burst reception data is represented by T
The data is converted into continuous reception data having a bit rate of 32 kHz by the DMA unit 60 and output.

Further, continuous transmission data having a bit rate of 32 kHz is converted by the TDMA section 60 into burst transmission data of 384 kHz. The 384 kHz burst transmission data is modulated by the modulation unit 41 of the transmission system 40 and transmitted via the RF unit 20 and the antenna 10.

In each of the transmission and reception processes, a 384 kHz transmission rate clock used for transferring data from the receiving system 30 to the TDMA unit 60 and for transferring data from the TDMA unit 60 to the transmitting system 40 is transmitted to the receiving system 30. Clock recovery unit 5 based on the output of demodulation unit 31
A reproduced clock reproduced at 0 is used.

FIG. 12 is a timing chart showing an example of transmission / reception data when the PHS terminal shown in FIG. 11 performs communication using one time slot for transmission / reception.

In FIG. 12, the PHS shown in FIG.
The case where the terminal receives data in the first reception slot shown in FIG. 12A and transmits data in the first transmission slot is shown.

In this case, as shown in FIG. 12B, the reception data of the first reception slot is synchronized with the 384 kHz reproduced clock reproduced by the clock reproducing unit 50.
The transmission data of the first transmission slot is also synchronized with the 384 kHz reproduced clock reproduced by the clock reproducing unit 50.

[0014]

By the way, in a PHS terminal for performing communication using one time slot for each transmission and reception shown in FIG. 11, when realizing 64 Kbps communication and high-speed handover, two time slots are respectively used for transmission and reception. It is necessary to perform the used communication.

FIG. 13 is a timing chart showing an example of transmission / reception data when the PHS terminal shown in FIG. 11 performs communication using two time slots for transmission and reception.

In FIG. 13, the PHS shown in FIG.
13 shows a case where a terminal receives data in the first reception slot and the second reception slot shown in FIG. 13A and transmits data in the first transmission slot and the second transmission slot.

In this case, the clock reproducing unit 50 reproduces a clock between the first reception slot and the second reception slot shown in FIG. 13B, outputs received data synchronized with the reproduced clock, and In the transmission first slot and the transmission second slot, the reception first slot and the reception second
The transmission data is output using the reproduction clock reproduced during the slot.

However, in high-speed handover or 64 kbps communication in which two time slots are used for transmission and reception, respectively, burst signals of two time slots may be received from different base stations, or fading may occur in only one of the slots. And the clock phase may be different between the two slots.

As a result, the clock reproducing unit 50 reproduces the clock from the burst generated based on the clocks having different phases, so that the clock is correctly reproduced depending on the response speed of the clock reproducing unit 50. There is no case.

Even if the response speed of the clock reproducing unit 50 is high, clocks having different phases for each slot are supplied to the TDMA unit 60 which performs processing based on the reproduced clock output from the clock reproducing unit 50. Therefore, the design of the TDMA unit 60 requires a maximum of 1b.
it has to take into account the clock jitter,
As a result, the circuit configuration becomes complicated.

FIG. 14 is a block diagram showing another configuration of the transmission / reception system of the conventional PHS terminal.

In the configuration shown in FIG. 14, two systems of clock recovery units 51 and 52 are provided, and these two systems of clock recovery units 51 and 52 are controlled by a slot control unit 54 which receives slot information from the TDMA unit 60. In addition to the control, the outputs of the clock reproducing units 51 and 52 are switched by a selector 53 controlled by a slot control unit 54 and selectively output.

In this case as well, clocks having different phases are supplied to the TDMA unit 60 for each slot. Therefore, the design of the TDMA unit 60 must consider a maximum of 1-bit clock jitter. as a result,
The circuit configuration becomes complicated.

Further, in order to avoid these problems,
A configuration in which each of the transmission / reception system and the clock recovery system has two systems is also conceivable. However, when such a configuration is adopted, the circuit scale increases, and the cost and the mounting area increase.

It is an object of the present invention to provide a radio communication terminal capable of transmitting and receiving using a plurality of slots with a simple configuration and a control method therefor.

[0026]

According to one aspect of the present invention, there is provided a wireless communication terminal for performing digital wireless communication according to the TDMA-TDD system, wherein each of the received signals received in a plurality of time slots is received from a plurality of time slots. Clock recovery means for recovering clocks of independent phases;
A reception data interface unit having a first processing delay and converting reception data synchronized with a reproduction clock reproduced by the clock reproduction unit into reception data synchronized with a fixed-phase clock; A transmission data interface unit having a second processing delay whose sum is controlled to be constant, and converting transmission data synchronized with the clock of the fixed phase into transmission data synchronized with a reproduced clock reproduced by the clock reproducing unit; It is characterized by having.

According to a second aspect of the present invention, in the first aspect of the present invention, the clock recovery means includes a plurality of clock recovery circuits for recovering a clock from a received signal, and a plurality of clock recovery circuits for each time slot. And a slot control means for switching the clock recovery circuit.

According to a third aspect of the present invention, in the first aspect of the present invention, the clock recovery means includes a clock recovery circuit that recovers a clock from a received signal.
A processing progress holding register that holds a part of the processing progress of the clock recovery circuit for each time slot; and a register control unit that controls the processing progress holding register corresponding to the time slot. I do.

According to a fourth aspect of the present invention, in the first aspect of the present invention, the reception data interface means and the transmission data interface means include a reproduction clock reproduced by the clock reproduction means and a clock having the fixed phase. Is characterized in that each processing delay is dynamically controlled in accordance with the phase difference.

[0030] The invention according to claim 5 is characterized in that TDMA-
In a method for controlling a wireless communication terminal that performs digital wireless communication according to the TDD method, clocks having independent phases are respectively recovered from received signals received in a plurality of time slots, and received data respectively synchronized with the reproduced clocks is stored as a first data. The transmission delay synchronized with the clock of the fixed phase is converted into the transmission data synchronized with the clock of the fixed phase by the processing delay of the After the conversion, the sum of the first processing delay and the second processing delay is controlled to be constant regardless of the phase difference between the reproduction clock and the fixed-phase clock.

According to a sixth aspect of the present invention, in the fifth aspect, a plurality of clock recovery circuits for recovering a clock from a received signal are provided, and the plurality of clock recovery circuits are provided for each time slot. The clock is reproduced by switching.

According to a seventh aspect of the present invention, in the invention of the fifth aspect, a part of a process of clock recovery for recovering a clock from a received signal is held for each time slot, and the held time is held. It is characterized in that clock recovery of another time slot is performed using a part of the process of clock recovery.

The invention according to claim 8 is the invention according to claim 5, wherein the first processing delay and the second processing are performed in accordance with a phase difference between the reproduction clock and the fixed-phase clock. The delay is dynamically controlled.

[0034]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a radio communication terminal and a control method therefor according to the present invention will be described below in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a configuration of a transmission / reception system of a PHS terminal to which the radio communication terminal and the control method according to the present invention are applied.

In FIG. 1, the transmission / reception system of the PHS terminal 100 includes an antenna 10, a radio unit (RF unit) 20, a reception system 30, a transmission system 40, a clock recovery unit 50, and a TDMA unit 60. .

Here, the receiving system 30 includes a demodulation unit 31, a decoding unit 32, a reception data interface unit (a reception data I /
F section) 33, and the transmission system 40 includes a modulation section 41, a transmission data interface section (transmission data I / F).
) 42.

In the PHS terminal 100 of this embodiment, two systems are prepared as transmission rate clocks.
One of the transmission rate clocks is a reproduced clock reproduced by the clock reproducing unit 50 based on the received signal.
One is a fixed-phase transmission rate clock.

Here, the reproduced clock reproduced by the clock reproducing unit 50 is used for the decoding process in the decoding unit 32 of the receiving system 30 and the modulation process in the modulating unit 41 of the transmitting system 40.

Also, the fixed-phase transmission rate clock is:
Reception data I / F unit 33, transmission data I / F unit 42, T
It is added to the DMA unit 60.

The burst reception signal received by the antenna 10 is applied to the demodulation unit 31 of the reception system 30 via the RF unit 20, where it is demodulated into reception data.

The clock reproducing unit 50 is provided with a demodulating unit 31.
A clock recovery process is performed based on the demodulated output of, and a clock is recovered from the received signal.

The decoding section 32 decodes the reception data demodulated by the demodulation section 31 using the reproduction clock reproduced by the clock reproduction section 50, and adds it to the reception data I / F section 33.

The reception data I / F unit 33 has a fixed-phase transmission rate clock added thereto, performs phase control of the reception data output from the decoding unit 32 using the fixed-phase transmission rate clock, and outputs 384 kHz. Is output to the TDMA unit 60 as the received data in a burst.

The TDMA unit 60 converts the 384 kHz burst received data input from the received data I / F unit 33 of the receiving system 30 into continuous received data of 32 kHz and outputs it as received data.

On the other hand, the continuous transmission data of 32 kHz inputted to the TDMA
is converted into burst transmission data of kHz, and the transmission system 4
0 is added to the transmission data I / F section 42.

The transmission data I / F section 42 receives the reproduction clock reproduced by the clock reproduction section 50 and the reception data I / F.
A fixed-phase transmission rate clock applied to the F unit 33 is input, and the phase of the transmission data is adjusted so that the sum of the processing delay of the reception data I / F unit 33 and the processing delay of the transmission data I / F unit 42 becomes constant. Perform control.

The transmission data whose phase is controlled by the transmission data I / F unit 42 is modulated by the modulation unit 41 and
It is transmitted via the antenna 10.

That is, in this embodiment, the reception system 30 is provided with the reception data I / F unit 33 for converting the reproduction clock synchronization reception data into the fixed phase synchronization reception data, and the transmission system 40 transmits the fixed phase synchronization transmission data to the transmission system 40. Transmission data I / F 4 for converting to reproduction clock synchronous transmission data
2 is provided to control the sum of the processing delay of the reception data I / F unit 33 and the processing delay of the transmission data I / F unit 42 to be constant.

It should be noted that the configuration of FIG.
If the clock recovery unit 50 cannot operate at a sufficiently high speed, a plurality of clock recovery units may be provided to switch between them. May be configured,
Further, a configuration may be adopted in which some registers of the clock recovery unit are multiplexed and switched and used for each slot.

FIG. 2 is a block diagram showing another embodiment of the PHS terminal according to the present invention, which is provided with a plurality of clock recovery units.

In the PHS terminal 200 shown in FIG.
Instead of the clock recovery unit 50 shown in FIG. 1, a clock recovery system 510 including two systems of clock recovery units 511 and 512, a selector 513, and a slot control unit 514 is provided.

This configuration is similar to that of the clock recovery units 511 and 51.
In a configuration that does not require a high-speed operation as 2, the two clock recovery units 511 and 512 are controlled by a slot control unit 514 that inputs slot information from the TDMA unit 60, and the two clock recovery units 5 are controlled by a selector 513.
11 and 512 by switching, the decoding unit 32 of the reception system 30 and the transmission data I / F unit 42 and the modulation unit 4 of the transmission system 40.
It is configured to add to 1.

FIG. 3 is a block diagram showing another embodiment of the PHS terminal according to the present invention in which some registers of the clock recovery unit are multiplexed.

In the PHS terminal 300 shown in FIG.
Instead of the clock reproducing unit 50 shown in FIG. 1, a clock reproducing system 520 including a clock reproducing unit 521, a processing progress holding register 522, and a register control unit 523 is provided.

In this configuration, the clock recovery units 511 and 51
2 is a configuration that does not require a high-speed operation, stores the processing progress of the clock generation unit 521 in a processing progress holding register 522, and registers the information stored in the processing progress holding register 522 as slot information from the TDMA unit 60. It is configured to be controlled by the unit 523.

FIG. 4 is a block diagram showing a specific example of the reception data I / F section 33 of the PHS terminal shown in FIGS.

In FIG. 4, the P shown in FIGS.
An example in which the reception data I / F unit 33 of the HS terminal is configured using a flip-flop 331 is shown.

Here, the data input D of the flip-flop 331 receives the reproduced clock synchronous reception data output from the decoder 32 shown in FIGS. 1 to 3, and the clock input CK has a fixed phase. A transmission rate clock is input. Then, the output Q of the flip-flop 331
Outputs fixed phase clock reception data synchronized with the fixed phase transmission rate clock.

That is, the flip-flop 331 constituting the reception data I / F unit 33 latches the reproduction clock synchronous reception data output from the decoding unit 32 with a fixed-phase transmission rate clock supplied to the TDMA unit 60, and
It is supplied to the DMA unit 60.

In this configuration, the reception data I / F unit 3
The processing delay in the flip-flop 331 constituting 3 differs depending on the phase difference between the reproduced clock and the fixed-phase transmission rate clock (fixed-phase clock).

FIG. 5 is a timing chart showing a processing delay by the reception data I / F unit 33 shown in FIG.

In FIG. 5, RCK shown in FIGS. 5A to 5J indicates a reproduction clock (reproduction bit rate clock), and MRD indicates a reproduction clock synchronization output in synchronization with the reproduction clock. The reception data (modem reception data) is shown. Here, the control width of the clock phase is set to 0.1 bit.

That is, in FIG. 5, FIG.
The phase difference between the reproduction clock and the fixed phase clock is 1.0b
In this case, when the reproduced clock synchronous reception data is latched by the reception data I / F unit 33 shown in FIG. 4, the processing delay in the reception data I / F unit 33 becomes 1.0 bit.

FIG. 5B shows a case where the phase difference between the reproduction clock and the fixed phase clock is 0.1 bit. In this case, the reproduction clock synchronous reception data is represented by the reception data I / O shown in FIG. When latched by the F unit 33, the processing delay in the reception data I / F unit 33 becomes 0.1 bit.

Similarly, FIGS. 5C to 5J show that the phase difference between the reproduced clock and the fixed phase clock is 0.2 bit.
In this case, when the reproduced clock synchronous reception data is latched by the reception data I / F unit 33 shown in FIG.
3, the processing delay is 0.2 bits to 0.9 bits, respectively.
it.

By the way, the TDMA section 60 generates transmission data based on the timing of the reception data. If the processing delay in the reception system is different at that time, the transmission timing of the transmission data changes accordingly. That is, the change in the processing delay of the receiving system corresponds to the transmission jitter.

The receiving system 3 shown in FIGS.
At 0, the processing delay ranges from 0.1 bit to 1.0 bit as shown in FIG. 5, and this processing delay always changes during reception. The transmission jitter caused by the processing delay of the processing system 30 becomes a problem in system operation.

Here, in order to absorb the transmission jitter, a configuration in which the transmission timing of the transmission data is dynamically changed in the TDMA unit 60 may be considered. It is not preferable to change dynamically because the circuit configuration becomes complicated.

Therefore, in the present embodiment, the transmission jitter is reduced by controlling the sum of the processing delay in reception data I / F section 33 and the processing delay in transmission data I / F section 42 to be constant. It is configured to absorb.

FIG. 6 is a block diagram showing a specific example of the transmission data I / F section 42 of the PHS terminal shown in FIGS.

In FIG. 6, transmission data I / F section 42
Are two flip-flops 421, 422 and 0.9b
and an it delay circuit 423.

Here, fixed phase synchronous transmission data synchronized with the fixed phase transmission rate clock output from the TDMA unit 60 is input to the data input D of the flip-flop 421, and the fixed phase synchronous transmission data is input to the clock input CK. A clock obtained by delaying the transmission rate clock (fixed phase clock) by 0.9 bit by the 0.9-bit delay circuit 423 is input, and the data input D of the flip-flop 422 is 0.9 bi output from the output Q of the flip-flop 421.
The transmission data delayed by t is input and the clock input CK is input.
Is supplied with a reproduction clock.

That is, the transmission data I / F shown in FIG.
In the section 42, first, the fixed phase synchronous transmission data output from the TDMA section 60 is
3 is latched with the 0.9-bit delay fixed phase clock output from 3 and the latched transmission data is again latched with the reproduction clock to convert the fixed phase synchronization transmission data into the reproduction clock synchronization transmission data.

The transmission data I / F section 42 controls the processing delay so that the sum of the processing delay and the processing delay in the reception data I / F section 33 is constant.

FIG. 7 is a timing chart showing a processing delay by the transmission data I / F unit 42 shown in FIG.

In FIG. 7, RCK shown in FIGS. 7A to 7J indicates a reproduction clock (reproduction bit rate clock), and MTD indicates a reproduction clock synchronization converted in synchronization with the reproduction clock. The transmission data (modem internal transmission data) is shown. Here, the received data I /
The control width of the clock phase is set to 0.1 bit similarly to the F section 33.
7 (A) to 7 (J) correspond to FIGS. 5 (A) to 5 (J) shown in FIG.

That is, in FIG. 7, FIG.
The phase difference between the reproduction clock and the fixed phase clock is 1.0b
In this case, the fixed phase synchronous transmission data is transmitted by the transmission data I / F unit 42 shown in FIG.
It is converted and output to the reproduction clock synchronous transmission data delayed by 1.0 bit.

FIG. 7B shows a case where the phase difference between the reproduced clock and the fixed phase clock is 0.1 bit. In this case, the fixed phase synchronous transmission data is the transmission data shown in FIG. The I / F 42 converts the data into reproduced clock synchronous transmission data delayed by 1.9 bits and outputs the data.

Similarly, FIGS. 7C to 7J show that the phase difference between the reproduced clock and the fixed phase clock is 0.2 bit.
6 to 0.9 bits. In this case, the fixed phase synchronous transmission data is 1.8 bits to 1.1 bi at the transmission data I / F unit 42 shown in FIG.
The data is converted into reproduced clock synchronous transmission data delayed by t and output.

FIG. 8 is a diagram showing the relationship between the processing delay by the reception data I / F unit 33 shown in FIG. 4 and the processing delay by the transmission data I / F unit 42 shown in FIG.

In FIG. 8, the phase difference between the reproduced clock and the fixed phase clock is 1.0 bit, 0.1 bit or more.
Received data I / in the case of 0.9 bits (A to J)
The processing delay by the F unit 33 and the processing delay by the transmission data I / F unit 42 are shown.

As is clear from FIG. 8, regardless of the phase relationship between the reproduced clock and the fixed phase clock, the processing delay by the reception data I / F section 33 and the transmission data I / F
The sum with the processing delay by the unit 42 is constant (2.0 bits), which indicates that the transmission jitter is absorbed.

The processing delay in the reception data I / F unit 33 and the transmission data I / F unit 42 is such that the phase of the reproduction clock in the reception slot is updated, but the transmission in the transmission slot of the same slot number is performed. It is assumed that it has been done. This is because the processing delay changes when the phase relationship between the recovered clock and the fixed phase clock changes between reception and transmission.

When the phase relationship differs between reception and transmission, it is necessary to incorporate a configuration for dynamically changing the processing delay into the reception data I / F unit 33 or the transmission data I / F unit 42.

FIG. 9 is a block diagram showing another configuration of transmission data I / F section 42 incorporating a configuration for dynamically changing the processing delay.

In FIG. 9, transmission data I / F unit 4
2 detects the phase difference between the reproduced clock and the fixed phase clock by the phase difference detection circuit 424,
The transmission data I / F is controlled by controlling the delay amount of the delay circuit 425 that delays the fixed-phase synchronous transmission data output from the TDMA unit 60 based on the phase difference between the recovered clock and the fixed-phase clock detected in Step 4. The processing delay in the section 42 is dynamically controlled.

[0088]

As described above, according to the present invention,
In a control method of a wireless communication terminal performing digital wireless communication according to a TDMA-TDD method, clocks having independent phases are respectively recovered from received signals received in a plurality of time slots, and received data respectively synchronized with the reproduced clocks are reproduced. The first processing delay converts the received data synchronized with the fixed phase clock into the received data, and the second processing delay converts the transmission data synchronized with the reproduced clock reproduced by the clock reproducing means with the second processing delay. Into the data, the first processing delay and the second
And the sum of the processing delays is controlled so as to be constant regardless of the phase difference between the reproduced clock and the fixed-phase clock. There is an effect that the used communication becomes possible.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a transmission / reception system of a PHS terminal configured by applying a wireless communication terminal and a control method thereof according to the present invention.

FIG. 2 is a block diagram showing another embodiment of the PHS terminal according to the present invention, which is provided with a plurality of clock recovery units.

FIG. 3 is a block diagram showing another embodiment of the PHS terminal according to the present invention in which some registers of the clock recovery unit are multiplexed.

FIG. 4 is a block diagram showing a specific example of a reception data I / F unit 33 of the PHS terminal shown in FIGS. 1 to 3;

FIG. 5 is a timing chart showing a processing delay caused by a reception data I / F unit 33 shown in FIG. 4;

FIG. 6 is a block diagram showing a specific example of a transmission data I / F unit 42 of the PHS terminal shown in FIGS. 1 to 3;

7 is a timing chart showing a processing delay caused by a transmission data I / F unit shown in FIG. 6;

8 is a diagram showing a relationship between a processing delay by the reception data I / F unit 33 shown in FIG. 4 and a processing delay by the transmission data I / F unit 42 shown in FIG. 6;

FIG. 9 is a block diagram showing another configuration of the transmission data I / F unit incorporating a configuration for dynamically changing the processing delay.

FIG. 10 is a diagram illustrating a TDMA frame used in a PHS terminal.

FIG. 11 is a block diagram showing a configuration of a transmission / reception system of a conventional PHS terminal.

12 is a timing chart showing an example of transmission / reception data when the PHS terminal shown in FIG. 11 performs communication using one time slot for transmission and reception, respectively.

13 is a timing chart showing an example of transmission / reception data when the PHS terminal shown in FIG. 11 performs communication using two time slots for transmission and reception, respectively.

FIG. 14 is a block diagram showing another configuration of the transmission / reception system of the conventional PHS terminal.

[Explanation of symbols]

Reference Signs List 10 antenna 20 radio unit (RF unit) 30 reception system 31 demodulation unit 32 decoding unit 33 reception data interface unit (reception data I /
F section) 40 transmission system 41 modulation section 42 transmission data interface section (transmission data I /
F section) 50 clock recovery section 60 TDMA section 100, 200, 300 PHS terminal 510 Clock recovery system 511, 512 Clock recovery section 513 Selector 514 Slot control section 520 Clock recovery system 521 Clock recovery section 522 Processing progress holding register 523 Register control section

Claims (8)

[Claims] 1. A wireless communication terminal for performing digital wireless communication according to the TDMA-TDD method, comprising: clock recovery means for recovering clocks having independent phases from received signals received in a plurality of time slots; Receiving data interface means for converting received data synchronized with a reproduced clock reproduced by the clock reproducing means into received data synchronized with a fixed-phase clock; and wherein the sum of the first processing delay is controlled to be constant. Transmission data interface means having a second processing delay and converting transmission data synchronized with the clock of the fixed phase into transmission data synchronized with the reproduced clock reproduced by the clock reproducing means. Wireless communication terminal. 2. The clock regenerating means comprises: a plurality of clock regenerating circuits for regenerating a clock from a received signal; and a slot control means for switching the plurality of clock regenerating circuits for each time slot. The wireless communication terminal according to claim 1. A clock recovery circuit configured to recover a clock from a received signal; a processing progress holding register configured to store a part of a processing progress of the clock recovery circuit for each time slot; 2. The wireless communication terminal according to claim 1, further comprising: register control means for controlling a processing progress holding register corresponding to the time slot. 4. The reception data interface unit and the transmission data interface unit dynamically control respective processing delays in accordance with a phase difference between a clock recovered by the clock recovery unit and a clock of the fixed phase. The wireless communication terminal according to claim 1, wherein 5. A method for controlling a radio communication terminal that performs digital radio communication according to a TDMA-TDD method, wherein clocks having independent phases are respectively reproduced from received signals received in a plurality of time slots, and the reproduced clocks are respectively reproduced. The synchronous reception data is converted into the reception data synchronized with the fixed-phase clock with the first processing delay, and the transmission data synchronized with the fixed-phase clock is reproduced with the second processing delay by the clock reproduction unit. The transmission data is converted into transmission data synchronized with a clock, and the sum of the first processing delay and the second processing delay is controlled to be constant regardless of the phase difference between the reproduction clock and the fixed-phase clock. A method for controlling a wireless communication terminal. 6. The apparatus according to claim 5, further comprising a plurality of clock recovery circuits for recovering a clock from the received signal, wherein the plurality of clock recovery circuits are switched for each time slot to recover a clock. A method for controlling a wireless communication terminal. 7. A part of a process of clock recovery for recovering a clock from a received signal is held for each time slot, and a part of the held process of clock recovery is used for another time slot. The method for controlling a wireless communication terminal according to claim 5, wherein clock recovery is performed. 8. The method according to claim 5, wherein the first processing delay and the second processing delay are dynamically controlled in accordance with a phase difference between the reproduced clock and the fixed-phase clock. The control method of the wireless communication terminal described in the above.