JP2001177580A - Impedance adapting system - Google Patents
Impedance adapting systemInfo
- Publication number
- JP2001177580A JP2001177580A JP36133999A JP36133999A JP2001177580A JP 2001177580 A JP2001177580 A JP 2001177580A JP 36133999 A JP36133999 A JP 36133999A JP 36133999 A JP36133999 A JP 36133999A JP 2001177580 A JP2001177580 A JP 2001177580A
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- output terminal
- transmission line
- impedance
- transmission
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Logic Circuits (AREA)
- Dc Digital Transmission (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、高周波数の電気信
号が伝播する伝送線路に対するインピーダンス適合を行
うインピーダンス適合システムに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an impedance matching system for performing impedance matching on a transmission line through which a high-frequency electric signal propagates.
【０００２】[0002]
【従来の技術】パソコンなどのデジタル電子機器には、
画像データや音声データなどの大量のデータを短時間に
高速度で処理することが要求され、その動作周波数は加
速度的に上昇している。このように動作周波数が高くな
ると、単位時間で処理できるデータ量が増加し、データ
の処理時間が短縮可能になるが、その反面でクロストー
クや反射という高速伝送線路特有のノイズが発生し、電
子機器に誤動作などの悪影響が発生するおそれがある。2. Description of the Related Art Digital electronic devices such as personal computers include:
It is required to process a large amount of data such as image data and audio data at high speed in a short time, and the operating frequency thereof is increasing at an accelerated rate. As the operating frequency increases, the amount of data that can be processed in a unit time increases, and the data processing time can be shortened. However, on the other hand, noise unique to high-speed transmission lines, such as crosstalk and reflection, is generated. There is a possibility that adverse effects such as malfunctions may occur on the device.
【０００３】この問題を解決するために、従来はダンピ
ング抵抗の直列終端による処理が行われており、この場
合には、図６に示すように、送信端信号源１１の出力イ
ンピーダンスと、直列接続されるダンピング抵抗Ｒｔと
の和が、回路基板上の伝送線路１２の特性インピーダン
スＺｏに等しくなるように、ダンピング抵抗Ｒｔの抵抗
値が選択される。このようにすると、図６に示すよう
に、ダンピング抵抗Ｒｔの送信側信号源１１と接続され
る一端をＡ’とし、ダンピング抵抗Ｒｔの他端をＢ’と
して、図７に示すように、Ｂ’点の電圧Ｖ（Ｂ’）は、
Ａ’点の電圧Ｖ（Ａ’）の１／２となり、伝送線路１２
の受信端Ｃ’からの反射波が重畳されて、伝送線路１２
上の電圧振幅は、正規のレベルを保持することになり、
信号波形の乱れは生じなくなる。In order to solve this problem, processing by a series termination of a damping resistor is conventionally performed. In this case, as shown in FIG. 6, the output impedance of the transmitting end signal source 11 and the series connection are controlled. The resistance value of the damping resistor Rt is selected such that the sum with the damping resistor Rt becomes equal to the characteristic impedance Zo of the transmission line 12 on the circuit board. In this case, as shown in FIG. 6, one end of the damping resistor Rt connected to the transmission-side signal source 11 is denoted by A ′, and the other end of the damping resistor Rt is denoted by B ′, and as shown in FIG. The voltage V (B ') at the point is
It is （of the voltage V (A ′) at the point A ′, and the transmission line 12
The reflected wave from the receiving end C ′ is superimposed on the transmission line 12 ′.
The upper voltage swing will hold the normal level,
Disturbance of the signal waveform does not occur.
【０００４】[0004]
【発明が解決しようとする課題】しかし、実際の電子製
品に使用されている多層回路基板には、製造誤差が存在
するために、導体パターン幅や層間絶縁層の厚みにばら
つきがあり、これが原因で特性インピーダンスにばらつ
きが生じてしまう。また、特性インピーダンスに対し
て、基板表面上に形成されたテストパターンのインピー
ダンスを測定して、特性インピーダンスの測定値として
いるために、スルーホールを介して、表層と内層とにわ
たって形成される伝送線路の特性インピーダンスは、テ
ストパターンのインピーダンスとは異なってしまう。こ
のために、テストパターンで得られた特性インピーダン
スに基づいて、前述したようにして、伝送線路に対して
ダンピング抵抗を接続しても、反射ノイズを充分に抑え
ることはできない。However, in a multilayer circuit board used in an actual electronic product, there are variations in the width of the conductor pattern and the thickness of the interlayer insulating layer due to manufacturing errors. Causes variation in characteristic impedance. In addition, since the impedance of the test pattern formed on the substrate surface is measured with respect to the characteristic impedance and used as the measured value of the characteristic impedance, the transmission line formed through the surface layer and the inner layer via the through hole. Is different from the impedance of the test pattern. For this reason, even if a damping resistor is connected to the transmission line based on the characteristic impedance obtained by the test pattern as described above, the reflection noise cannot be sufficiently suppressed.
【０００５】本発明は、高周波電気信号が伝播される伝
送線路に対する前述したようなインピーダンス適合の現
状に鑑みてなされたものであり、その目的は、伝送線路
の実際の特性インピーダンスに基づいて、常に適確なイ
ンピーダンス適合を行うことが可能なインピーダンス適
合システムを提供することにある。The present invention has been made in view of the above-described current state of impedance matching with respect to a transmission line through which a high-frequency electric signal is propagated, and its object is to always use the actual characteristic impedance of the transmission line. An object of the present invention is to provide an impedance matching system capable of performing accurate impedance matching.
【０００６】[0006]
【課題を解決するための手段】前記目的を達成するため
に、請求項１記載の発明は、送信側信号源からの高周波
電気信号が伝播される伝送線路に対して、前記伝送線路
の特性インピーダンスに適合する抵抗値の調整抵抗の挿
入接続を行うインピーダンス適合システムであり、前記
抵抗値の選択の切換を行う選択スイッチを備え、該選択
スイッチの切換により選択される抵抗値の調整抵抗を、
前記伝送線路に直列に挿入接続する調整抵抗接続ユニッ
トと、該調整抵抗接続ユニットの出力側端子と前記伝送
線路との接続点の電圧レベルを、前記送信側信号源の出
力端子の電圧レベルの１／２に一致させ、または近似的
に一致させるように、前記選択スイッチの切換制御を行
う制御手段とを有することを特徴とするものである。In order to achieve the above object, according to the present invention, the characteristic impedance of the transmission line is set relative to the transmission line through which the high-frequency electric signal from the transmission-side signal source is propagated. An impedance matching system that performs an insertion connection of an adjustment resistor having a resistance value that conforms to, comprising a selection switch that switches selection of the resistance value, and an adjustment resistor having a resistance value selected by switching the selection switch.
An adjusting resistor connection unit that is inserted and connected in series with the transmission line; and a voltage level at a connection point between an output terminal of the adjusting resistor connection unit and the transmission line is set to one of a voltage level of an output terminal of the transmission signal source. And control means for performing switching control of the selection switch so as to match or approximately match with / 2.
【０００７】このような手段によると、実際の電圧検出
に基づいて、製造誤差に起因してばらつきを有する伝送
線路の特性インピーダンスに、適確に対応するインピー
ダンス適合が行われ、波形ひずみのない信号の伝送が行
われ、反射ノイズの発生が完全に防止され、或いは反射
ノイズが大幅に低減される。[0007] According to such means, based on actual voltage detection, impedance matching is accurately performed corresponding to the characteristic impedance of the transmission line having variations due to manufacturing errors, and a signal without waveform distortion is obtained. Is transmitted, and the occurrence of reflected noise is completely prevented, or the reflected noise is greatly reduced.
【０００８】[0008]
【発明の実施の形態】以下に、本発明の一実施の形態
を、図１ないし図５を参照して説明する。図１は本実施
の形態が伝送線路に適用された場合の全体構成を示す説
明図、図２は本実施の形態の概略構成を示すブロック
図、図３は本実施の形態の構成を示す回路説明図、図４
は図３のスイッチ素子の構成を示す回路図、図５は本実
施の形態の動作を示すフローチャートである。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is an explanatory diagram showing an overall configuration when the present embodiment is applied to a transmission line, FIG. 2 is a block diagram showing a schematic configuration of the present embodiment, and FIG. 3 is a circuit showing a configuration of the present embodiment. Explanation diagram, FIG.
Is a circuit diagram showing the configuration of the switch element in FIG. 3, and FIG. 5 is a flowchart showing the operation of the present embodiment.
【０００９】本実施の形態は、図１に示すように、従来
の方式によりダンピング抵抗Ｒｔが接続された伝送線路
１２に適用された例であり、伝送線路１２に対して挿入
配設される調整抵抗接続制御系ユニット１が設けられ、
この調整抵抗接続制御系ユニット１は、伝送線路１２の
実際の特性インピーダンスに基づいて、調整抵抗を選択
し、選択した調整抵抗によって、反射ノイズを防止する
インピーダンス適合を行う機能を有している。この調整
抵抗接続制御ユニット１には、図２に示すように、全体
の制御を行うＣＰＵ２が設けられ、このＣＰＵ２には、
制御動作のプログラムが格納されたＲＯＭ６が接続さ
れ、さらに、伝送線路１２に接続される調整抵抗を選択
する抵抗選択コントローラ３が接続されている。As shown in FIG. 1, the present embodiment is an example in which the present invention is applied to a transmission line 12 to which a damping resistor Rt is connected by a conventional method. A resistance connection control system unit 1 is provided,
The adjustment resistor connection control system unit 1 has a function of selecting an adjustment resistor based on the actual characteristic impedance of the transmission line 12 and performing impedance matching for preventing reflection noise using the selected adjustment resistor. As shown in FIG. 2, the adjustment resistor connection control unit 1 is provided with a CPU 2 for performing overall control.
A ROM 6 storing a control operation program is connected, and further, a resistance selection controller 3 for selecting an adjustment resistor connected to the transmission line 12 is connected.
【００１０】また、抵抗選択コントローラ３の入力端子
には、送信側信号源１１の出力端子Ａが接続され、抵抗
選択コントローラ３の出力端子には、抵抗選択コントロ
ーラ３により選択される複数の調整抵抗が配置された抵
抗配置ブロック５が接続されている。そして、抵抗配置
ブロック５の出力端子Ｂが、インピーダンス適合が行わ
れる伝送線路１２とＣＰＵ２とに接続され、送信側信号
源１１の出力端子ＡがＣＰＵ２に接続されており、この
ＣＰＵ２には、送信側信号源１１の出力端子Ａの電圧
と、抵抗配置ブロック５の出力端子Ｂの電圧とを検出す
る電圧検出手段が設けられている。An output terminal A of the transmission-side signal source 11 is connected to an input terminal of the resistance selection controller 3, and a plurality of adjustment resistors selected by the resistance selection controller 3 are connected to an output terminal of the resistance selection controller 3. Are connected. The output terminal B of the resistor arrangement block 5 is connected to the transmission line 12 where impedance matching is performed and the CPU 2, and the output terminal A of the transmission-side signal source 11 is connected to the CPU 2. A voltage detecting means for detecting the voltage of the output terminal A of the side signal source 11 and the voltage of the output terminal B of the resistor arrangement block 5 is provided.
【００１１】ところで、本実施の形態は、図３に示すよ
うに、すでに送信側信号源１１の出力端子Ａに、従来の
方式によって、ダンピング抵抗Ｒｔが接続されている場
合に適用されており、抵抗選択コントローラ３に設けら
れたスイッチ素子７ａ〜７ｎの入力側端子は、送信側信
号源１１の出力端子Ａに一端が接続されたダンピング抵
抗Ｒｔの他端に接続されている。また、スイッチ素子７
ａ〜７ｎの出力側端子は、それぞれ、抵抗配置ブロック
５の抵抗Ｒ１〜Ｒｎの一端にそれぞれ接続され、抵抗Ｒ
１〜Ｒｎの他端は、抵抗配置ブロック５の出力端子Ｂに
接続されている。そして、ＣＰＵ２には、スイッチ素子
７ａ〜７ｎに制御信号を出力するポートＰ１〜Ｐｎが設
けられ、ポートＰ１〜Ｐｎは、スイッチ素子７ａ〜７ｎ
の制御端子にそれぞれ接続されている。By the way, as shown in FIG. 3, the present embodiment is applied to a case where a damping resistor Rt is already connected to the output terminal A of the transmission-side signal source 11 by a conventional method. The input terminals of the switch elements 7 a to 7 n provided in the resistance selection controller 3 are connected to the other end of the damping resistor Rt, one end of which is connected to the output terminal A of the transmission signal source 11. Also, the switch element 7
a to 7n are connected to one ends of resistors R1 to Rn of the resistor arrangement block 5, respectively.
The other ends of 1 to Rn are connected to the output terminal B of the resistor arrangement block 5. The CPU 2 is provided with ports P1 to Pn for outputting control signals to the switch elements 7a to 7n, and the ports P1 to Pn are connected to the switch elements 7a to 7n.
Are connected respectively to the control terminals.
【００１２】一方、スイッチ素子７ａ〜７ｎは、全て同
一の構成となっていて、図４でスイッチ素子７ａを取り
上げて説明すると、トランジスタ１０のベースが、ダン
ピング抵抗Ｒｔを介して送信側信号源１１の出力端子Ａ
に接続され、トランジスタ１０のコレクタが、ＣＰＵ２
のポートＰ１に接続され、トランジスタ１０のエミッタ
とアース間にプルダウン抵抗Ｒｐが接続され、トランジ
スタ１０のエミッタとプルダウン抵抗Ｒｐの接続点が、
抵抗配置ブロック５の抵抗Ｒ１に接続されている。On the other hand, the switching elements 7a to 7n all have the same configuration. If the switching element 7a is described with reference to FIG. 4, the base of the transistor 10 is connected to the transmission-side signal source 11 via a damping resistor Rt. Output terminal A
And the collector of the transistor 10 is connected to the CPU 2
, A pull-down resistor Rp is connected between the emitter of the transistor 10 and the ground, and a connection point between the emitter of the transistor 10 and the pull-down resistor Rp is
It is connected to the resistor R1 of the resistor arrangement block 5.
【００１３】このような構成の本実施の形態の動作を、
図５のフローチャートを参照して説明する。図５のフロ
ーチャートのステップＳ１で、ＲＯＭ６に格納されてい
る制御プログラムを取込んで作動するＣＰＵ２の指令に
よって、先ず、ポートＰ１から制御信号が出力され、こ
の制御信号がスイッチ素子７ａのトランジスタ１０のコ
レクタに入力される。このために、スイッチ素子７ａの
トランジスタ１０はＯＮ状態となり、トランジスタ１０
のベースと抵抗Ｒ１間が接続され、トランジスタ１０の
ベースと抵抗配置ブロック５の出力端子Ｂとの間に調整
抵抗として抵抗Ｒ１が接続された状態となる。この状態
では、送信側信号源１１の出力端子Ａから発信される信
号は、ダンピング抵抗Ｒｔと抵抗Ｒ１を通過して、抵抗
配置ブロック５の出力端子Ｂに接続される伝送線路１２
に送信される。The operation of the present embodiment having such a configuration is described below.
This will be described with reference to the flowchart of FIG. In step S1 of the flowchart of FIG. 5, a control signal is first output from the port P1 in response to a command from the CPU 2 which operates by fetching a control program stored in the ROM 6, and this control signal is transmitted to the transistor 10 of the switch element 7a. Input to the collector. Therefore, the transistor 10 of the switch element 7a is turned on, and the transistor 10
Is connected to the resistor R1, and the resistor R1 is connected between the base of the transistor 10 and the output terminal B of the resistor arrangement block 5 as an adjustment resistor. In this state, the signal transmitted from the output terminal A of the transmission side signal source 11 passes through the damping resistor Rt and the resistor R1, and is connected to the transmission line 12 connected to the output terminal B of the resistor arrangement block 5.
Sent to.
【００１４】次いで、ステップＳ２に進んで、ＣＰＵ２
によって、抵抗配置ブロック５の出力端子Ｂの電圧Ｖｂ
が検出され、ステップＳ３に進んで、ＣＰＵ２によって
送信側信号源１１の出力端子Ａの電圧Ｖａが検出され、
Ｖｂ＝Ｖａ／２が満足されるか否かの判定が行われる。
この場合、Ｖｂ＝Ｖａ／２が満足されると判定される
と、送信側信号源１１の出力インピーダンス、ダンピン
グ抵抗Ｒｔ及び抵抗Ｒ１の和が、伝送線路１２の特性イ
ンピーダンスＺｏに等しいことになるので、調整抵抗接
続制御系ユニット１による調整抵抗の接続処理は終了す
る。この状態では、送信側信号源１１の出力端子Ａの電
圧と抵抗配置ブロック５の出力端子Ｂの電圧Ｖｂとを実
際に測定して、Ｖｂ＝Ｖａ／２の条件が確認されている
ので、送信側信号源１１の出力インピーダンス、ダンピ
ング抵抗Ｒｔ及び調整抵抗Ｒ１の和が、伝送線路１２の
特性インピーダンスＺｏにマッチングしており、伝送線
路１２上の各位置での信号の電圧には、伝送線路１２の
端部からの反射波が重畳されて、伝送線路１２上の電圧
値は正規のレベルを維持し、信号波形には乱れが発生せ
ず反射ノイズの発生が防止される。Next, the process proceeds to step S2, where the CPU 2
The voltage Vb of the output terminal B of the resistor arrangement block 5
Is detected, the process proceeds to step S3, and the CPU 2 detects the voltage Va of the output terminal A of the transmission-side signal source 11,
It is determined whether Vb = Va / 2 is satisfied.
In this case, when it is determined that Vb = Va / 2 is satisfied, the sum of the output impedance of the transmission-side signal source 11, the damping resistor Rt, and the resistor R1 is equal to the characteristic impedance Zo of the transmission line 12. The connection process of the adjustment resistor by the adjustment resistor connection control system unit 1 ends. In this state, since the voltage of the output terminal A of the transmission side signal source 11 and the voltage Vb of the output terminal B of the resistor arrangement block 5 are actually measured and the condition of Vb = Va / 2 has been confirmed, the transmission is performed. The sum of the output impedance of the side signal source 11, the damping resistance Rt, and the adjustment resistance R1 matches the characteristic impedance Zo of the transmission line 12, and the voltage of the signal at each position on the transmission line 12 includes the transmission line 12 The reflected wave from the end is superimposed, the voltage value on the transmission line 12 is maintained at a normal level, and the signal waveform is not disturbed and the reflection noise is prevented from being generated.
【００１５】一方、ステップＳ３で、Ｖｂ＝Ｖａ／２が
満足されないと判定されると、ステップＳ４に進んで、
ＣＰＵ２によるスイッチ素子７ａ〜７ｎの切換処理がｎ
＋１回目であるか否かの判定が行われ、この場合には切
換処理がｎ＋１回目でないと判定されるので、ステップ
Ｓ５に進んで、ＣＰＵ２の指令によって、ポートＰ２に
制御信号が出力され、スイッチ素子７ｂがＯＮ状態に設
定される。そして、ステップＳ６において、スイッチ素
子７ｂと抵抗Ｒ２間が接続され、スイッチ素子７ｂと抵
抗配置ブロック５の出力端子Ｂとの間に調整抵抗として
抵抗Ｒ２が接続された状態となる。この状態では、送信
側信号源１１の出力端子Ａから発信される信号は、ダン
ピング抵抗Ｒｔと抵抗Ｒ２を通過して、抵抗配置ブロッ
ク５の出力端子Ｂに接続される伝送線路１２に送信され
る。On the other hand, if it is determined in step S3 that Vb = Va / 2 is not satisfied, the process proceeds to step S4,
The switching process of the switch elements 7a to 7n by the CPU 2 is n
It is determined whether or not the switching process is the +1 time. In this case, since it is determined that the switching process is not the (n + 1) th process, the process proceeds to step S5, and a control signal is output to the port P2 by a command from the CPU 2, The element 7b is set to the ON state. Then, in step S6, the connection between the switch element 7b and the resistor R2 is established, and the resistor R2 is connected between the switch element 7b and the output terminal B of the resistor arrangement block 5 as an adjustment resistor. In this state, a signal transmitted from the output terminal A of the transmission-side signal source 11 is transmitted to the transmission line 12 connected to the output terminal B of the resistor arrangement block 5 through the damping resistor Rt and the resistor R2. .
【００１６】ステップＳ６からは、ステップＳ２次いで
ステップＳ３に進んで、すでに説明したようにして、Ｖ
ｂ＝Ｖａ／２が満足されるか否かの判定が行われ、Ｖｂ
＝Ｖａ／２が満足されると判定されると、送信側信号源
１１の出力インピーダンス、ダンピング抵抗Ｒｔ及び抵
抗Ｒ２の和が、伝送線路１２の特性インピーダンスＺｏ
に等しいことになるので、調整抵抗接続制御系ユニット
１による調整抵抗の接続処理は終了する。一方、Ｖｂ＝
Ｖａ／２が満足されないと判定されると、ステップＳ４
に進み、ＣＰＵ２によるスイッチ素子７ａ〜７ｎの切換
処理がｎ＋１回目であると判定されるまで、ステップＳ
５、ステップＳ６、ステップＳ２、ステップ３の処理が
繰り返され、調整抵抗接続制御系ユニット１による調整
抵抗接続の切り換え動作が継続される。From step S6, the process proceeds to step S2 and then to step S3, where V
It is determined whether or not b = Va / 2 is satisfied.
= Va / 2 is satisfied, the output impedance of the transmission-side signal source 11, the sum of the damping resistance Rt and the resistance R2 becomes the characteristic impedance Zo of the transmission line 12.
Therefore, the connection process of the adjustment resistor by the adjustment resistor connection control system unit 1 ends. On the other hand, Vb =
If it is determined that Va / 2 is not satisfied, step S4
Until the CPU 2 determines that the switching process of the switch elements 7a to 7n is the (n + 1) -th time.
5, the processing of step S6, step S2, and step 3 is repeated, and the switching operation of the adjustment resistor connection by the adjustment resistor connection control system unit 1 is continued.
【００１７】このような処理により、抵抗値がＲ１〜Ｒ
ｎの調整抵抗の何れの接続によっても、Ｖｂ＝Ｖａ／２
が満足されないと判定されると、ステップＳ７に進ん
で、ＣＰＵ２によって、調整抵抗として接続した場合
に、Ｖｂ／Ｖａが１／２に最も近い抵抗値ＲｇがＲ１〜
Ｒｎから選択され、ポートＰｇに制御信号が出力され、
選択された抵抗Ｒｇが調整抵抗として、スイッチ素子７
ｇと抵抗配置ブロック５の出力端子Ｂ間に接続される。
この状態では、送信側信号源１１の出力タンピーダン
ス、ダンピング抵抗Ｒｔ及び抵抗Ｒｇの和が、伝送線路
１２の特性インピーダンスＺｏに最も近い状態が設定さ
れ、信号伝播時の反射ノイズを大幅に抑制することが可
能になる。By such processing, the resistance values are R1 to R
Vb = Va / 2 by any connection of the n adjustment resistors
Is determined not to be satisfied, the process proceeds to step S7, and when the CPU 2 is connected as an adjustment resistor, the resistance value Rg whose Vb / Va is closest to 1/2 is R1 to R1.
Rn, a control signal is output to the port Pg,
The selected resistor Rg serves as an adjustment resistor,
g and the output terminal B of the resistor arrangement block 5.
In this state, the state is set in which the output tampedance of the transmission-side signal source 11, the sum of the damping resistance Rt and the resistance Rg is closest to the characteristic impedance Zo of the transmission line 12, and the reflection noise during signal propagation is greatly suppressed. It becomes possible.
【００１８】以上に説明したように、本実施の形態によ
ると、ＣＰＵ２によって、抵抗選択コントローラ３のス
イッチ素子７ａ〜７ｎが順次ＯＮ状態にされ、このＯＮ
制御に対応して抵抗配列ブロック５の抵抗Ｒ１〜Ｒｎが
順次調整抵抗に選択されて、送信側信号源１１の出力端
子Ａと、抵抗配置ブロック５の出力端子Ｂ間に、ダンピ
ング抵抗Ｒｔと選択された抵抗値の調整抵抗が直列に接
続される。そして、各調整抵抗の接続ごとに、ＣＰＵ２
によって、抵抗配置ブロック５の出力端子Ｂの電圧Ｖｂ
が、送信側信号源１１の出力端子Ａの電圧Ｖａの１／２
になるか否かが判定され、Ｖｂ＝Ｖａ／２が満足される
抵抗値が調整抵抗として選択され、何れの抵抗値でもＶ
ｂ＝Ｖａ／２が満足されない場合には、Ｖｂ／Ｖａが１
／２に最も近い抵抗値が調整抵抗として選択される。As described above, according to the present embodiment, the switching elements 7a to 7n of the resistance selection controller 3 are sequentially turned on by the CPU 2, and this ON state is set.
In response to the control, the resistors R1 to Rn of the resistor array block 5 are sequentially selected as adjustment resistors, and a damping resistor Rt is selected between the output terminal A of the transmission-side signal source 11 and the output terminal B of the resistor placement block 5. The adjustment resistors having the adjusted resistance values are connected in series. Then, for each connection of each adjustment resistor, the CPU 2
The voltage Vb of the output terminal B of the resistor arrangement block 5
Is の of the voltage Va of the output terminal A of the transmission-side signal source 11.
Is determined, and a resistance value satisfying Vb = Va / 2 is selected as an adjustment resistance.
If b = Va / 2 is not satisfied, Vb / Va is 1
The resistance value closest to / 2 is selected as the adjustment resistance.
【００１９】このようにして、Ｖｂ＝Ｖａ／２を満足す
る抵抗値の調整抵抗が選択された場合には、抵抗配列ブ
ロック５の出力端子Ｂに接続される伝送線路１２の特性
インピーダンスＺｏと、送信側信号源１１の出力インピ
ーダンス、ダンピング抵抗Ｒｔ及び調整抵抗の和とがイ
ンピーダンス適合することになり、伝送線路１２におい
て信号の反射ノイズを防止することが可能になる。ま
た、Ｖｂ／Ｖａ＝１／２に最も近い抵抗値が、調整抵抗
として選択された場合には、抵抗配列ブロック５の出力
端子Ｂに接続される伝送線路１２の特性インピーダンス
Ｚｏと、送信側信号源１１の出力インピーダンス、ダン
ピング抵抗Ｒｔ及び調整抵抗の和とが、近似的にインピ
ーダンス適合することになり、伝送線路１２において信
号の反射ノイズを大幅に低減することが可能になる。As described above, when an adjustment resistor having a resistance value satisfying Vb = Va / 2 is selected, the characteristic impedance Zo of the transmission line 12 connected to the output terminal B of the resistor array block 5 and The output impedance of the transmission-side signal source 11 and the sum of the damping resistance Rt and the adjustment resistance are impedance-matched, so that signal reflection noise on the transmission line 12 can be prevented. When the resistance value closest to Vb / Va = 1/2 is selected as the adjustment resistance, the characteristic impedance Zo of the transmission line 12 connected to the output terminal B of the resistance array block 5 and the transmission-side signal The output impedance of the source 11 and the sum of the damping resistance Rt and the adjustment resistance approximately match the impedance, so that the reflection noise of the signal in the transmission line 12 can be greatly reduced.
【００２０】なお、以上の実施の形態では、ＣＰＵ２が
ｎ個の抵抗Ｒ１〜Ｒｎを順次単独に選択して、調整抵抗
を選択する場合を説明したが、本発明はこの実施の形態
に限定されるものではなく、例えば、ＣＰＵ２が抵抗Ｒ
１〜Ｒｎを順次選択しても、Ｖｂ＝Ｖａ／２を満足する
抵抗値が得られない場合には、Ｒ１〜Ｒｎの複数個を使
用して並列接続回路を形成し、該並列接続回路の抵抗値
によって、Ｖｂ＝Ｖａ／２により近い調整抵抗を得るよ
うに構成することも可能である。また、実施の形態で
は、ダンピング抵抗Ｒｔが予め接続されている場合を説
明したが、本発明は、この実施の形態に限定されるもの
ではなく、ダイピング抵抗Ｒｔが接続されていない場合
に適用することも可能である。In the above embodiment, the case has been described where the CPU 2 selects the n resistors R1 to Rn independently and selects the adjustment resistor, but the present invention is limited to this embodiment. For example, if the CPU 2
If a resistance value satisfying Vb = Va / 2 cannot be obtained even when 1 to Rn are sequentially selected, a parallel connection circuit is formed by using a plurality of R1 to Rn. Depending on the resistance value, it is also possible to obtain an adjustment resistance closer to Vb = Va / 2. In the embodiment, the case where the damping resistor Rt is connected in advance has been described. However, the present invention is not limited to this embodiment, and is applied to a case where the diping resistor Rt is not connected. It is also possible.
【００２１】[0021]
【発明の効果】本発明では、選択スイッチで伝送線路の
特性インピーダンスに適合する抵抗値を切り換え選択
し、切換選択された抵抗値の調整抵抗を、伝送線路に直
列に挿入接続する調整抵抗接続ユニットに対する制御
が、制御手段によって行われ、この制御では、調整抵抗
接続ユニットの出力側端子と伝送線路との接続点の電圧
レベルが、送信側信号源の出力端子の電圧レベルの１／
２に一致するか、または、近似的に一致するように、選
択スイッチの切換制御が行われ、切換選択された抵抗値
の調整抵抗が、送信側信号源からの高周波電気信号が伝
播される伝送線路に直列に挿入接続される。このため
に、本発明によると、実際の電圧検出に基づいて、製造
誤差に起因してばらつきを有する伝送線路の特性インピ
ーダンスに、適確に対応するインピーダンス適合が行わ
れて、波形ひずみのない信号の伝送が行われ、反射ノイ
ズの発生を完全に防止し、或いは大幅に低減することが
可能になる。According to the present invention, an adjustment resistor connection unit for switching and selecting a resistance value suitable for the characteristic impedance of a transmission line by a selection switch, and inserting and connecting an adjustment resistor of the selected resistance value in series to the transmission line. Is controlled by the control means. In this control, the voltage level at the connection point between the output terminal of the adjustment resistor connection unit and the transmission line is 1 / the voltage level of the output terminal of the transmission signal source.
The switching of the selection switch is performed so as to match or approximately match with 2 and the adjustment resistance of the selected and switched resistance value is transmitted by the transmission of the high-frequency electric signal from the transmission-side signal source. It is inserted and connected in series to the line. For this reason, according to the present invention, based on the actual voltage detection, the impedance matching corresponding to the characteristic impedance of the transmission line having the variation due to the manufacturing error is accurately performed, and the signal without waveform distortion is obtained. Is transmitted, and the occurrence of reflected noise can be completely prevented or greatly reduced.
【図１】本発明の一実施の形態が伝送線路に適用された
場合の全体構成を示す説明図である。FIG. 1 is an explanatory diagram showing an overall configuration when an embodiment of the present invention is applied to a transmission line.
【図２】同実施の形態の概略構成を示すブロック図であ
る。FIG. 2 is a block diagram showing a schematic configuration of the embodiment.
【図３】同実施の形態の構成を示す回路説明図である。FIG. 3 is a circuit diagram illustrating the configuration of the embodiment.
【図４】図３のスイッチ素子の構成を示す回路図であ
る。FIG. 4 is a circuit diagram showing a configuration of a switch element of FIG. 3;
【図５】同実施の形態の動作を示すフローチャートであ
る。FIG. 5 is a flowchart showing an operation of the embodiment.
【図６】従来のダンピング抵抗によるインピーダンス適
合の説明図である。FIG. 6 is an explanatory diagram of impedance matching by a conventional damping resistor.
【図７】従来のインピーダンス適合動作の説明図であ
る。FIG. 7 is an explanatory diagram of a conventional impedance matching operation.
１‥‥調整抵抗接続制御系ユニット、２‥‥ＣＰＵ、３
‥‥抵抗配置ブロック、６‥‥ＲＯＭ、７ａ〜７ｎ‥‥
スイッチ素子、１０‥‥トランジスタ、１１‥‥送信端
信号源、１２‥‥伝送線路。1 ‥‥ adjustment resistor connection control system unit 2 ‥‥ CPU, 3
{Resistor arrangement block, 6} ROM, 7a-7n}
Switch element, 10 ‥‥ transistor, 11 ‥‥ transmission end signal source, 12 ‥‥ transmission line.
Claims (1)
播される伝送線路に対して、前記伝送線路の特性インピ
ーダンスに適合する抵抗値の調整抵抗の挿入接続を行う
インピーダンス適合システムであり、 前記抵抗値の選択の切換を行う選択スイッチを備え、該
選択スイッチの切換により選択される抵抗値の調整抵抗
を、前記伝送線路に直列に挿入接続する調整抵抗接続ユ
ニットと、 該調整抵抗接続ユニットの出力側端子と前記伝送線路と
の接続点の電圧レベルを、前記送信側信号源の出力端子
の電圧レベルの１／２に一致させ、または近似的に一致
させるように、前記選択スイッチの切換制御を行う制御
手段とを有することを特徴とするインピーダンス適合シ
ステム。1. An impedance matching system for inserting and connecting an adjusting resistor having a resistance value matching a characteristic impedance of a transmission line to a transmission line through which a high-frequency electric signal from a transmission-side signal source is propagated, An adjustment resistor connection unit for inserting and connecting an adjustment resistor having a resistance value selected by switching the selection switch to the transmission line in series; and Switching control of the selection switch so that a voltage level at a connection point between an output terminal and the transmission line is equal to or approximately equal to 1/2 of a voltage level of an output terminal of the transmission signal source. And a control means for performing the following.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP36133999A JP2001177580A (en) | 1999-12-20 | 1999-12-20 | Impedance adapting system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP36133999A JP2001177580A (en) | 1999-12-20 | 1999-12-20 | Impedance adapting system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2001177580A true JP2001177580A (en) | 2001-06-29 |
Family
ID=18473178
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP36133999A Pending JP2001177580A (en) | 1999-12-20 | 1999-12-20 | Impedance adapting system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2001177580A (en) |
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