JP2001168297A - Semiconductor element and semiconductor memory device using it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor element in which the number of elements is small, in which a memory comprising an information storage function can be constituted by itself in a small area, and which does not require a cooling operation down to a cryogenic temperature, and to provide a semiconductor memory device. SOLUTION: Until whether one electron is captured by a trap is discriminated precisely as the current value of an FET, a capacitance across gate channels is set to be small. The magnitude of a threshold value by whether one electron is captured by the trap is sensed, and information is stored at room temperature. As a result, it is possible to realize the semiconductor memory device whose integration is high, whose power consumption is low and which is nonvolatile. It is possible to obtain a remarkable effect that the power consumption in a system is low, and that the system can be miniaturized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device suitable for high integration and a semiconductor memory device using the same.

[0002]

2. Description of the Related Art Conventionally, polycrystalline silicon (polysilicon)
Is a static RAM (SRA
M). Related prior art is described in T. Yamanaka, et al, IEEE International El
ectron Devices Meeting, p477-480, 1990. By utilizing a polycrystalline silicon transistor, the degree of integration of an integrated circuit can be improved. This is a normal bulk MOSFET formed on the surface of a semiconductor substrate
This is because a polysilicon transistor can be formed by lamination on the upper portion of the substrate through an insulating film. An SRAM requires four bulk MOSFETs and two polycrystalline silicon transistors to form a memory cell for one bit. However, since a polycrystalline silicon transistor can be formed by being stacked on top of a bulk MOSFET, it is substantially required. Has a bulk MOSFE
One memory cell of the SRAM can be configured with T4 areas.

[0003] Other prior art related to the present invention include:
K. Nakazato, et al, ElectronicsLetters, Vol. 29, N
o. A single electronic memory as described in 4, pp384-385, 1993. In this prior art, it has been reported that a memory can be configured by controlling each electron. However, the operating temperature is as low as 30 mK.

[0004] Another prior art related to the present invention includes a random telegraph noise (RTN, Rand) of a MOSFET.
om Telegraph Noise). This is discussed in F. Fang, et al, 1990 Symposium on VLSI Tech
nology, pp37-38, 1990. RTN is
When the drain current of a MOSFET is measured over a fixed time under a constant voltage condition, a state transition occurs randomly between two states of a high current state and a low current state. It is known that this current change may reach several percent of the total current value. This RTN is caused by the fact that one electron is captured by a level existing at the interface between Si and SiO ₂ or is emitted from the level, so that the current value changes. As described above, the RTN is only used for basic research as a component of the current noise of the MOSFET, and is not applied to the RTN.

[0005]

While fine processing technology for semiconductor integrated circuits has advanced at a high level today, it is technically difficult to continue further miniaturization in the future. Even if it is technically possible, the problem that the manufacturing cost is greatly increased by using advanced technology has become apparent. For this reason, it has been strongly demanded that the degree of integration be improved by a fundamentally new method, instead of simply miniaturizing the semiconductor elements constituting the integrated circuit circuit as in the prior art. On the other hand, the function of the above-described conventional polycrystalline silicon transistor is basically a variable resistance element that can control the resistance between the source and the drain by the gate voltage. Therefore, in order to configure the memory cell of the SRAM, as many as six MOSFETs are required in total, including MOSFETs formed on a normal Si substrate. In contrast, D
A memory cell of a RAM is known as a RAM system having the highest degree of integration because one MOSFET and one capacitor can store one-bit information. However, since the DRAM is a method of reading the amount of electric charge to a data line whose capacity cannot be ignored, the capacitance of the memory cell is required to be about several tens of fF, and it is difficult to realize the capacitance in a small area with continued miniaturization. Have been. By using a MOSFET having a floating gate and a control gate, the flash EE
A non-volatile storage device such as a PROM has been realized.
Further, as a similar nonvolatile memory element, MNOS (M
etalNitride Oxide Semiconductor) devices are known. This MNOS stores electric charges at the interface between the SiO ₂ film and the Si ₃ N ₄ film instead of the floating gate of the flash EEPROM. Thus, M with floating gate
By using OSFET or MNOS element,
Although there is an advantage that one-bit information can be stored for a long time with only one transistor, since a current flows through an insulating film, a long time is required for rewriting, and the number of rewriting times is one.
There is a limit of about one million times. For this reason, there is a problem that the use of the nonvolatile memory device is limited.

On the other hand, since the single-electron memory discussed in Nakazato et al. Operates only at an extremely low temperature of 30 mK, there is a major problem that the memory must be cooled to an extremely low temperature. Further, the cell of this single-electron memory is composed of one capacitor and two active elements, and has a problem that the number of elements is larger than that of a conventional DRAM. In order to form a memory with higher integration than before without depending on miniaturization of the element as described above, DRA
An element that does not require a capacitance element such as M and has a memory function in the element itself is desired. However, to date, no such memory element is known.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a memory having a small number of elements and a small area, the element itself having an information storage function, and not requiring cooling to an extremely low temperature, and a semiconductor using the same. It is to provide a storage device.

[0008]

In order to achieve the above object, a semiconductor device according to the basic technical concept of the present invention is characterized in that the presence / absence of trapping of one carrier (electron) in one trap is determined by using an FET.
The capacitance between the gate and the channel is set small until it can be clearly detected as the magnitude of the current value. That is, the value of the threshold value of the FET depending on the presence or absence of carrier trapping is determined by the digital value "1".
And "0", information can be stored even at room temperature.

More specifically, a semiconductor device according to a representative embodiment of the present invention has a source region (1) and a drain region (2), and the source region (1) is a channel region (3).
And the channel region (3) is connected to the gate electrode (4) via a gate insulating film (5), and the source region (1) and the drain region (2 A level (7) for capturing at least one carrier is formed near the current path (6) in the channel region (3) between the gate electrode (4) and the channel region. (3) is small enough to satisfy the inequality 1 / Cgc> kT / q ² (where k is the Boltzmann constant, T is the operating temperature, and q is the amount of electron charge). It is characterized by being set (see FIG. 1).

According to another embodiment of the present invention, the semiconductor device has a source region (19) and a drain region (20).
(19) is the drain region (20) through the channel region (21)
And the channel region (21) is a gate insulating film (23)
Connected to the gate electrode (22) through the source region (19)
And the channel region (21) between the drain region (20) and
Has at least one region (24) for confining carriers, and the confinement region (24) and the channel region (2)
1), and the effective capacitance Cgc between the gate electrode (22) and the channel region (21) is inequality 1 / Cgc> kT / q ² (here Where k is the Boltzmann constant, T is the operating temperature, and q is the amount of electron charge) (see FIG. 10).

In a semiconductor device according to still another embodiment of the present invention, the capacitance value C between the channel region (21) and the confinement region (24) is changed between the gate electrode (22) and the confinement region (24). And the capacitance value Ctt for at least one other of the carrier confinement regions (24) is inequality q ² / 2Ctt> kT (where k is Boltzmann's constant, T is the operating temperature, and q is the electron temperature. (See FIG. 10).

In order to further increase the number of times that the memory can be rewritten, it is required that the deterioration of the barrier (insulating film) between the channel region and the carrier confinement region is small. An embodiment of the present invention suitable for solving the problem of barrier deterioration includes a source region and a drain region, and the source region is connected to the drain region through a channel region (46), and the channel region (46 ) Is connected to the gate electrode (51) via the gate insulating film (53), near the channel region, surrounded by a potential barrier, has at least one region (47) for confining carriers, A memory is performed by holding carriers in the carrier confinement region (47), and a thin film structure having a thickness of 9 nm or less made of a semiconductor material between the channel region and the carrier confinement region.
(48) (see FIG. 17).

The characteristics of the polycrystalline silicon device (FIG. 1) according to a typical embodiment of the present invention are as follows. The voltage between the drain (2) and the source (1) is fixed and the voltage between the gate electrode (4) and the source is constant. When repeatedly increasing or decreasing the potential difference between (1) and
The conductance between (4) and the drain (2) shows hysteresis even at room temperature (see FIG. 2). That is, as shown in FIG.
When the voltage is swept up and down between the voltage Vg0 (0 volt) and the second voltage Vg1 (50 volt), the drain current shows hysteresis even at room temperature. This has never been known before, and has been experimentally discovered by the inventors. The reason why this hysteresis occurs will be described below.

FIG. 4A shows a band diagram of the channel region (3) when the potential difference Vgs between the gate and the source in the semiconductor device of FIG. 1 is 0 volt. A drain current flows in a direction perpendicular to the plane of FIG. 4A. In the following description,
Consider a case where the voltage between the drain and the source is sufficiently smaller than the gate voltage. However, even when the voltage between the drain and the source is large, the following results hold as they are. First, as shown in FIG.
(3) forms a well-like potential with low energy between the gate oxide film (5) and the surrounding SiO ₂ protective film (10). At this time, P type or N type with low impurity concentration or i
The energy level (11) of the conduction band of the (intrinsic semiconductor) type channel region (3) is the energy level of the conduction band in the high impurity concentration N-type source (1) or in the degenerated high impurity concentration N-type source ( There are no electrons in the channel (3) because it is sufficiently higher than the Fermi level (12) in (1). Therefore, no drain current flows. In addition, a trap level (7) exists near the channel (3), and can capture electrons as carriers. The cause of this trap level is
Levels due to grains (crystal grains in the channel region (3) of polycrystalline silicon) surrounded by high barriers, levels in grains, and grain boundaries (high-energy interface areas between grains) At Si, SiO ₂ interface
(Interface between the channel region (3) and the gate oxide film (5)),
A level or the like in the gate oxide film (5) can be considered, but any of these levels may be used in the following description. It is not clear at this time which of these actually captures electrons in the above experiment. Among the trap levels having various levels, the energy of the trap level (7) involved in the hysteresis characteristic of the present invention is sufficiently higher than the Fermi level (12) of the source (1), and this trap level ( 7)
There are no electrons. Potential difference between gate (4) and source (1)
When Vgs is increased from 0 volts to a low threshold voltage Vl, the potential of the channel region (3) rises. Therefore, the energy level of the channel (3) having an initial value of Vgs = 0 volt (see FIG.
(See FIG. 4 (A)), under the condition of 0 volts <Vgs <Vl, as shown in FIG.
The potential of (3) drops. When Vgs reaches the low threshold voltage Vl, the Fermi level of the source region (1) changes to the channel region.
Since the energy level approaches the conduction band energy level of (3) (a difference of about kT when the Boltzmann constant is k and the operating temperature is T), electrons are introduced from the source into the channel region (3). As a result, a current flows between the drain D and the source. Furthermore, when the gate voltage is increased, the number of electrons in the channel region (3) further increases, but when Vgs reaches the trap capture voltage Vg1, the energy of the trap level (7) is reduced to the source region (1).
, At least one electron is trapped in the trap level (7) due to the distribution of electrons due to the thermal energy of the electrons introduced from the source region (1). At this time, since the level of the trap (7) is sufficiently lower than the potentials of the gate oxide film (5) and the surrounding SiO ₂ protective film (10), the electrons trapped by the trap level (7) lose their heat. The gate oxide film (5) and the surrounding SiO ₂ protective film by energy
It does not move to (10). Also, for example, Si-Si
A channel region near the trap level (7) at the O ₂ interface
Since the high energy grain boundary of the polycrystalline silicon in (3) exists, electrons trapped in the trap level (7) cannot move from the trap level (7) (see FIG. 4).
(C)). Since the other electrons can move, the drain current continues to flow.

As described above, one electron is present at the trap level (7).
The threshold voltage of the polycrystalline silicon semiconductor device shown in FIG. 1 changes from a low threshold voltage Vl to a high threshold voltage Vh when the individual elements are captured. The reason will be described below. That is, when Vgs is lowered in the range of Vh <Vgs <Vg1 from the state of FIG. 4C, the electrons in the channel (3) decrease, but generally, high energy around the trap level (7). The electron trapped at the trap level (7) remains as it is (FIG. 5A). When the gate voltage further decreases and the voltage of the gate (4) becomes Vgs = Vh, the Fermi level (12) of the source (1) becomes k higher than the energy level of the conduction band of the channel (3).
Since they are separated by about T, the electrons in the channel almost disappear (Fig. 5
(See (B)). Therefore, no drain current flows. However, the threshold at which the drain current stops flowing like this
Vh is higher than the low threshold voltage Vl by a voltage corresponding to the amount of charge trapped in the trap level (7). Further Vgs
When, for example, Vgs = 0 volts is reached, the potential of the high energy region around the trap level (7) decreases with the decrease of the gate voltage, and as a result, the region of the reduced energy The electrons trapped in the trap level (7) are emitted by tunneling due to the electric field effect (see FIG. 5C). After that, when Vgs is raised again and swept up and down, the above operation is repeated, so that hysteresis accompanying capture / emission of electrons is observed.

The inventors have further discovered that this hysteresis appears only when the capacitance between the gate and the channel is small. The device exhibiting the above-mentioned hysteresis was a device having a gate length and a gate width of 0.1 μm, but the device having a gate length and a gate width of 1 μm did not exhibit the hysteresis. That is, in order for the hysteresis to appear, it is essential that the capacitance between the gate and the channel is small. This can be explained as follows. The following relationship exists between the charge amount Qs accumulated in the trap level and the threshold change amount ΔVt (= Vh−Vl).

ΔVt = Qs / Cgc (1) where Cgc is the capacitance between the gate and the effective channel. In order to use the hysteresis as a memory, it is necessary that a high threshold state and a low threshold state can be clearly distinguished as a change in drain current value. That is, it is necessary that the difference in the threshold value can be clearly sensed as the difference in the drain current value. The condition for this can be determined as follows. Generally, the drain current Id of a MOS transistor having a threshold value Vt
Is expressed by the following equation near the threshold value.

Id = ADexp [q (Vgs−Vt) / (kT)] (2) where A is a proportionality coefficient, q is an electron charge, Vgs is a gate-source voltage of a MOS transistor, and Vt is a threshold. Voltage,
k is Boltzmann's constant and T is the operating temperature. Therefore, when the threshold Vt = Vh, the drain current is Idh = ADexp [q (Vgs-Vh) / (kT)] (3), and when the threshold Vt = Vl, the drain current is Idl = ADexp [q (Vgs-Vl) / (kT)] (4). From this, the ratio of the drain current values in the two states of Vt = Vh and Vt = Vl is expressed by the following equation.

Idl / Idh = exp [q (Vh−Vl) / (kT)] (5) Therefore, in order to sense the drain current value and distinguish between the above two states, the current ratio of equation (5) must be at least But the base of natural logarithm e (=
2.7) It is necessary to be at least, and practically, it is desirable to be at least 10. If the condition of being equal to or larger than the base e of the natural logarithm is used, ΔVt (= Vh−Vl)> kT / q (6) is obtained. Therefore, from (1), it is necessary that Qs / Cgc> kT / q (7). In order to satisfy this current sensing condition by capturing one electron, it is necessary that q / Cgc> kT / q (8). According to equation (8), Cgc needs to be 6aF or less (here, a (at) means 10 to the minus 18th power) for room temperature operation. The gate length is 1
For a micron-sized device, Cgc is about 1fF (where f (femto) means 10 to the 15th power),
It deviates greatly from this condition. In the prototype device of the present invention, Cgc is as extremely small as 0.01 aF, which indicates that a threshold shift has occurred such that sensing of only one electron at room temperature is possible.

The inventors set and hold Vgs between 0 volts and Vg1, so that the immediately preceding threshold value is 1
It was found that it was kept stable for more than an hour. FIG. 3 shows the results of this experiment. FIG. 3 shows a change in drain current measured at a constant gate voltage under the conditions of FIG. In the low threshold condition, the high current level is maintained,
At the high threshold, the low current level was maintained. Therefore, information can be held (stored) using the shift of the threshold value. Further, information can be read by sensing the drain current at this time. That is, a state where the current is smaller than the reference value (13) can be read as "1", and a state where the current is larger than the reference value (13) can be read as "0" (see FIG. 3). Writing of information can be performed by controlling the gate voltage. First, it is assumed that the gate voltage was Vg0 in the initial state. Gate voltage Vg1
And set the transistor threshold voltage to Vh. As a result, "1" of digital information can be written. Thereafter, the gate voltage is swept in the negative direction to 0 volt to change the threshold voltage to Vl. Thus, "0" of digital information can be written.

As described above, writing, holding, and reading of information can be performed by one element, and the number of elements is smaller than that of the related art.
The memory can be configured by (area). In the present invention, storage is performed by capturing a small number of electrons in a storage node.
Unlike the floating gate MOSFET, the number of rewrites is not limited (or relatively limited) by the deterioration of the insulating film. In the embodiment of FIG. 1 described above, the relative positional relationship (distance) between the carrier trap level as the carrier confinement region and the effective channel region as the current path is difficult to determine, and the variation between elements is large. There is. In contrast, as shown in the embodiment of FIG. 10, by independently providing the carrier confinement region (24) surrounded by the potential barrier near the channel (21), this variation can be reduced. From the viewpoint of element performance stability, it is preferable that the variation between elements of ΔVt, which is the voltage difference between the high threshold voltage Vh and the low threshold voltage Vl, is small. Equation (1) is an equation that holds when Cgt is sufficiently smaller than C, but is expressed by the following equation when other cases are included.

ΔVt = q / (1 + Cgt / C) Cgc (9) where Cgc is the capacitance between the gate (22) and the channel (21), and Cgt is the gate (22) and the carrier confinement region (2
C) is the capacitance between the carrier confinement region (24) and the channel (21).

On the other hand, in the embodiment of FIG. 1, the carrier confinement region has a carrier trap level,
In equation (9), it was found that the capacitance C between the carrier confinement region and the channel was most likely to vary. It is necessary that Cgt is sufficiently smaller than C so that ΔVt does not change much even if C changes. In the embodiment of FIG. 10, the capacitance between the gate (22) and the carrier confinement region (24) is increased by the large thickness of the gate insulating film (23) between the gate electrode (22) and the carrier confinement region (24). Cgt is set to a small value,
On the other hand, due to the small thickness of the insulating film (25) between the carrier confinement region (24) and the channel (21), the carrier confinement region (24)
The capacitance C between the channel and the channel (21) can be set to a large value. On the other hand, in retaining the information of the capacitance value Ctt in the carrier confinement region (24), it is necessary to ensure stability against thermal fluctuation. Temperature T (T is absolute temperature)
In general, there is an energy fluctuation of about kT (k is Boltzmann coefficient). For stable information retention, energy change q ² by capturing one electron
/ 2Ctt must be larger than this fluctuation, that is, the inequality q ² / 2Ctt> kT (18) must be satisfied. According to equation (18), Ctt needs to be 3 aF or less for operation at room temperature.

In another embodiment of the present invention (FIG. 17),
A semiconductor thin film structure (48) is provided in the insulating film (49, 50) between the storage region (47) and the channel (46) to reduce the deterioration of the insulating film (49, 50). That is, in the semiconductor element according to the present embodiment, the potential barrier is provided in the insulating film (49, 50) by the quantum confinement effect of the thin film structure (48), so that the thin film structure (48) is effectively the same as the insulating film. It plays a role and makes it possible to reduce the actual insulating film thickness.
As shown in FIG. 17, in the semiconductor thin film (48) provided in the insulating films (49, 50), the energy level is shifted from the conduction band due to the effect of quantum confinement in the film thickness direction. Serves as a potential barrier between the storage area and the carrier supply area for writing and erasing. For this reason,
It is described in detail below. When the thickness of the semiconductor thin film (49) is L, the effective mass of carriers in the thin film is m, and the Planck constant is h,
The energy of the lowest energy state of the quantum wave of the carrier due to the effect of confinement in the film thickness direction is approximately given by the following equation.

[0025] For effective as a potential barrier when h ² / 8mL ² to (19) energy shift due to the quantum confinement effect was taken into account thermal energy fluctuation, the inequality h ² / 8mL ^2> kT
(20) must be satisfied. From equation (20), when Si is used for the semiconductor, the film thickness at which the barrier is effective at room temperature is 9 nm or less. Therefore, channel (4
Insulating film (49, 50) between 6) and carrier confinement region (47)
When carriers move in both directions through the semiconductor, there is a probability that the carriers exist in the semiconductor thin film (48) in a short time, but the probability that the carriers exist in the semiconductor thin film (48) for a long time is extremely low . As a result, when the carrier moves between the channel (46) and the carrier confinement region (47), the semiconductor thin film (48) operates as a temporary carrier passage region, so that the semiconductor thin film (48) consequently has the carrier confinement. Cannot be carried out, and will act as a potential barrier. In this structure, a similar barrier effect can be realized with a smaller insulating film thickness as compared with a case where this structure is not used. Therefore, the film fatigue of the insulating films (49, 50) is small. In order to further reduce the film fatigue, a multilayer semiconductor thin film (48) could be formed. This structure in which the semiconductor thin film is provided in the insulating film has an additional advantage that the height of the potential barrier between the carrier confined storage region and the carrier supply region for writing and erasing can be appropriately set. This is because the energy shift due to quantum confinement is determined by the size L of the confinement region, so that the barrier height can be adjusted by the film thickness L other than the material of the thin film. In the conventional structure, the barrier height is determined only by the material of the insulating film. Other objects and features of the present invention will become apparent from the following examples.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a memory device according to a specific embodiment of the present invention will be described. FIG. 1 is a structural diagram of a storage element according to the present embodiment. Source (1), and drain (2)
Is a region made of high impurity concentration n-type polycrystalline silicon. The channel section (3) is a non-doped polysilicon region. This source (1), drain (2), channel
(3) consists of thin, thin lines of polycrystalline silicon. In the example that the inventors actually prototyped, the channel width was
It is 0.1 micron and 10 nm thick. This source
(1) A polycrystalline silicon contact portion having a larger thickness is connected to the end of the drain (2), and is connected to a metal wiring on this polycrystalline silicon. For example, this polycrystalline silicon contact portion is 0.1 μm thick ten times as thick as the channel portion (3). This is because if a contact hole is to be made directly on the thin polycrystalline silicon, the polycrystalline silicon itself will not be etched. Gate
(4) is provided so as to cross the channel (3) via the gate insulating film (5). In this embodiment, the thickness of the gate (4) is 0.1 μm. In this embodiment, the area around the polysilicon film serving as the channel (3) is all S
Surrounded by iO ₂ (10). Since the dielectric constant of SiO ₂ is about 1 / of that of silicon, the capacitance between the channel (3) and the gate electrode (4) is reduced by surrounding it with SiO ₂ . This is one of the reasons that hysteresis can be realized at room temperature. In the present embodiment,
Polycrystalline silicon of the channel is thin 10nm on SiO ₂ a
After (amorphous) -Si was deposited, it was formed by crystallization by heat treatment at 750 ° C. During this heat treatment, a
In -Si, silicon crystal grains grow, but when the size of the crystal grains reaches the film thickness, crystal growth can no longer be performed in the direction perpendicular to the film. At the same time, the speed of crystal growth in the direction parallel to the film is reduced. For this reason, the size of the crystal grains in the lateral direction becomes substantially equal to the film thickness. As described above, this embodiment is characterized in that the crystal grains are extremely small. Such small crystal grains also contribute to reducing the capacitance between the gate and the channel. This will be described below. In the low current region near the threshold, the current actually flows through a small number of current paths (6) having the lowest resistance in the channel (3) (see FIG. 1). Actually, a current flows as electrons walk one after another through the crystal grains. In this embodiment, since the size of the crystal grains is small, the current path is also extremely narrow. For this reason, as shown in FIG. 1, the region where electrons actually exist is considerably smaller than the entire region of the channel. For this reason, the capacitance Cgc between the gate and the effective channel is small. In this prototype device, Cgc was set extremely small in order to observe the effect of the change in threshold value as large as possible. For this reason, the range of the voltage required for the operation is as large as several tens of volts. By setting Cgc to be larger, it is possible to set the operation range to a range of several volts used in a normal integrated circuit. Specifically, the gate oxide film
The thickness of (5) may be further reduced, and the gate length and gate width may be increased. This is technically easy to achieve. In this embodiment, the channel portion is formed of polycrystalline silicon. However, in a normal bulk MOSFET formed on the surface of a crystalline Si substrate, if the capacitance between the gate and the channel can be reduced to the extent that the above condition is satisfied. Hysteresis can be realized and used as a storage element. In the case of a bulk MOSFET, there is no effect of the crystal grains as described above, and since the lower side is covered with Si having a high dielectric constant, it is necessary to reduce the dimensions of the element as compared with the case of the polycrystalline silicon. . Therefore, the manufacturing is more difficult, but the bulk MOSFET has a higher carrier mobility, so that a large current value can be flown, which is advantageous for high-speed operation. Or MOSFET of SOI (Siliconon Insulator) structure
The above-mentioned hysteresis can also be realized by using.
SOI structure grows single crystal silicon on insulating film,
This is a technique for manufacturing a MOSFET therein. This SO
Since I can reduce the capacitance between the gate and the channel as compared with the bulk MOSFET, the hysteresis can be realized with a larger size than using the bulk MOSFET structure. In the above example, an n-channel type in which electrons are conducted has been described as an example, but the same operation can be performed using holes.
Further, a semiconductor other than silicon can be used for the channel region. In this embodiment, the case where the gate (4) is located below the channel (3) is shown, but the same operation can be performed even if the gate is fabricated above. It is also possible to provide gates on both the upper and lower sides of the channel, and the operation is the same as in the above case. Further, a gate can be provided beside the channel. It is also possible to provide gates on both sides of the channel.

Next, a memory integrated circuit using the present semiconductor device will be described with reference to FIG. FIG. 6 shows a configuration of a storage device using the polycrystalline silicon storage element of FIG. It is assumed that the characteristics of the semiconductor element are as shown in FIG. That is, when a voltage of Vw is applied between the gate and the source, the element is in the "1" state (high threshold Vh state). Conversely, when a voltage of -Vw is applied between the gate and the source, the element enters the "0" state (low threshold Vl state). Even if a voltage of -Vw / 2 to Vw / 2 is applied between the gate and the source or between the gate and the drain, the threshold voltage does not change. This characteristic is obtained by lowering the threshold voltage as a whole in the characteristic of FIG. 2, and can be realized by introducing a donor impurity into the channel portion of the prototype device. In FIG. 6, MP1-MP4 are semiconductor elements of the present invention having the structure of FIG. 1 and the characteristics of FIG. Each gate terminal is connected to a word line, the drain terminal is connected to a data line, and the source terminal is grounded. To write digital information, the word line driving circuit and the data line driving circuit shown in FIG. 6 are used as follows. To write "1" to MP1, word line 1 is set to Vw / 2 and data line 1 is set to -Vw / 2. The other word lines and data lines are set to 0V. As a result, the voltage Vw is applied between the gate and the drain of MP1, and MP1 is set to the "1" state (high threshold state). At this time, since only a voltage of Vw / 2 or less is applied to the elements other than MP1, the threshold voltage does not change. To write "0" to MP1, set word line 1 to -Vw /
2 and the data line 1 is set to Vw / 2. As a result, a voltage of -Vw is applied between the gate and the drain of MP1, and MP1 is in the "0" state (low threshold state). At this time, the threshold voltage does not change because only a voltage of -Vw / 2 or more is applied to the elements other than MP1. Reading of information is performed as follows (see FIG. 6). In the data line driving circuit, the data line is connected to a voltage source via a load element. On the other hand, the other end of the data line is connected to a sense amplifier.
Consider a case where information of MP1 is read. For this purpose, the selected word line 1 is set to 0 V, and the other unselected word lines 2 are set.
Is -Vw / 2. When MP1 is in the “1” state, MP1
Is turned off and the data line remains high.
Even if MP2 is in the “0” state, the non-selected word line
Since it is Vw / 2, no current flows through MP1. MP
When 1 is in the "0" state, a current flows from the data line 1 to the ground line via MP1, and the potential of the data line 1 drops. This is amplified by the sense amplifier to complete the read operation. The storage device can be configured in this manner.

In this storage device, as shown in FIG. 8, a normal bulk MOSFET in which peripheral circuits such as a memory decoder, a sense amplifier, a control circuit, and an output circuit are formed on the surface of a Si substrate.
The memory cell array realized by using T and including the storage elements of MP1 to MP4 in FIG. 1 can be manufactured thereover via an insulating film. This is because the polycrystalline silicon of the storage element of MP1 to MP4 can be manufactured above the bulk MOSFET. With this configuration, the area of the peripheral circuit can be omitted, and an integrated circuit approximately twice as high as the conventional dynamic RAM can be realized. In FIG. 8, there is actually a wiring layer between the bulk MOSFET and the polycrystalline silicon, but this wiring layer is omitted in the figure. As described above, the present storage device can store 1-bit information with one element, and thus can constitute a highly integrated memory integrated circuit. Further, by stacking the peripheral circuit and the memory cell as described above, the degree of integration can be further increased. Also, unlike the ordinary dynamic RAM, it is not necessary to read out the charge amount, and a signal can be generated statically on the data line. Therefore, even if the miniaturization is advanced, S
The / N ratio does not decrease. Further, accumulated information can be stored for a long time, and refreshing is not required unlike DRAM. Therefore, power consumption can be reduced,
Peripheral circuits can be simplified. As described above, it is possible to realize a memory which is more than twice as high as that of the conventional DRAM.
The cost per bit can be reduced to less than half.
In addition, the power required to hold information can be significantly reduced as compared with the related art. In the above example of the storage device, the case where Vl is negative and Vh is positive has been described as shown in FIG. When the threshold voltages Vl and Vh of the storage element are higher than this, the same operation can be performed by setting the signal for controlling the gate higher by that amount.

Next, the manufacturing process of this embodiment will be described with reference to FIG. First, an n-channel M
An OS (15) and a p-channel MOS (16) (that is, a CMOS device) are formed, an insulating film is formed thereon, and a metal wiring (17) is formed (FIG. 9A). After this, the interlayer insulating film (1
8) is deposited and flattened to reduce surface irregularities.
Next, a polycrystalline silicon region to be a gate electrode (4) of the storage element is formed. This polycrystalline silicon is doped with an n-type impurity at a high concentration to have a low resistance. An SiO ₂ film having a thickness of about 50 nm serving as a gate insulating film (5) is deposited by a chemical vapor deposition (CVD) method, and amorphous silicon serving as a channel is deposited thereon. After patterning this, the source
(1) N-type impurities such as As and P are ion-implanted into the drain region (2) and annealed at about 750 ° C., so that the channel (3) becomes polycrystalline silicon. On this, a protective film of SiO ₂ (10)
To form a highly integrated storage device of the present invention (FIG. 9).
(B)). Although not shown, by further providing a conductive layer on this, electrical noise can be shielded and the reliability of the memory can be improved.

(Embodiment 2) FIG. 10 shows a second embodiment of the present invention. As the substrate, an SOI substrate is used. Sauce (19),
And a drain (20) are low-resistance regions made of high impurity concentration n-type silicon, and a silicon channel (2
1) is a thin line. In addition, SiO ₂
A thin film (25) is formed on which a storage region (24) for confining carriers with silicon crystal grains is formed. Further thereon, a gate electrode (22) is provided with a gate insulating film (23) interposed therebetween. In this embodiment,
Since the line width of the channel (21) is small, the capacitance value Cgc between the gate electrode (22) and the channel (21) becomes small. Writing and erasing are performed by changing the potential of the gate. Writing is performed by injecting electrons in the channel into the storage region (24) across the potential barrier by the insulating film (25), while when erasing, electrons are extracted from the storage region (24) . In this embodiment, writing and erasing to and from the storage area (25) are performed by exchanging electrons with the channel, but may be performed from a channel other than the channel. This situation is the same in the following embodiments. Further, in this embodiment, Si is used for the source, drain and channel, and SiO ₂ is used for the insulating film.
The drain may be another semiconductor or metal, and the insulating film may be another. Further, in this embodiment, the storage area is provided above the channel, but it may be below or horizontally. In this embodiment, an SOI substrate is used, and single crystal Si is used for a source, a drain, and a channel.
This may be formed of polycrystalline silicon. In this case, the difference from the first embodiment is that the storage area (24) is provided independently. Further, it is not necessary that the insulating film between the channel and the storage region and the insulating film between the gate and the storage region are made of the same material. In this embodiment, electrons are used as carriers, but holes may be used. This is the same in the following embodiments. In the present embodiment, a small crystal grain is used for the storage node (24), and SiO 2 is formed around the Si crystal grain (24).
₂ (23, 25) reduces the parasitic capacitance between the surrounding area. Since the crystal grains (24) are small, the capacitance value Ctt may be calculated by the self capacitance. The self-capacity of a sphere having a radius r surrounded by a substance having a dielectric constant ε is given by 4πεr. For example, in the case of a silicon crystal grain having a particle diameter of 10 nm, the capacitance Ctt of the storage node is about 1 aF.

FIG. 11 is an enlarged view of the vicinity of the channel, the carrier confinement region, and the gate. As shown in FIG.
The gate-source voltage is set to the first voltage Vg0 (0 volt)
And a second voltage Vg1 (5 volts), the drain current exhibits hysteresis. At this time,
FIG. 1 is a potential distribution diagram at bb ′ in FIG.
3, shown in FIG. The reason why this hysteresis occurs will be described below. In the semiconductor device of FIG. 10, the channel region when the potential difference Vgs between the gate and the source is 0 volt
FIG. 13A shows the potential diagram of (21). This is Figure 1
2 corresponds to the state (25). Note that a drain current flows in a direction perpendicular to the paper surface of FIG. In the following description, it is assumed that the drain-source voltage is sufficiently smaller than the gate voltage. However, even when the voltage between the drain and the source is large, the following results hold as they are. First, as shown in FIG. 13A, the channel (21)
A potential with low energy is formed surrounded by a potential barrier (25) between the storage region (24) and the surrounding SiO ₂ film (23). Therefore, the storage region composed of Si crystal grains
(24) is surrounded by insulating films (23, 25) and can capture electrons as carriers. The energy level of the conduction band of the P-type or low impurity concentration N-type or i (intrinsic semiconductor) type channel region (21) is a high impurity concentration N-type source.
No electrons are present in the channel (21) because it is sufficiently higher than the energy level of the conduction band in (19) or the Fermi level in (19) in a degenerated high impurity concentration N-type source.
Therefore, no drain current flows. Note that the energy of the carrier confinement region (24) is sufficiently higher than the Fermi level of the source (19), and no electrons exist in this region (24). Potential difference Vgs between gate (22) and source (19)
From 0 volts to a low threshold voltage Vl,
Since the potential of the channel region (21) increases, the potential of the channel region (21) with respect to the electrons decreases as shown in FIG. 13B, and electrons are introduced from the source (19) into the channel region (21). . As a result, a current flows between the drain D and the source. Further, when the gate voltage is increased, the number of electrons in the channel region (21) further increases. However, as shown in FIG. 13C, when Vgs reaches the write voltage Vg1, the storage region (24)
Energy and the potential gradient between the channel and the channel increase, so that at least one electron is captured in the storage region (24) over the potential barrier (25) due to the thermal energy distribution of the electrons and a tunnel phenomenon. . This corresponds to the transition from the state (27) to the state (28) in FIG. As a result, as shown in FIG. 14A, a Coulomb blockade by one electron captured in the storage area (24) occurs, and the potential of the storage area (24) increases, and the electrons of the further electrons are captured. Is prevented from being injected into the storage area (24).

As described above, when one electron is captured in the storage area (24), the threshold voltage of the semiconductor device of FIG. 10 changes from the low threshold voltage Vl to the high threshold voltage Vh. The reason will be described below. That is, when Vgs is lowered in the range of Vh <Vgs <Vg1 from the state of FIG.
Although the electrons in (21) decrease, a potential barrier (25) exists between the channel and the channel, and the electrons captured in the storage region (24) remain. When the voltage of the gate (22) further decreases and becomes Vgs = Vh, the Fermi level of the source (19) is separated by about kT from the energy level of the conduction band of the channel (21), so that the electrons in the channel almost disappear. 14 (B)). Therefore, no drain current flows. This corresponds to the state (29) in FIG. However, the threshold value Vh at which the drain current does not flow becomes higher than the lower threshold voltage Vl by the voltage corresponding to the amount of charge trapped in the storage region (24). When Vgs is further lowered, for example, Vgs =
When the voltage reaches 0 volt, the potential gradient between the storage area (24) and the channel (21) increases with the decrease in the gate voltage. As a result, the electrons captured in the storage region (24) are emitted by tunneling due to the thermal energy distribution of the electrons and the electric field effect (see FIG. 14C). A potential diagram in a state where electrons are emitted is equal to the first diagram in FIG. Therefore, the semiconductor element returns to the state (25) in FIG. After that, when Vgs is raised again and swept up and down, the above operation is repeated, so that hysteresis accompanying capture / emission of electrons is observed. Even in this structure, the condition of Expression (8) is necessary to detect the presence or absence of one electron as a current value.

Next, the manufacturing process of this embodiment will be described. As shown in FIG. 10, a source (19), a drain (20), a channel (21)
To form The channel is processed into a fine wire. The source and the drain are heavily doped with n-type impurities. The channel is doped n-type, i-type, or p-type with a low impurity concentration.
Next, a SiO ₂ film (25) is deposited by the CVD method,
Silicon crystal grains (24) are formed by method D (chemical vapor deposition). Thereafter, a SiO ₂ film (23) is deposited again by the CVD method, and a metal film is deposited, and then the gate electrode (2
Form 2). In order to form the radius r of the silicon crystal grains (24), which are storage regions, fine, nuclei generated at the initial stage of deposit formation by the CVD method are used as silicon crystal grains (24). For this reason, it is desirable that the formation of the silicon crystal grains (24) by the CVD method be completed at a low temperature in a short time.

(Embodiment 3) FIG. 15 shows a third embodiment of the present invention. The difference from the second embodiment is that two gate electrodes
In (31) and (32), the channel (33) and the carrier confinement region (3
4) It has a structure sandwiching it. Therefore, the second embodiment differs from the second embodiment in that writing and erasing can be performed not only on the gate electrode 1 (31) but also on the gate electrode 2 (32). Further, when the device of Example 2 is integrated, it is expected that the potential near the carrier confinement region and the channel region fluctuates due to the influence of external potential fluctuation. It is characterized by being shielded from external potential fluctuations due to shielding.

(Embodiment 4) FIG. 16 shows a fourth embodiment of the present invention. A channel (3) of a bulk MOS structure in which a source (35) and a drain (36) are formed in a silicon semiconductor crystal substrate.
9), an insulating film (40) is provided, a plurality of silicon crystal grains (41) are formed thereon, an insulating film (42) is formed thereon, and a source (35) and a drain ( A gate electrode 2 (38) having a shape in which a gap is provided in the direction connecting 36) is provided, and a gate electrode 1 (37) is provided thereon via an insulating film (43). Source (3
5) and a drain (36) are regions made of high impurity concentration n-type bulk silicon, and a P-type region (44)
It is. When a positive voltage is applied to the gate electrode 1 (37), electrons are induced on the surface of the P-type region to form a channel (39). At this time, the potential of the gate electrode 2 (38) is changed to the gate electrode 1 (3).
Since it is set lower than 7), the gate electrode 2 (38) operates as an electrostatic shield electrode. As a result, the channel (45) is formed only in the narrow gap region of the gate electrode 2, and the effective capacitance Cgc between the gate electrode 1 (37) and the channel (39) can be reduced. Writing and erasing can be performed in the same manner as in the third embodiment by changing the potential of the gate electrode 1 (37), the gate electrode 2 (39) or the substrate (44).

(Embodiment 5) FIG. 17A shows a fifth embodiment of the present invention. The direction in which the current flows is perpendicular to the plane of the drawing, and the vicinity of the channel and the carrier confinement region is enlarged. The shapes of the source and the drain are the same as in the second embodiment. This embodiment is different from the second embodiment in that the Si channel
The structure is such that a Si thin film (48) is provided in the SiO2 insulating films (49) and (50) between (46) and the storage region (47) of Si crystal grains. The carriers in the channel (46) reach the storage area (47) via the thin film portion (48). FIG. 17B shows a potential diagram of this structure. In this thin film portion (48), an energy shift (52) occurs due to the effect of quantum confinement in the thickness direction, and in the thin film portion (48), electrons in the channel (46) try to move to the carrier confinement region (47). Acts as a barrier. As a result, in order to achieve the same barrier effect, compared with the thickness of the SiO 2 film (FIG. 10 (25)) between the channel and the carrier confinement region when this structure is not used, the gap between the channel and the carrier confinement region is reduced. SiO2 film (49), (5
The sum of the film thicknesses of 0) may be small. Therefore, the fatigue of the insulating film can be reduced, and the number of times of rewriting the memory can be increased. Note that the potential barrier using the quantum confinement effect described in this embodiment is effective in preventing the insulating film from being fatigued even if the number of carriers entering and exiting the carrier confining region (47) is large.

(Embodiment 6) In Embodiment 6, the configuration of a memory read circuit of a semiconductor memory device according to the present invention will be described with reference to FIG.
This will be described with reference to FIG. The semiconductor device of the present invention, which is one of the embodiment of FIG. 1, the embodiment of FIG. 6, the embodiment of FIG. 10, the embodiment of FIG. 15, the embodiment of FIG. As shown in the upper part, the carrier capture portion is represented by a black circle symbol to distinguish it from a normal FET. FIG.
The circuit diagram of the memory cell for bits (FIG. 10A), the voltage applied to the word line (W) and the data line (D) during reading and writing (FIG. 10A), and Dependence of the drain current of the used semiconductor element MM7 on the gate voltage (between the gate and the source) (FIG. 3 (c)).
And This circuit configuration itself is the same as that of the first embodiment shown in FIG.

FIG. 19 shows a circuit configuration for reading information stored in the memory cell MM1. Although omitted in the figure, many memory cells similar to MM1 are arranged on the array. MM1 for storing information is a conventional ordinary MOSF
The current value that can flow is smaller than that of ET. This is because the capacitance between the gate and the channel is set small.
A configuration for reading this small current value stably at high speed will be described below. The memory cell composed of the semiconductor element MM1 is connected to a data line D, and this data line (D) is connected to an input transistor M9 of a differential amplifier via a data line selection switch M5. Further, a dummy cell including MM5 and MM6 is connected to another data line (Dn) paired with the data line D. Dn is also connected to the gate terminal of the other input transistor M10 of the differential amplifier via the data line selection switch M6. Then M
The operation of reading the information of M1 will be described. FIG. 20 shows the signal timing at this time. Consider a case where MM1 is written with "0" and the threshold voltage is low. “0” is always written in the dummy cells MM5 and MM6 in advance. At the time of reading, first, S2 is set to the low level, and both D and Dn are precharged to the power supply voltage Vr. At the same time, S3 and S4 are set to the high level to connect the data lines D and Dn to the inputs M9 and M10 of the differential amplifier. Connect to At the same time, S5 and S6 are set to the high level to activate the differential amplifier and output (OUT, OUTn)
To equalize. The word lines W1 and WD are changed from low level to high level to change the cell MM1 and the dummy cell (M
When (M5, MM6) is selected, MM1 is turned on, and the potential of the data line D decreases. At the same time, the dummy cells MM5 and MM6 are turned on, and the potential of the data line Dn also decreases. However, the dummy cell is MM5
And MM6 are connected in series, the current driving capability is smaller than that of MM1, and the potential change of Dn is more gradual than D. When the data of D and Dn are determined, S6 is set to the low level to make the differential amplifier operable. The potential difference between D and Dn is amplified by a differential amplifier and output (OU).
T) goes high and the output (OUTn) goes low. This completes the reading of "0" of MM1. When MM1 is "1" (when the threshold value is high and a current does not flow much), the data line D does not drop much while being precharged, and the potential of Dn falls earlier. The potential difference between D and Dn is amplified by the differential amplifier to complete the read operation. When reading a cell consisting of MM2, MM3 and MM4 are dummy cells. Only one dummy cell needs to be provided for each data line.
The increase in area is small.

With the above circuit configuration, D, D
Reading becomes possible only by generating a slight potential difference in n. Therefore, the amount of charge to be discharged from the data line D through the MM1 is at least good, and high-speed operation is possible. In this example, MM5 and MM6 are connected in series as means for making the current of the dummy cell almost half the current of the memory cell. However, this reference can also be made by halving the channel width or reducing the applied gate voltage. A potential can be generated.

FIG. 21 shows a layout arrangement of memory cells of the semiconductor memory device. FIG. 21 (a) shows four adjacent
A circuit diagram of the cell is shown, and a corresponding mask layout is shown in FIG. The two memory cells MM91 and MM92 connected to the word line W91 share the same gate electrode, thereby omitting wiring. Further, two memory cells MM93, connected to the same data line D91,
In the MM91, the area is reduced by directly connecting the diffusion layers and sharing one contact.

(Embodiment 7) Another embodiment of the semiconductor memory device according to the present invention will be described with reference to FIGS. The present embodiment shows a configuration in which reading can be performed at a higher speed than in the sixth embodiment. FIG. 22A shows a plurality of memory cells MM51, MM52, MM5 connected to the same sub data line (D).
3 is a circuit diagram of a cell set. FIG. 3B shows a voltage applied when writing and reading to and from the memory element MM51, and FIG. 3C shows characteristics of the MM51. Reference numeral 23 shows a memory configuration using this cell set. This embodiment is most different from the sixth embodiment in that the data lines are hierarchized into a main data line (MD51) and a sub data line (D) (FIG. 2).
3), thereby enabling high-speed reading. As shown in FIG. 22A, the memory cells MM51-M
The source terminal of M53 is connected to the sub data line D. The sub data line is connected to a preamplifier composed of M53 and M52, and the output of the preamplifier (PA51) is connected to the main data line MD51 (FIG. 2).
3). A plurality of such cell sets are connected to the main data line MD51 via a preamplifier. M
D51 is a main amplifier composed of a differential amplifier (MA51)
Connected to one of the inputs. One row in which the cell sets are arranged in an array is composed of dummy cells. The dummy cell (for example, MM54) is also a preamplifier (PA52).
Is connected to another main data line MD52 via
52 is connected to the other input terminal of the main amplifier MA51. The preamplifier PA52 of the dummy cell set is designed so that the current driving capability is approximately half that of the preamplifier PA51. This can be realized, for example, by halving the channel width of the transistor.

The operation of reading information from the MM 51 will be described below. First, information of "0" is written in the dummy cell MM54 in advance. First, consider the case where information “0” is stored in the MM 51. First, the high level V is applied to S52.
By applying r and setting S51 to the ground level, the sub data line D is set to the ground level. A high level is applied to S53 to select a cell set, and M52 is turned on. At the same time, the main data lines MD51, MD5
2 is precharged to the high level Vr. When the word line W changes from low to high level (Vr), the MM 51 becomes conductive, and the sub-data line D is charged from P (= Vr) through the MM 51. As a result, M53 is turned on, and the main data line MD51 is connected to MM52 and MM5.
3 and the potential of MD51 drops. By the same operation, the dummy cell MM54 connected to the same word line is turned on, the preamplifier PA52 operates to discharge the main data line MD52, and the potential of the MD52 drops. However, since the current drive capability of the PA52 is smaller than that of the PA51, the decrease in the potential of the MD52 does not occur in the MD5.
1 is more gradual than the decrease in the potential. This MD51 and M
The potential difference from D52 is detected by the main amplifier MA51 to obtain an output. The same applies to reading “1”.

In this embodiment, the memory cell MM51 only needs to drive the sub data line D. The parasitic capacitance is small because the number of connected cells is as small as about 8-32 and the length is short. Therefore, high-speed driving can be performed by the memory element MM51. Since the main data line MD51 is driven at high speed by the preamplifier PA51, high speed operation is also possible. In the present embodiment, in order to generate a reference voltage for the differential amplifier MA51, a difference is set between the current driving powers of the preamplifier PA52 and the preamplifier PA51. This embodiment is characterized in that the variation is less likely to be affected by changing the current value in the preamplifier unit having a large transistor size as in the present embodiment than by halving the current in the cell itself as in the sixth embodiment.
Various known circuits such as the differential amplifier and the current mirror type differential amplifier circuit used in the sixth embodiment can be used as the main amplifier MA51.

In the sixth and seventh embodiments, the example in which the memory cell is constituted by one transistor has been described. However, there is a similar memory cell as shown in FIG. Same figure
(a) is a case where a back gate is provided on the opposite side of the gate electrode across the channel. When a plurality of memory cells are connected to the same back gate terminal, there is an advantage that by applying a negative voltage to this back gate, information of many memory cells can be reset to "0" at the same time. Alternatively, "1" can be written to many cells at the same time by applying a positive voltage to the back gate. As the back gate terminal, the semiconductor substrate itself or a well region can be used. In FIG. 24B, the P terminal runs in a direction parallel to the word line, and can be controlled independently for each row. FIG. 24C shows the case where the P terminal runs in the direction parallel to the data line. FIG. 24D shows a case where the gate of the memory element MM73 is connected to the data line. In this case, since the P terminal is not required, the area can be reduced. FIG.
(e) shows a case where the gate of the memory element MM74 is connected to a word line, which is also characterized by a small cell area.

Embodiment 8 FIG. 2 shows another embodiment of the present invention.
5, shown in FIG. As shown in FIG. 25 (a), the memory cell includes a storage element (MM21) of the present invention and a switching FET.
This is a circuit in which the element (M25) is connected in series.
In this circuit, the word line is connected to the gate of M25, and the voltage applied from the data line (D) to MM21 can be cut off by M25. Therefore, an unnecessary voltage is not applied to an unselected cell sharing a word line or a data line with the selected cell. Therefore, there is an advantage that the data retention characteristics are superior to those of the sixth and seventh embodiments.

Writing to this memory cell is performed as follows. First, the case where "0" is written will be described. A voltage of Vcc + Vt is applied to a selected word line, and a ground level (0) is applied to a selected data line. Thereby, M25
Becomes conductive and N21 is almost at the ground level. Since P is Vcc / 2, a voltage of -Vcc / 2 is applied between the gate and source of the MM 21 to write "0" (see FIG. 25C). Next, writing “1” will be described. Again, a voltage of Vcc + Vt is applied to the word line, and a voltage of Vcc is applied to the data line. As a result, a voltage of Vcc / 2 is applied between the gate and the source of MM21, and "1" is written (see FIG. 25C). This cell can be read by the same means as in the sixth and seventh embodiments, but the present embodiment shows a configuration in which reading and writing can be performed with a low power supply voltage. Reading from this memory will be described with reference to FIG. To read information from the memory cell consisting of M25 and MM21, the word line W21 is changed from the ground level to the power supply voltage level Vcc, and at the same time, M28, MM25,
The word line WD22 of the dummy cell composed of MM26 is changed from low to high. Subsequent reading is the same as in the sixth embodiment. However, after the output is determined, the memory cell is rewritten by the write driver connected to the output of the sense amplifier. For example, in MM21,
To write "1", Vcc is applied to the data line D.
As a result, a voltage of approximately Vcc is applied between the gate and the source of MM21, and "1" can be written. Also MM
When "0" is written to 21, D is set to the ground level. As a result, a voltage of -Vcc / 2 is applied between the gate and the source, and "0" is written. In this embodiment, rewriting is performed every time information is read from the memory. As a result, after a potential difference between the data line D and the dummy data line Dn that can be read is generated,
The information of the MM 21 may be reversed from “0” to “1”. Therefore, the read voltage V in FIG.
r and the write voltage Vcc / 2 can be set to close values. Therefore, the write voltage can be set to a low value. For example, Vr
Can be set to 3V and Vcc / 2 can be set to 4V. On the other hand, in order to assure that the inversion of information does not occur at the time of reading as in the seventh embodiment (see FIG. 22C), the writing voltage Vp needs to be about three times the reading voltage Vr. A high voltage is required for writing.

As a memory cell circuit similar to that of the present embodiment, there is a circuit shown in FIG. FIG. 27A is different from FIG. 25A in that the gate of the MM 81 is connected to P. FIG. 27B shows the case where the gate terminal of the memory element MM82 is controlled by a control signal C from outside the memory cell. FIG. 28 shows a layout of four bits of the memory cell in FIG. In FIG. 28, MM101-1
Reference numeral 04 denotes the element shown in Example 1 made of polycrystalline silicon. Also in this layout, the word lines of adjacent memory cells are formed of the same electrode, and two adjacent memory cells share a contact and are connected to a data line. This reduces the memory cell area.

(Embodiment 9) In this embodiment, another memory cell circuit and read circuit of the present invention will be described. FIG. 29A shows a circuit diagram of a memory cell, and FIG. 29B shows applied voltages at the time of reading and writing of the present memory cell.
9 (c) shows the characteristics of MM31 and MM32 used for the memory cell. This memory cell is characterized in that complementary information is written to MM31 and MM32. That is, when writing "1", a voltage of Vcc is applied to the word line W, and Ve (negative voltage) is applied to the data line D. This gives M
Since 33 is conductive, the potential of D is applied to N31, and N31 becomes Ve. Since the voltage Ve is applied between the gate and the source of the MM 32, the MM 32 enters a low threshold state. Vcc is applied between the gate and source of MM31.
A voltage of -Ve is applied, and a high threshold state is set. To write "0" in the memory cell, the data line D is set to the write voltage Vp. As a result, a state in which MM31 has a low threshold and MM32 has a high threshold can be realized. After this writing, when the potential of the data line is set to Vcc / 2, MM31
And a voltage of about Vcc / 2 is applied between the gate and the source of the MM32. In the "1" state, D is to be discharged. In the case of "0" state, D is to be charged. If this is detected by a differential amplifier as shown in FIG. 30, information can be read. In this memory cell, a difference appears whether the potential of the data line falls or rises depending on whether the information of the memory cell to be read is "1" or "0". Therefore, the reference voltage (Vcc / 2) can be directly applied to one input terminal of the differential amplifier. Therefore, no dummy cell is required. On the other hand, in the circuits according to the embodiments described above, only the difference of whether the potential of the data line is maintained or dropped depending on whether the information of the cell is "1" or "0" appears. Therefore, a dummy cell is necessary. Met.

(Embodiment 10) In this embodiment, another memory cell circuit according to the present invention will be described. FIG. 31A shows a memory cell circuit for one bit, FIG. 31B shows applied voltages at the time of reading and writing, and FIG.
1 shows the characteristics of MM42. This memory cell is shown in FIG.
Are selected by the same word line by combining two memory cells shown in FIG. In this embodiment, MM4
1 and MM42 are written with complementary information. That is, when the MM41 is in the low threshold state, the MM42 is in the high threshold state, and when the MM41 is in the high threshold state, the MM42 is in the low threshold state. Therefore, when the word line is set to the high level after writing, a potential difference appears on the data lines D and Dn reflecting the difference in current driving force between the MM41 and the MM42. As shown in FIG. 32, if D and Dn are connected to a pair of input terminals of the differential amplifier, the stored information of the cell can be read.

This embodiment is characterized in that a dummy cell is not required, and it is not necessary to generate a reference potential of the differential amplifier, and the device operates stably with respect to device variations. The circuit design is simple. Note that the same operation can be performed using the memory cell circuit shown in FIG.

In the above embodiment, an example is shown in which an n-channel insulated gate field effect transistor is used as a switching element of a memory cell. However, it is needless to say that another switching element may be used. For example, a p-channel field effect transistor can be used. In this case, the polarity of the voltage applied to the gate is opposite to that of the n-channel. Further, although the case where the storage element is an n-channel type has been described as an example, it goes without saying that a storage device can be similarly configured in the case of a p-channel type (which operates by storing holes).

(Embodiment 11) The semiconductor memory devices (memory) described in Embodiments 6 to 10 hold information in a non-volatile manner, and the time required for writing is extremely shorter than that of a conventional non-volatile memory. There is a feature that the number of times is not limited. Writing is performed at high speed because writing is completed by injecting only a few electrons. Further, the number of times of rewriting is not limited because writing can be performed by moving a small number of electrons. Such a storage device can be used as a main storage of a microprocessor in the data processing system shown in FIG. Further, since the present storage device holds information in a nonvolatile manner, the storage device holds the information even after power is turned off. Therefore, there is a feature that so-called external storage, which has conventionally been performed using a hard disk or a floppy (registered trademark) disk, can be realized by the same memory chip. Also, since the main memory is non-volatile, this computer has a feature that when the power is turned off and then turned on again, the computer can immediately return to the immediately preceding use state. Furthermore, by using the semiconductor memory device (memory) described in Embodiments 6 to 10 as the cache memory of the microprocessor, the cache memory can be made non-volatile and low power consumption can be achieved. It becomes possible.

[0053]

According to the present invention, it is possible to provide a memory having a small number of elements and a small area, which itself has an information storage function, and to provide a semiconductor element which does not require cooling to an extremely low temperature. In a semiconductor memory device using this semiconductor element, a nonvolatile memory that can be rewritten at high speed can be realized.

[Brief description of the drawings]

FIG. 1 is a structural diagram of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing actually measured values of a gate-source voltage dependency of a drain current according to the first embodiment.

FIG. 3 is an actual measurement result showing retention of information after “1” and “0” are written in the semiconductor device of the first embodiment.

FIG. 4 is a diagram showing a change in a band near a channel when a gate voltage is increased in the present invention.

FIG. 5 is a diagram showing a change in a band near a channel when a gate voltage is decreased in the present invention.

FIG. 6 is a diagram showing a configuration of a storage device of the present invention.

FIG. 7 is a diagram illustrating hysteresis characteristics assumed in the storage device of FIG. 6;

FIG. 8 is a diagram showing a structure in which a peripheral circuit is formed on the surface of a Si substrate and a memory cell is stacked thereon in Example 1 of the present invention.

FIG. 9 is a cross-sectional view showing a manufacturing process of the present invention.

FIG. 10 is a structural diagram of a semiconductor device according to a second embodiment of the present invention.

FIG. 11 is an enlarged view of the vicinity of a channel, a carrier confinement region, and a gate according to a second embodiment of the present invention.

FIG. 12 is a diagram illustrating the voltage dependency between the gate and the source of the drain current according to the second embodiment.

FIG. 13 is a diagram showing a potential distribution near a channel and a carrier confinement region when a gate voltage is increased in the present invention.

FIG. 14 is a diagram showing a potential distribution near a channel and a carrier confinement region when a gate voltage is decreased in the present invention.

FIG. 15 is a structural diagram of a semiconductor device according to a third embodiment of the present invention.

FIG. 16 is a structural diagram of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 17 is a structural diagram and a potential distribution diagram of a semiconductor device according to a fifth embodiment of the present invention.

FIG. 18 is a diagram illustrating a circuit diagram of a memory cell according to a sixth embodiment of the present invention and a diagram illustrating applied voltages.

FIG. 19 is a circuit diagram of a memory read circuit according to a sixth embodiment of the present invention.

FIG. 20 is a diagram illustrating timings of signal application according to the sixth embodiment of the present invention.

FIG. 21 is a diagram showing a circuit diagram and a mask layout of a 4-bit memory cell according to a sixth embodiment of the present invention.

FIG. 22 is a circuit diagram of a memory cell set according to a seventh embodiment of the present invention and a diagram showing characteristics of applied voltages and storage elements.

FIG. 23 is a diagram illustrating a configuration of a memory according to a seventh embodiment of the present invention.

FIG. 24 is a diagram showing a circuit diagram of a memory cell of the present invention.

FIG. 25 is a circuit diagram of a memory cell according to Example 8 of the present invention and a diagram showing characteristics of applied voltages and storage elements.

FIG. 26 is a circuit diagram of a memory read circuit according to an eighth embodiment of the present invention.

FIG. 27 is a circuit diagram of a memory cell of the present invention.

FIG. 28 is a diagram showing a circuit diagram for four bits and a corresponding mask layout according to the embodiment of the present invention.

FIG. 29 is a circuit diagram of a memory cell according to a ninth embodiment of the present invention and a diagram showing characteristics of applied voltages and storage elements.

FIG. 30 is a circuit diagram of a read / write circuit according to Embodiment 9 of the present invention.

FIG. 31 is a circuit diagram of a memory cell according to a tenth embodiment of the present invention, showing applied voltages and characteristics of storage elements.

FIG. 32 is a circuit diagram of a read circuit according to Example 10 of the present invention.

FIG. 33 is a diagram showing a modification of the memory cell according to the tenth embodiment of the present invention.

FIG. 34 is a diagram showing a data processing device using the storage device of the present invention.

[Explanation of symbols]

MP1-4, MM1-MM104: storage element of the present invention, Vgs: gate-source voltage, Cgs: capacitance between gate channels, Vl: threshold voltage in "0" state, Vh ... in "1" state Threshold voltage, Vg0 ... voltage for writing "0", Vg1
... voltage for writing "1", Vw ... absolute value of voltage applied to word line at the time of writing, M1-M104 ... insulation effect type field effect transistor, C ... capacitance between channel and carrier confinement regions, Cgt ... gate -Capacitance between carrier confinement regions, Ctt ... total capacitance with respect to the periphery of the carrier confinement region.

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) H01L 29/788 29/792 (72) Inventor Takashi Hashimoto 1-280 Higashi-Koigabo, Kokubunji-shi, Tokyo Inside Central Research Laboratory, Hitachi, Ltd. (72) Inventor Koichi Seki 1-280 Higashi Koikekubo, Kokubunji-shi, Tokyo Inside the Hitachi, Ltd. Central Research Laboratory (72) Inventor Masakazu Aoki 1-280 Higashi Koikekubo, Kokubunji-shi, Tokyo In the Hitachi, Ltd. Central Research Laboratory (72) Invention Person Ken Sakata 1-280 Higashi Koigakubo, Kokubunji-shi, Tokyo, Japan Inside the Hitachi, Ltd. Central Research Laboratory (72) Inventor Yoshinobu Nakagome 1-280 Higashi Koikekubo, Kokubunji-shi, Tokyo, Japan Inside the Central Research Laboratory, Hitachi, Ltd. (72) Inventor Miki Takeuchi 1-280 Higashi Koigakubo, Kokubunji-shi, Tokyo Inside the Hitachi, Ltd. Central Research Laboratory

Claims (10)

[Claims] 1. A semiconductor memory cell array device comprising a plurality of data lines, a plurality of word lines, and a plurality of memory cells, wherein each of the memory cells corresponds to one of the plurality of data lines. A first source region connected to a data line, a first drain region, a first channel region between the first source region and the first drain region, and a first channel region A first field-effect transistor having a first gate electrode positioned opposite to the first gate electrode, wherein the first gate electrode is connected to a corresponding word line of the plurality of word lines; A second source region connected to the first drain region, a second drain region, a second channel region between the second source region and the second drain region,
A second gate electrode positioned opposite to the second channel region; and a carrier confinement region controlled by the second gate electrode, wherein the second gate electrode includes the first gate electrode. A second field-effect transistor connected to the drain region of the semiconductor memory cell array device. 2. The semiconductor memory cell array according to claim 1, wherein said carrier confinement region is formed between said second gate electrode and said second channel region. apparatus. 3. The semiconductor memory cell array device according to claim 2, wherein a voltage between said second drain region and said second source region is constant and said second gate electrode and said second source are kept. A semiconductor memory cell array, wherein each of the memory cells has conductivity indicating hysteresis between the second source region and the second drain region when a potential difference between the second source region and the second drain region changes. apparatus. 4. The semiconductor memory cell array device according to claim 2, wherein said second gate electrode is formed of a metal or a semiconductor, said second channel region is formed of a semiconductor on an insulating layer, and said carrier confinement region is formed. Wherein each of the word lines controls a potential of a corresponding second gate electrode. 5. The semiconductor memory cell array device according to claim 2, wherein said plurality of data lines include a plurality of main data lines and a plurality of sub data lines, and wherein said first source region is provided for said plurality of sub data lines. Connected to corresponding sub-data lines, each of the sub-data lines is connected to a corresponding main data line of the plurality of main data lines via a switch or a preamplifier, and the plurality of memory cells are gridded together with the lines. A semiconductor memory cell array device characterized by being arranged in a shape. 6. The semiconductor memory cell array device according to claim 1, wherein said carrier confinement region is formed inside said second channel region. 7. The semiconductor memory cell array device according to claim 6, wherein said second gate electrode and said second source are kept in a state where a voltage between said second drain region and said second source region is constant. A semiconductor memory cell array, wherein each of the memory cells has conductivity indicating hysteresis between the second source region and the second drain region when a potential difference between the second source region and the second drain region changes. apparatus. 8. The semiconductor memory cell array device according to claim 6, wherein said second gate electrode is formed of metal or semiconductor, said second channel region is formed of semiconductor on an insulating layer, and said carrier confinement region is Wherein each of the word lines controls a potential of a corresponding second gate electrode. 9. The semiconductor memory cell array device according to claim 6, wherein said plurality of data lines include a plurality of main data lines and a plurality of sub data lines, and wherein said first source region is provided for said plurality of sub data lines. Connected to corresponding sub-data lines, each of the sub-data lines is connected to a corresponding main data line of the plurality of main data lines via a switch or a preamplifier, and the plurality of memory cells are gridded together with the lines. A semiconductor memory cell array device characterized by being arranged in a shape. 10. A semiconductor memory cell array device having a carrier confinement region formed of fine particles.