JP2001159922A - Voltage regulator circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a high power supply voltage variation removal ratio characteristic up to a high frequency area and to realize stable operation even when an output capacitor of low equivalent series resistance and small capacity is used. SOLUTION: A feedback circuit to a 1st IQS semiconductor element 13 is constituted of two stages consisting of 1st and 2nd operational amplifiers 15, 16 and a power supply variation removal ratio is improved by increasing an amplification factor. Since it is unnecessary to increase the amplification factors of these amplifiers 15, 16, power consumption can be reduced. Since a 3rd operational amplifier 17 is connected as a feedback circuit of the 2nd amplifier circuit, the increase of closed loop gain by the amplifier 16 can be suppressed and the stability of circuit operation can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage regulator circuit, and more particularly to a voltage regulator circuit which receives a voltage which may fluctuate as an input, controls the voltage, and applies a voltage stabilized to a constant voltage to a load connected to an output. And a voltage regulator circuit.

[0002]

2. Description of the Related Art As a power supply circuit for controlling a power supply voltage and supplying a constant voltage to a load, the following two methods are widely classified. In the first method, a semiconductor element is inserted between a power supply and a load, and this semiconductor element is made to act as a voltage or current control type resistance element, and a current flowing through the semiconductor element and a voltage drop generated by the resistance component are reduced. This is a method of controlling the value so that the voltage supplied to the load becomes constant. In the second method, a semiconductor element and a coil and / or a capacitor are interposed between a power supply and a load, and the semiconductor element acts as a switching element to convert electric energy into magnetic energy of the coil or electrostatic energy of the capacitor. In this method, the conversion ratio is controlled by a switching element through the conversion process and the reverse conversion process so that the voltage supplied to the load becomes constant. Usually, the former is called a linear regulator and the latter is called a switching regulator.

As is well known, a switching regulator has a high power supply conversion efficiency, can obtain a voltage higher or lower than the original power supply voltage, and can also obtain a voltage of the opposite polarity. On the other hand, linear regulators have drawbacks compared to switching regulators, such as being able to output only a voltage lower than the original power supply voltage and having lower conversion efficiency than switching regulators due to the operating principle.

However, since a linear regulator does not perform electrical switching, so-called switching noise does not occur, and the linear regulator is often used as a circuit for supplying power to electronic equipment requiring low noise. In particular, in electronic devices that handle relatively high-frequency signals, such as electronic devices that handle wireless and electronic devices that handle video signals, linear regulators are often used to prevent noise from the power supply from entering the signal band. ,
It is required that noise from a power supply be prevented more than other electronic devices.

FIG. 5 is a diagram showing a configuration example of a general linear regulator. Referring to FIG. 5, the linear regulator has a first MOS (Metal-Oxide Sequential) having a power supply terminal 1 connected to a source electrode and a drain electrode connected to an output terminal 2.
and Miconductor) type semiconductor device 3, dividing resistors R _a, which is connected between the output terminal 2 and the ground potential, and R _b, the output capacitor C and the resistor R _e, a reference voltage source 4, dividing resistors R _a , _Rb and a reference voltage signal from a reference voltage source 4, and an output from an error amplifier 5 connected to the gate electrode of the first MOS type semiconductor element 3. Is connected to a load _RL . Here, the output capacitor C is a capacitance component necessary for stabilizing a so-called control loop, which is composed of the first MOS type semiconductor element 3, the voltage dividing resistors R _a and R _b , and the error amplifier 5. Further, the resistance R _e is not intended to be implemented as an actual circuit elements, a resistor which represents the equivalent series resistance component of the output capacitor C.

The first MOS type semiconductor element 3 inserted between the power supply terminal 1 and the output terminal 2 operates as the above-described voltage control type resistance element, and divides the voltage by the voltage dividing resistors R _a and R _b. The difference between the detected output voltage signal and the reference voltage signal is amplified by the error amplifier 5, and the output signal of the error amplifier 5 controls the first MOS type semiconductor element 3 to change its resistance value. By controlling the value of the voltage drop due to the resistance component, the output voltage is kept constant as a result.

In the above-described circuit configuration, a power supply voltage fluctuation removal ratio (hereinafter, referred to as PSRR) is usually used as a characteristic value indicating the rate of voltage fluctuation generated at the output terminal 2 when AC noise is superimposed on the power supply terminal 1. ) Is used.

As described above, especially in wireless applications, it is required that a large PSRR be obtained up to a higher frequency, and the current consumption of the entire circuit is particularly large in portable applications. Low current consumption is an essential requirement.

However, in an actual circuit, the PSRR value has a characteristic of decreasing with frequency, and the decrease tends to increase sharply at a specific frequency or higher.

On the other hand, the first M which becomes a voltage control type resistance element
The size of the OS-type semiconductor element 3 is determined by the magnitude of the current to be supplied to the load _RL. However, as the size of the first MOS-type semiconductor element 3 increases, the frequency at which PSRR decreases becomes lower.

Further, in order to reduce the size of the entire circuit, it is necessary to reduce the size of the circuit components. However, the first MOS type semiconductor element 3, the error amplifier 5, the voltage dividing resistors R _a and R _b are required. Can be a single silicon semiconductor as an integrated circuit, while the output capacitor C
Are difficult to integrate and must be made as individual components. In order to realize a stable operation as a circuit, the output capacitor C
Is preferable to be large, but there is a disadvantage that the shape of the capacitor becomes large. Ceramic type capacitors are well known as small external size capacitors.
Although there is an advantage that even a small outer shape size in the same volume than are other such as tantalum capacitors, also small value of resistor R _e is an equivalent series resistance. If the value of the resistor _Re is small, the circuit shown in FIG. 5 tends to lose stability.

In order to cope with these problems, it is one of effective means to improve the characteristics of the error amplifier 5 as much as possible. Generally, a so-called operational amplifier used as the error amplifier 5 has an amplification factor and a frequency. If the characteristics are to be improved, the current consumption tends to increase, and the demand for low power consumption cannot be met.

As described above, while a small series regulator capable of suppressing noise superimposed on a power supply even at a higher frequency is desired, in the conventional circuit configuration,
There is a limit.

Here, the limit of the PSRR characteristic by the conventional circuit configuration shown in FIG. 5 will be analytically described. Figure 6 shows the MO
FIG. 3 is a diagram illustrating an equivalent circuit of an S-type semiconductor element. However, in FIG. 6 is illustrates the output resistance R _op of the error amplifier 5, voltage dividing resistors R _a, R _b, load R _L, the output capacitor C, the resistance R _e is an equivalent series resistance of the output capacitor C at the same time . First MOS type semiconductor element 3 which is a voltage control type resistor
It is well known that can be represented by an equivalent circuit as shown in FIG. Here, V _g is the gate voltage of the first MOS type semiconductor device 3, V _g1 is the output voltage of the error amplifier 5, V _s is the source voltage, V _o is the drain voltage, g _m is the transmission conductance, and V _gs is the gate. A source-to-source voltage, C _gs represents a gate capacitance, and r _ds represents a source-drain resistance.
The signal flow diagram can be drawn by obtaining the transfer function of the voltage of each part from this equivalent circuit.

FIG. 7 is a diagram showing a conventional circuit as a signal flow diagram. In FIG. 7, a portion surrounded by a broken line represents the first MOS type semiconductor element 3, and each box represents a transfer function. That is, the signal transmission element 3a to the output side of the first MOS type semiconductor element 3 represents the transfer function _Td , and the signal transmission element 3a on the gate side of the first MOS type semiconductor element 3
b denotes a transfer function T _g , and the first MOS type semiconductor device 3
The signal transfer element 3c based on the gate capacitance of the above and the output resistance of the error amplifier 5 driving the same represents the transfer function T _g1 . Each transfer function T _d , T _g , T _g1 is represented by the following equation.

The transfer function T _d is

[0017]

(Equation 1)

The transfer function T _g is

[0019]

(Equation 2)

The transfer function T _g1 is

[0021]

(Equation 3)

Here, s is a complex frequency. Further, Z _L in equation (1) is

[0023]

(Equation 4)

## EQU1 ## Where R is

[0025]

(Equation 5)

## EQU1 ## Generally, a so-called operational amplifier is used as the error amplifier, and its frequency response characteristic is such that the operational amplifier has a first pole frequency 1 / a ₁ ,
Assuming that the second pole frequency is 1 / a ₂ and the open loop gain is A ₀ , the amplification factor A of the operational amplifier is approximately expressed by the following equation.

[0027]

(Equation 6)

Using the above equation, PSRR can be expressed by the following equation from the signal flow diagram of FIG.

[0029]

(Equation 7)

Normally, the first MOS type semiconductor element 3 is
When operating in the saturation region, r _dsTo be regarded as $ 1
Can be. Also, if the amplification factor A of the operational amplifier is sufficiently large,
If you can think about it,_g1Can be regarded as A≫1
Therefore, equation (7) can be approximated as the following equation.

[0031]

(Equation 8)

The characteristic of the PSRR with respect to the frequency represented by the equation (8) is as shown in FIG. 8 when the characteristic of the operational amplifier represented by the equation (6) is combined. FIG. 8 is a diagram illustrating PSRR characteristics of a conventional circuit. This PSRR
The characteristic is a characteristic obtained from calculation, but also shows a characteristic almost similar to this characteristic in an actual circuit.

From the above analysis, the following means are effective to obtain a large PSRR up to a higher frequency. That is, the open-loop gain A ₀ of the operational amplifier is made as large as possible, the first pole frequency of the operational amplifier is made as high as possible, the gate capacitance of the first MOS type semiconductor device 3 is made as small as possible, and the output resistance of the operational amplifier is also made small. By making it as low as possible, a large PSRR can be obtained up to higher frequencies.

However, as a means for increasing the open loop gain and increasing the first pole frequency, the current consumption of the operational amplifier may be increased.
This means cannot meet the demand for low current consumption.

On the other hand, the stability of the operation as a series regulator circuit can be explained as follows. FIG.
As shown in the signal flow diagram, the series regulator has a so-called feedback amplifier configuration including the first MOS type semiconductor element 3, a load circuit, and an error amplifier 5. Therefore, the stability of the series regulator becomes the stability of the feedback amplifier itself. In order for the feedback amplifier to operate stably, as is well known, in the open loop gain characteristic of the circuit, the gain becomes 0 or less before the phase is delayed by 180 degrees.

Here, the open loop gain characteristic of the conventional circuit configuration is obtained from FIG. 6 as follows.

[0037]

(Equation 9)

As in the case of PSRR, when the first MOS type semiconductor operates in the saturation region, it can be considered that r _ds ≫1, so that equation (9) can be approximated as follows.

[0039]

(Equation 10)

FIG. 9 shows the frequency dependence of the open loop characteristic represented by the equation (10). FIG. 9 is a diagram illustrating the open-loop characteristics of the conventional circuit. From this open loop characteristic,
The following are known as means for securing stability. That is, it is advantageous for stability that the open loop gain A ₀ of the operational amplifier is not large. Further, it is preferable that the first pole frequency and the second pole frequency of the operational amplifier are as high as possible, the gate capacitance of the first MOS type semiconductor element is as small as possible, and the output resistance of the operational amplifier is as low as possible. Then, the equivalent series resistance of the output capacitor acts to return the phase lag, and advantageously acts on stability.

[0041]

Therefore, PSRR
Increasing the open loop gain of the operational amplifier, which is one of the means for improving the characteristics, impairs the stability of the circuit, and this means that this means alone is not sufficient.

While lowering the output resistance of the operational amplifier contributes to both improvement in PSRR characteristics and stability, lowering the output resistance of the operational amplifier increases the current consumption and the device for the output circuit. This increases the size, which is disadvantageous for reducing power consumption, and in the case of an integrated circuit, increases the silicon area.

Further, although the equivalent series resistance of the output capacitor is expected to be large to some extent, there is a problem that stability has to be sacrificed in response to the above-mentioned demand for reducing the outer size of the ceramic type capacitor. Was.

The present invention has been made in view of the above points, and improves the limit in the above-described conventional circuit, obtains a large PSRR characteristic up to a higher frequency region, and has a low equivalent series resistance and a low capacitance. It is an object of the present invention to provide a voltage regulator circuit that can realize a stable operation even when a small output capacitor is used.

[0045]

According to the present invention, in order to solve the above problem, one of a source electrode and a drain electrode is connected to a power supply and the other is connected to a load.
A MOS type semiconductor element, a load voltage detecting means connected between a source electrode or a drain electrode connected to the load and a ground potential for detecting a voltage of the load, and a load voltage detecting means connected in parallel to the load voltage detecting means. And a reference voltage generating means for generating a reference voltage signal serving as a reference, and an error detecting means for detecting a difference between a signal from the load voltage detecting means and the reference voltage signal. A voltage regulator that controls a gate electrode of the first MOS-type semiconductor element in accordance with a signal from the first MOS-type semiconductor element to keep a voltage of an electrode to which a load of the first MOS-type semiconductor element is connected constant. A first operational amplifier for detecting a difference between the reference voltage signal and a signal from the load voltage detecting means, and an output of the first operational amplifier as one input and the first operational amplifier A second operational amplifier having an output connected to the gate electrode of the OS-type semiconductor element, a source electrode or a drain connected to the output signal of the second operational amplifier and a power supply of the first MOS-type semiconductor element A third operational amplifier connected to input the voltage signal of the electrode and having an output connected to another input of the second operational amplifier. Is done.

According to such a voltage regulator circuit, the feedback control loop has a two-stage configuration, so that the first
And the second operational amplifier can be provided with different characteristics, and the amplification factor and the output resistance can be independently set to optimum performance. With this, PS
The RR characteristics are improved, the power consumption can be reduced, and the stability of the circuit operation can be improved.

[0047]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a diagram showing a configuration example of a specific electronic circuit of the voltage regulator circuit according to the first embodiment of the present invention. In FIG. 1, the voltage regulator circuit has a source electrode connected to a power supply terminal 11,
A first MOS having a drain electrode connected to the output terminal 12
Resistors R _a and R _b , an output capacitor C, and a resistor R connected between the semiconductor element 13 and the output terminal 12 and the ground potential to constitute a means for detecting the voltage of the load _RL.
e , a reference voltage source 14, a first operational amplifier 15 which receives load voltage detection signals from the voltage dividing resistors R _a and R _b and a reference voltage signal from the reference voltage source 14, and a first operational amplifier. A second operational amplifier 16 having an output of the amplifier 15 as one input and having an output connected to the gate electrode of the first MOS type semiconductor element 13; an output signal of the second operational amplifier 16 and a voltage of the power supply terminal 11; And a third output connected to another input of the second operational amplifier 16.
And an operational amplifier 17. Note that the first to third operational amplifiers 15, 16, 17 can use various operational amplifier circuits including general operational amplifiers. The amplification factor of the first operational amplifier 15 is “A”,
The amplification factor of the second operational amplifier 16 is indicated by “B”, and the amplification factor of the third operational amplifier 17 is indicated by “P”.

According to the above configuration, the feedback circuit to the first MOS type semiconductor element 13 has a two-stage configuration of the first operational amplifier 15 and the second operational amplifier 16, so that the amplification factor can be easily increased. Since it can be increased, PSRR can be improved, and since it is not necessary to increase the respective amplification factors, power consumption can be reduced. Further, by providing the third operational amplifier 17 as a feedback circuit of the second operational amplifier 16, an increase in the open loop gain due to the second operational amplifier 16 is suppressed, and the stability of the circuit operation is improved. it can. Hereinafter, the reason will be described in detail.

FIG. 2 is a diagram showing the structure of the control loop of the voltage regulator circuit according to the first embodiment of the present invention in the form of a signal flow diagram. In FIG. 2, a portion surrounded by a broken line corresponds to a first MOS semiconductor element 13 that regulates and outputs a power supply voltage. Signal transmission element 13
Reference numerals a and 13b denote control blocks representing the first MOS type semiconductor element 13 including the load R _L , the output capacitor C, the resistance R _e of the equivalent series resistance component thereof, and the voltage dividing resistors R _a and R _b. It is represented by transfer functions T _d and T _g . The signal transfer element 13c represents a control block having a transfer function T _g1 determined by the output resistance of the second operational amplifier 16 and the gate capacitance of the first MOS semiconductor device 13. The drain electrode of the first MOS type semiconductor element 13 is connected to the signal transmission element 15a of the first operational amplifier 15, which functions as an error amplifier for detecting an error with respect to the reference voltage _Vref of the reference voltage source 14. The configuration up to here is basically the same as the configuration of the conventional circuit shown in FIG.

Next, the signal transmission element 16a in FIG.
Is a second operational amplifier 16, which amplifies the difference between the output signal of the third operational amplifier 17 and the output signal of the first operational amplifier 15, and outputs the amplified signal to the first MOS type semiconductor device 13
Drive the gate. Further, the signal transmission element 17 of FIG.
a denotes a third operational amplifier 17 for amplifying and outputting a difference between a signal obtained from a source electrode of the first MOS type semiconductor element 13 and an output signal of the second operational amplifier 16. Third
The output of the operational amplifier 17 is connected to the input of the second operational amplifier 16, whereby a new control loop is added. Hereinafter, PS according to the configuration of the present invention will be described.
The RR characteristics and operation stability will be analytically described.

The signal transmission elements 13a, 13b, 13c
As described above, the first MOS type semiconductor element 13 including the load R _L , the output capacitor C and the resistance R _e of the equivalent series resistance component thereof, the voltage dividing resistors R _a and R _b , and the second operational amplifier 16
, And transfer functions T _d , T _g , and T _g1 determined by the gate resistance of the first MOS type semiconductor element 13.
These transfer functions T _d , T _g , and T _g1 are basically functions determined by the first MOS semiconductor device 13 used, the load R _L , the output capacitor C, and the voltage dividing resistors _Ra and _Rb . The equation is the same as the equation used in the above-described conventional circuit. That is,

[0052]

[Equation 11]

[0053]

(Equation 12)

[0054]

(Equation 13)

Is as follows. Also, Z in the equation (11)
_L is

[0056]

[Equation 14]

Is as follows. Where R is

[0058]

(Equation 15)

Is as follows. The first operational amplifier 15 is equivalent to the error amplifier 5 in the conventional circuit, and has an amplification factor A
Is represented by the following equation.

[0060]

(Equation 16)

Here, A ₀ is the open loop gain of the first operational amplifier 15. Further, the amplification factor B of the second operational amplifier 16 can be expressed by the following equation, similarly to the first operational amplifier 15.

[0062]

[Equation 17]

Here, B ₀ is the open loop gain of the second operational amplifier 16. The third operational amplifier 17 has a single amplification factor without frequency characteristics, and has a configuration that can be expressed by the following equation.

[0064]

P = P ₀ (18) Here, P is an amplification factor of the third operational amplifier 17, and P ₀ is an open loop gain of the third operational amplifier 17.

When the PSRR characteristic and the open loop gain characteristic are obtained from the above equations, the following equations are obtained.

[0066]

[Equation 19]

[0067]

(Equation 20)

As in the case of the analysis of the conventional circuit, the first M
When the OS-type semiconductor element 13 operates in the saturation region, it can be considered that r _ds ≫1, so the above equation can be approximated by the following equation.

[0069]

(Equation 21)

[0070]

(Equation 22)

From the above equation, the following can be understood as the effect of the present invention. Regarding the PSRR characteristic, the first operational amplifier 15
And the two-stage configuration of the second operational amplifier 16, even though the respective amplification factors are not large, the amplification factor “A” of the first operational amplifier 15 is used as the third term of the denominator of the equation (21). The product term with the amplification factor “B” of the second operational amplifier 16 is included, and PSRR can be improved. That is,
The amplification factor of each operational amplifier can be made lower than that of the conventional circuit. As a result, the current consumption can be reduced as compared with the case where a single operational amplifier requires a high amplification factor as in the conventional circuit. Circuit design becomes easier.

Further, regarding the stability, the second operational amplifier 16 has a configuration of a feedback amplifier circuit having the third operational amplifier 17 as a feedback circuit, and the first term of the equation (22) is As long as the second operational amplifier 16 has a sufficient gain, it becomes almost 1, and the second operational amplifier 16 does not increase the open loop gain. Therefore, although the open loop gain characteristic is substantially determined by the first operational amplifier 15, as described above, the PSRR can be increased even if the open loop gain of the first operational amplifier 15 is reduced. The gain can be kept low, which can contribute to stabilization.

The gate of the first MOS type semiconductor element 13 is driven by the second operational amplifier 16,
Is connected only to the input of the second operational amplifier 16, so that the output resistance of the first operational amplifier 15 does not affect the PSRR and the open loop characteristics of the entire circuit. The design of the operational amplifier 15 can be facilitated.

As a result, in the configuration of the present invention, PSRR can be easily increased as compared with the conventional circuit, and stability can be ensured. In addition, the characteristics required for each of the operational amplifiers are less strict than those of the conventional circuit, and the design can be simplified.

Next, a second embodiment of the present invention will be described. In the present embodiment, in the control configuration described in the first embodiment, the open loop gain A ₀ of the first operational amplifier 15 is Open loop gain B ₀
The third operational amplifier 17 is configured to have a gain of 1 or less while increasing the gain.

Although the second operational amplifier 16 has a configuration of a feedback amplifier having the third operational amplifier 17 as a feedback circuit as described in the first embodiment, the entire circuit operates stably. In this case, the second operational amplifier 1
The feedback amplifier circuit composed of the sixth operational amplifier 17 and the third operational amplifier 17 needs to be stable. The transfer characteristic of only this circuit portion is expressed by the following equation.

[0077]

(Equation 23)

FIG. 3 schematically shows this transfer characteristic. FIG. 3 is a diagram for explaining the operation of the voltage regulator circuit according to the second embodiment of the present invention. In FIG. 3, f _b1, f _b2 is the first pole and second pole of the frequency of the second operational amplifier 16 respectively, f _c is the second
Is the frequency of the pole formed by the output resistance of the operational amplifier 16 and the gate capacitance of the first MOS type semiconductor element 13.
As shown in FIG. 3, when a normal operational amplifier or the like is used as the second operational amplifier 16, the pole frequency f _b1 of the second operational amplifier 16, Output resistance of the operational amplifier 16 and the first MO
The frequency f _c of the pole formed by the gate capacitance of the S-type semiconductor element 13 and the frequency f _b2 of the second pole of the second operational amplifier 16 are in this order. Therefore, for this purpose transfer characteristic is stable, the phase is delayed by 180 degrees, at a frequency lower than f _c, the gain is required to be less than or equal to 1. To achieve this, it is advantageous to keep the gain of the second operational amplifier 16 low and keep the gain of the third operational amplifier 17 at 1 or less. In this case, by setting the gain of the first operational amplifier 15 high, the desired PS
RR can be easily obtained.

Next, a third embodiment of the present invention will be described. In the present embodiment, in the control configuration described in the first embodiment, the connection relation of each block is kept as it is, and the first pole of the second operational amplifier 16 is connected to the load of the operational amplifier. The configuration uses an operational amplifier determined by the connected capacitance and the output resistance of the operational amplifier.

As described in the second embodiment, the frequency characteristic of the feedback amplifier composed of the second operational amplifier 16 and the third operational amplifier 17 is the same as that of the first operational amplifier 16. It is characterized by three frequencies: a pole, a second pole, and a pole determined by the output resistance of the second operational amplifier 16 and the gate capacitance of the first MOS semiconductor device 13.

Naturally, the higher these frequencies are, the more stable the circuit can operate up to higher frequencies. Generally, as a method of stabilizing an operational amplifier, a method of loading a phase compensation capacitor therein to increase the frequency interval between the first pole and the second pole is generally often used. However, this technique acts to lower the frequency of the first pole, making the design of the second operational amplifier 16 of the present invention difficult.

However, as in the present embodiment, by using an operational amplifier whose first pole of the second operational amplifier 16 is determined by the capacity connected to the load of the operational amplifier and the output resistance of the operational amplifier, The second operational amplifier 16 that determines the lowest frequency among the three frequencies described above.
Is eliminated, and a circuit stable up to higher frequencies can be formed.

Various methods are known as an actual configuration method of the operational amplifier in which the first pole is determined by the capacity connected to the load of the operational amplifier and the output resistance of the operational amplifier. For this, an operational amplifier circuit called a so-called current control type operational amplifier can be used.

Next, a fourth embodiment of the present invention will be described. FIG. 4 is a diagram illustrating a configuration example of a voltage regulator circuit according to the fourth embodiment. In the present embodiment, in the control configuration described in the first embodiment, a single second MOS type semiconductor device 1
8 is used. That is, the gate electrode and the source electrode of the second MOS type semiconductor element 18 are connected to the gate electrode and the source electrode of the first MOS type semiconductor element 13,
The drain electrode is connected to the non-inverting input of the second operational amplifier 16.

As is well known, a current proportional to a voltage difference between a gate and a source of a MOS semiconductor element flows to a drain. Therefore, when the gate and the source are input, the difference is arithmetically amplified, and the third operational amplifier 17 can function.

As described above, by realizing the third operational amplifier 17 with a single second MOS type semiconductor element 18, the circuit area of the operational amplifier can be greatly reduced, and the conventional circuit has one circuit. In contrast to the configuration using only one operational amplifier, the present invention can eliminate the disadvantage of increasing the silicon area during integration by using three operational amplifiers.

Further, the single second MOS type semiconductor device 1
The use of 8 makes it possible to use a MOS type semiconductor having the same conductivity type as the first MOS type semiconductor element 13, for example, both of them can be P-channel MOSFETs.
There are many advantages in the actual circuit configuration, for example, a part of the drain of the first MOS type semiconductor element 13 can be used as the second MOS type semiconductor element 18.

[0088]

As described above, according to the present invention, the first
A signal at the load is fed back to the gate of the MOS type semiconductor element via the two-stage operational amplifier of the first operational amplifier and the second operational amplifier to perform control. As a result, the power supply voltage fluctuation rejection ratio, that is, the PSRR characteristic,
It has a value determined by the product of the amplification factors of the two operational amplifiers, and can be increased as compared with a control method using feedback of only one operational amplifier.

In addition, by adopting the two-stage configuration, the performance with respect to the amplification factor or the output resistance required for one operational amplifier can be reduced, and as a result, the current consumption of each operational amplifier can be reduced. In addition, when integration is to be achieved, the required device size can be reduced, and the silicon area can be reduced.

Since the third operational amplifier is configured as a feedback circuit with respect to the second operational amplifier, the second operational amplifier may cause an increase in the open loop gain of the voltage regulator circuit as a whole. In addition, stable operation is possible despite the fact that the first operational amplifier and the second operational amplifier are connected in series.

Since the gate of the MOS type semiconductor element is driven only by the second operational amplifier,
The output resistances of the first operational amplifier and the third operational amplifier do not have to be so low. As a result, the current consumption of the first operational amplifier and the third operational amplifier can be reduced, and the device size can be reduced. Can be reduced, and mounting can be performed with a smaller silicon area during integration.

Since the second operational amplifier has a configuration in which the first pole is determined by the capacity of the load, the first pole of the second operational amplifier is equivalently eliminated, and a higher operating amplifier is provided. It is possible to obtain a large PSRR up to the frequency domain.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration example of a specific electronic circuit of a voltage regulator circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a structure of a control loop of the voltage regulator circuit according to the first embodiment of the present invention in the form of a signal flow diagram.

FIG. 3 is a diagram illustrating an operation of a voltage regulator circuit according to a second embodiment of the present invention.

FIG. 4 is a diagram illustrating a configuration example of a voltage regulator circuit according to a fourth embodiment;

FIG. 5 is a diagram illustrating a configuration example of a general linear regulator.

FIG. 6 is a diagram showing an equivalent circuit of a MOS semiconductor device.

FIG. 7 is a diagram showing a conventional circuit as a signal flow diagram.

FIG. 8 is a diagram illustrating PSRR characteristics of a conventional circuit.

FIG. 9 is a diagram illustrating open-loop characteristics of a conventional circuit.

[Explanation of symbols]

Reference Signs List 11 power supply terminal 12 output terminal 13 first MOS type semiconductor element 13a, 13b, 13c signal transmission element 14 reference voltage source 15 first operational amplifier 15a signal transmission element 16 second operational amplifier 16a signal transmission element 17 third operational amplifier 17a signal transmission element 18 the second MOS type semiconductor device R _a, the resistance of the equivalent series resistance component R _b voltage-dividing resistor C output capacitor R _e output capacitor R _L load T _d, T _g, T _g1 transfer function V _ref reference voltage

Claims (4)

[Claims] A first electrode connected to a power supply and one of a source electrode and a drain electrode connected to a load;
A MOS type semiconductor element, a load voltage detecting means connected between a source electrode or a drain electrode connected to the load and a ground potential for detecting a voltage of the load, and a load voltage detecting means connected in parallel to the load voltage detecting means. And a reference voltage generating means for generating a reference voltage signal serving as a reference, and an error detecting means for detecting a difference between a signal from the load voltage detecting means and the reference voltage signal. A voltage regulator that controls a gate electrode of the first MOS-type semiconductor element in accordance with a signal from the first MOS-type semiconductor element to keep a voltage of an electrode to which a load of the first MOS-type semiconductor element is connected constant. A first operational amplifier for detecting a difference between the reference voltage signal and a signal from the load voltage detecting means; an output of the first operational amplifier as one input; A second operational amplifier having an output connected to the gate electrode of the MOS-type semiconductor element; a source electrode or drain connected to the output signal of the second operational amplifier and the power supply of the first MOS-type semiconductor element A third operational amplifier connected to receive the voltage signal of the electrode and having an output connected to another input of the second operational amplifier. 2. An amplification factor of said first operational amplifier is made larger than an amplification factor of said second operational amplifier, and said third operational amplifier is
2. The voltage regulator circuit according to claim 1, wherein the gain of said operational amplifier is set to 1 or less. 3. The operational amplifier according to claim 1, wherein the second operational amplifier has a frequency at which a frequency of the first pole is determined by a capacitance connected to an output and its own output resistance. Voltage regulator circuit. 4. The third operational amplifier has a gate electrode connected to the output of the second operational amplifier, a source electrode connected to a power supply connected side of the first MOS type semiconductor element, 2. The voltage regulator circuit according to claim 1, wherein a single second MOS type semiconductor element having a drain electrode connected to an input of said second operational amplifier is provided.