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JP2001144214A - Semiconductor device and bonding structure thereof - Google Patents

Semiconductor device and bonding structure thereof

Info

Publication number
JP2001144214A
JP2001144214A JP32632999A JP32632999A JP2001144214A JP 2001144214 A JP2001144214 A JP 2001144214A JP 32632999 A JP32632999 A JP 32632999A JP 32632999 A JP32632999 A JP 32632999A JP 2001144214 A JP2001144214 A JP 2001144214A
Authority
JP
Japan
Prior art keywords
semiconductor device
circuit board
solder
solder balls
tensile strength
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP32632999A
Other languages
Japanese (ja)
Inventor
Tetsuo Yoshizawa
徹夫 吉沢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP32632999A priority Critical patent/JP2001144214A/en
Publication of JP2001144214A publication Critical patent/JP2001144214A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having excellent heat shock resistance and a bonding structure thereof having a prolonged lifetime of bonding by preventing thermal stress due to difference in the coefficient of thermal expansion from concentrating at the parts where the semiconductor device and a circuit board are bonded through solder balls. SOLUTION: A semiconductor element 2 is die bonded to one side of a circuit board 1 having electrode parts formed on the opposite sides thereof and then it is wire bonded and sealed with resin 3. Subsequently, solder balls 5, 6 are mounted at the electrode parts 4 on the opposite side of the circuit board 1 thus constituting a (BGA type or CSP type) semiconductor device 7. A solder ball 6 being mounted on at least one peripheral electrode part 4 among a plurality of electrode parts 4 on the circuit board 1 is made of a material having tensile strength higher than that of the material of other solder balls 5. The solder balls 5, 6 of the semiconductor device 7 are positioned at the electrode parts 9, 10 on a circuit board 8 and soldered thus jointing the semiconductor device 7 and the circuit board 8 electromechanically.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体装置および
半導体装置と回路基板との接合構造に関するものであ
る。
The present invention relates to a semiconductor device and a bonding structure between the semiconductor device and a circuit board.

【0002】[0002]

【従来の技術】従来、半導体素子を回路基板に電気的接
合することにより構成される半導体装置であるパッケー
ジとしては、QFP(Quad Flat Package )、TCP
(TapeCarrier Package)、BGA(Ball Grid Arra
y )、CSP(Chip Scaleor Size Package)、CC
B(Controlled Collapsed Bonding)等が知られてい
る。
2. Description of the Related Art Conventionally, a package which is a semiconductor device formed by electrically bonding a semiconductor element to a circuit board includes a QFP (Quad Flat Package), a TCP, and the like.
(TapeCarrier Package), BGA (Ball Grid Arra)
y), CSP (Chip Scaleor Size Package), CC
B (Controlled Collapsed Bonding) and the like are known.

【0003】BGA型半導体装置(パッケージ)に関し
ては、例えば、米国特許第5,239,198号、米国
特許第5,285,352号、米国特許第5,381,
307号、米国特許第5,397,921号の各明細書
に記載されており、BGA型半導体装置は、回路基板
(インターポーザ)上に半導体素子(半導体チップ)を
ボンディングした後に樹脂で封止し、回路基板の半導体
素子搭載面と反対側の面上の配線電極部にはんだボール
を搭載し溶融させて構成する構造であり、BGA型半導
体装置を第2の回路基板(実装基板)へ実装する際に
は、BGA型半導体装置のはんだボールを介して第2の
回路基板(実装基板)の配線電極部にはんだ接合してい
る。
[0003] Regarding the BGA type semiconductor device (package), for example, US Pat. No. 5,239,198, US Pat. No. 5,285,352, US Pat.
No. 307 and U.S. Pat. No. 5,397,921, each of which describes a BGA type semiconductor device in which a semiconductor element (semiconductor chip) is bonded on a circuit board (interposer) and then sealed with a resin. And a structure in which solder balls are mounted and melted on wiring electrode portions on a surface of the circuit board opposite to the semiconductor element mounting surface, and the BGA type semiconductor device is mounted on a second circuit board (mounting board). In this case, the semiconductor device is soldered to the wiring electrode portion of the second circuit board (mounting board) via the solder ball of the BGA type semiconductor device.

【0004】このような従来のBGA型半導体装置の構
成を図2の(a)および(b)を用いて説明すると、表
裏両面に回路パターンと電極部を有する回路基板101
の片側の面に半導体素子102をダイボンディングして
ワイヤボンディングする。その後に、樹脂103でトラ
ンスファーモールドして半導体素子102を封止し、次
に、半導体素子102を搭載した面の反対側の面の電極
部104にはんだペーストを印刷し、はんだペースト上
にはんだボール105を搭載する。その後リフロー工程
を経てはんだペーストとはんだボール105を溶融さ
せ、はんだボール105を付着形成して外部端子とす
る。そして洗浄してはんだペーストのフラックスを除去
して、(BGA型)半導体装置107を形成している。
The configuration of such a conventional BGA type semiconductor device will be described with reference to FIGS. 2A and 2B. A circuit board 101 having a circuit pattern and electrode portions on both front and back surfaces will be described.
The semiconductor element 102 is die-bonded and wire-bonded to one surface of the semiconductor device 102. Thereafter, the semiconductor element 102 is sealed by transfer molding with a resin 103, and then a solder paste is printed on the electrode portion 104 on the surface opposite to the surface on which the semiconductor element 102 is mounted, and solder balls are formed on the solder paste. 105 is mounted. Thereafter, through a reflow process, the solder paste and the solder balls 105 are melted, and the solder balls 105 are attached and formed to form external terminals. Then, the flux of the solder paste is removed by washing to form a (BGA type) semiconductor device 107.

【0005】次に、図2の(b)に示すように、両面に
回路パターンと電極部を有する第2の回路基板(実装基
板)108の電極部109上にはんだペーストを塗布
し、BGA型半導体装置107の電極部104と第2の
回路基板108の電極部109を位置決めしはんだペー
スト上に外部端子であるはんだボール105を搭載す
る。その後、リフロー工程を経てはんだボール105と
はんだペーストを溶融させてはんだ付けを行なう。これ
により、半導体装置107の電極部104と回路基板1
08の電極部109が電気機械的に接合されることとな
る。
Next, as shown in FIG. 2B, a solder paste is applied on the electrode portion 109 of a second circuit board (mounting board) 108 having a circuit pattern and electrode portions on both sides, and a BGA type The electrode portion 104 of the semiconductor device 107 and the electrode portion 109 of the second circuit board 108 are positioned, and a solder ball 105 as an external terminal is mounted on the solder paste. Thereafter, the solder balls 105 and the solder paste are melted through a reflow process, and soldering is performed. Thereby, the electrode portion 104 of the semiconductor device 107 and the circuit board 1
08 electrode portion 109 is electromechanically bonded.

【0006】また、CSP型半導体装置(パッケージ)
に関しては、例えば、米国特許第5,346,861
号、米国特許第5,592,025号の各明細書に記載
されており、CSP型半導体装置は、半導体素子(半導
体チップ)をボンディングし樹脂封止したフレキシブル
基板の半導体素子搭載面とは反対側の面の電極部にクリ
ームはんだを印刷し、その上にはんだボールを載せ、リ
フローはんだ工程により、はんだボールをフレキシブル
基板の電極部と一体的に構成したものである。CSP型
半導体パッケージを第2の回路基板(実装基板)へ実装
する際には、第2の回路基板(実装基板)のクリームは
んだを塗布した配線電極部に対してCSP型半導体装置
のはんだボールを位置決めして搭載し、リフローはんだ
工程を経て、CSP型半導体装置のフレキシブル基板の
電極部と第2の回路基板の電極部とを電気的機械的に接
合を図っている。
A CSP type semiconductor device (package)
See, for example, US Pat. No. 5,346,861
No. 5,592,025, the CSP type semiconductor device is opposite to the semiconductor element mounting surface of a flexible substrate in which semiconductor elements (semiconductor chips) are bonded and resin-sealed. A cream solder is printed on the electrode portion on the side surface, a solder ball is placed thereon, and the solder ball is integrally formed with the electrode portion of the flexible substrate by a reflow soldering process. When mounting the CSP type semiconductor package on the second circuit board (mounting board), the solder balls of the CSP type semiconductor device are applied to the wiring electrode portions of the second circuit board (mounting board) coated with cream solder. The electrodes of the flexible substrate of the CSP type semiconductor device and the electrodes of the second circuit board are electrically and mechanically joined through the reflow soldering process after positioning and mounting.

【0007】また、CCB型の半導体装置(パッケー
ジ)に関しては、例えば、米国特許第3,292,24
0号、米国特許第3,303,393号の各明細書に記
載されており、前記米国特許第3,303,393号明
細書には、電気回路素子を電気接続するための回路パタ
ーンを形成した回路基板と、半導体素子を載せたチップ
エレメント基板とを電気機械的に接合するために、ボー
ル状のターミナルエレメントをソルダーコーティングを
介してチップエレメント基板上に載せ、回路基板の回路
パターンのターミナル部とターミナルエレメントとを位
置合わせし、はんだリフロー工程に流してはんだ接合す
る構成が開示されている。
Further, as for a CCB type semiconductor device (package), see, for example, US Pat. No. 3,292,24.
No. 0, U.S. Pat. No. 3,303,393, and in U.S. Pat. No. 3,303,393, a circuit pattern for electrically connecting electric circuit elements is formed. A ball-shaped terminal element is mounted on the chip element substrate via solder coating in order to electromechanically bond the circuit board thus formed and the chip element substrate on which the semiconductor element is mounted, and the terminal portion of the circuit pattern of the circuit board is formed. There is disclosed a configuration in which the terminal and the terminal element are aligned with each other, and are flowed through a solder reflow process to be soldered.

【0008】[0008]

【発明が解決しようとする課題】しかしながら、前述し
た従来の半導体装置であるBGAやCSPを第2の回路
基板(実装基板)へ接合することによって構成される半
導体装置の接合構造に関しては次のような問題点があ
る。
However, a bonding structure of a semiconductor device formed by bonding a BGA or a CSP, which is a conventional semiconductor device, to a second circuit board (mounting board) is as follows. Problems.

【0009】図2を用いて説明すると、半導体装置(B
GA型半導体パッケージ)107は複合材料で構成さ
れ、特に熱膨張係数が異なる複数の材料で構成されてい
る。すなわち、熱膨張係数は、半導体素子102のシリ
コンでは2〜3ppm/℃、BTレンジとガラスで構成
されている回路基板101は約13〜17ppm/℃で
あり、樹脂103はシリコンにできる限り近付けた熱膨
張係数に設定されている。また、NEMA規格のFR−
4による回路基板108の熱膨張係数は13〜17pp
m/℃程度である。
Referring to FIG. 2, the semiconductor device (B
The GA type semiconductor package 107 is made of a composite material, and particularly made of a plurality of materials having different coefficients of thermal expansion. That is, the coefficient of thermal expansion of the silicon of the semiconductor element 102 is 2 to 3 ppm / ° C., that of the BT range and the circuit board 101 made of glass is about 13 to 17 ppm / ° C., and the resin 103 is as close as possible to silicon. The coefficient of thermal expansion is set. In addition, FR-
4, the coefficient of thermal expansion of the circuit board 108 is 13 to 17 pp.
m / ° C.

【0010】したがって、半導体装置(BGA型半導体
パッケージ)107を第2の回路基板108に接合して
構成する接合構造について熱衝撃試験を行なうと、はん
だ接合部には、熱膨張係数差に基づく熱応力が発生し、
熱応力ストレスを受けることになる。
[0010] Therefore, when a thermal shock test is performed on a bonding structure formed by bonding the semiconductor device (BGA type semiconductor package) 107 to the second circuit board 108, a thermal bond based on the difference in thermal expansion coefficient is found in the solder bonding portion. Stress occurs,
It will be subjected to thermal stress.

【0011】熱応力ストレスは、はんだ接合部におい
て、その中心部よりも周辺部に大きくかかる。すなわ
ち、熱膨張係数差をΔα、温度差をΔTとし、中立点ま
たは拘束点からの距離をLとするとき、伸びΔlは次式
で表される。Δl=L×Δα×ΔT
[0011] Thermal stress is applied more to the peripheral portion of the solder joint than to the center thereof. That is, when the difference in thermal expansion coefficient is Δα, the difference in temperature is ΔT, and the distance from the neutral point or the constraint point is L, the elongation Δl is represented by the following equation. Δl = L × Δα × ΔT

【0012】はんだボール105の形状は概して樽状に
なっており、そのため、樽状の上部接続部(回路基板1
01の電極部104側)と下部接続部(第2の回路基板
108の電極部1109側)に熱応力ストレスが集中
し、クラックが生じ、最悪の場合には破断に至ってしま
う。すなわち、接合寿命が短くなり、市場でのトラブル
の原因となったりする。
The shape of the solder ball 105 is generally barrel-shaped, so that the barrel-shaped upper connection portion (the circuit board 1) is formed.
The thermal stress stress concentrates on the electrode portion 104 (side of the first electrode substrate 104) and the lower connection portion (the side of the electrode portion 1109 of the second circuit board 108), and cracks occur. In the worst case, breakage occurs. That is, the bonding life is shortened, which may cause a trouble in the market.

【0013】これを回避する策としては、半導体装置1
07と第2の回路基板108のはんだボール空隙にアン
ダーフィル材としての樹脂を注入し、はんだボール10
5にかかる熱応力を分散させる方法もあるが、リペアー
が難しくなったり、コスト高になったりする。
As a measure to avoid this, the semiconductor device 1
07 and the resin as an underfill material are injected into the solder ball gaps of the second circuit board 108, and the solder balls 10
Although there is a method of dispersing the thermal stress applied to 5, the repair becomes difficult or the cost increases.

【0014】以上は、BGA型を例にとって説明した
が、CSP型も同様な課題がある。
Although the BGA type has been described above as an example, the CSP type has similar problems.

【0015】そこで、本発明は、上述の従来技術の有す
る未解決の問題点に鑑みてなされたものであって、半導
体装置と回路基板をはんだボールを介して接合する接合
部における熱膨張係数差によって生じる熱応力集中を避
け、耐熱衝撃性に優れ、接合寿命を伸ばすことができる
半導体装置およびその接合構造を提供することを目的と
するものである。
In view of the foregoing, the present invention has been made in view of the above-mentioned unsolved problems of the prior art, and has been made in view of the above, and has been made in consideration of the difference in thermal expansion coefficient at the joint between a semiconductor device and a circuit board via solder balls. It is an object of the present invention to provide a semiconductor device which can avoid thermal stress concentration caused by the above, has excellent thermal shock resistance, and can extend a bonding life, and a bonding structure thereof.

【0016】[0016]

【課題を解決するための手段】上記目的を達成するた
め、本発明の半導体装置は、表裏両面に多数の電極部を
有する回路基板の一方の面の電極部に電子回路素子を接
合して電子回路を構成し、他方の面に外部端子である金
属ボールを多数有する半導体装置において、少なくとも
一つの金属ボールが他の金属ボールよりも引張強度が大
きい材料で作製されていることを特徴とする。
In order to achieve the above object, a semiconductor device according to the present invention comprises a circuit board having a large number of electrodes on both front and back sides, and an electronic circuit element is joined to an electrode on one side of a circuit board. In a semiconductor device which forms a circuit and has a large number of metal balls as external terminals on the other surface, at least one metal ball is made of a material having higher tensile strength than other metal balls.

【0017】本発明の半導体装置において、他の金属ボ
ールよりも引張強度が大きい材料で作製された金属ボー
ルは、前記回路基板の端部に配置され、あるいは前記回
路基板の外周辺に配列されているが好ましい。
In the semiconductor device of the present invention, a metal ball made of a material having a higher tensile strength than other metal balls is disposed at an end of the circuit board or is arranged around an outer periphery of the circuit board. Is preferred.

【0018】また、本発明の半導体装置の接合構造は、
表裏両面に多数の電極部を有する回路基板の一方の面の
電極部に電子回路素子を接合して電子回路を構成する半
導体装置の多数の外部端子である金属ボールを第2の回
路基板の電極部にそれぞれ対応させてはんだ接合する半
導体装置の接合構造において、前記半導体装置における
多数の金属ボールのうち少なくとも一つを他の金属ボー
ルよりも引張強度が大きい材料で作製し、該少なくとも
一つの金属ボールを前記第2の回路基板の電極部のうち
前記少なくとも一つの金属ボールの位置に対応する電極
部にはんだ接合して構成することを特徴とする。
Further, the bonding structure of the semiconductor device of the present invention is as follows.
A circuit board having a large number of electrode parts on both front and back sides is bonded to an electrode part on one side of a circuit board. In a bonding structure of a semiconductor device in which solder bonding is performed corresponding to each of the portions, at least one of a number of metal balls in the semiconductor device is made of a material having a tensile strength greater than other metal balls, and the at least one metal ball is formed. A ball is soldered to an electrode portion of the electrode portion of the second circuit board corresponding to the position of the at least one metal ball.

【0019】本発明の半導体装置の接合構造において、
他の金属ボールよりも引張強度が大きい材料で作製され
た金属ボールは、前記回路基板の端部に配置され、ある
いは前記回路基板の外周辺に配列されていることが好ま
しい。
In the semiconductor device bonding structure of the present invention,
It is preferable that the metal balls made of a material having a higher tensile strength than other metal balls are arranged at the end of the circuit board or are arranged around the outer periphery of the circuit board.

【0020】[0020]

【作用】本発明によれば、BGA型、CSP型等の半導
体装置(半導体パッケージ)の外部端子である金属(は
んだ)ボールのうち少なくとも一つの金属ボールの材料
を他の金属ボールの材料よりも引張強度の大きい材料と
することにより、熱膨張係数差によって生じる熱応力が
金属ボール接合部に集中してかかることを避けることが
でき、接合部のクラックや破断による重大なはんだ付け
による欠陥をなくすることができ、耐熱衝撃性に優れ、
接合寿命を向上させる接合構造を得ることができる。
According to the present invention, the material of at least one of the metal (solder) balls, which is the external terminal of a semiconductor device (semiconductor package) such as a BGA type or a CSP type, is made smaller than the material of the other metal balls. By using a material with high tensile strength, it is possible to avoid the thermal stress caused by the difference in thermal expansion coefficient being concentrated on the metal ball joint, and to eliminate defects due to serious soldering due to cracks and breaks in the joint. Can be excellent in thermal shock resistance,
A joining structure that improves the joining life can be obtained.

【0021】さらに、他の金属ボールの材料よりも引張
強度の大きい材料で作製した金属ボールをBGA型、C
SP型等の半導体装置の端部あるいは周辺部に配設する
ことにより、前述した効果が一層顕著になる。
Further, a metal ball made of a material having a higher tensile strength than that of the other metal balls is BGA type, C type
By arranging the semiconductor device at the end or the periphery of a semiconductor device such as an SP type device, the above-described effects are further enhanced.

【0022】[0022]

【発明の実施の形態】本発明の実施の形態を図面に基づ
いて説明する。
Embodiments of the present invention will be described with reference to the drawings.

【0023】(第1の実施例)図1の(a)は、本発明
の第1の実施例における半導体装置の断面図であり、同
(b)は、半導体装置を第2の回路基板に接合させた接
合構造を示す断面図である。
(First Embodiment) FIG. 1A is a sectional view of a semiconductor device according to a first embodiment of the present invention, and FIG. 1B is a sectional view of the semiconductor device mounted on a second circuit board. It is sectional drawing which shows the joined structure joined.

【0024】図1の(a)において、表裏両面に回路パ
ターンと電極部が形成された回路基板(インターポー
ザ)1の片側の面に半導体素子(半導体チップ)2をダ
イボンディングしてワイヤボンディングする。その後
に、樹脂3でトランスファーモールドし半導体素子2を
封止し、次に、半導体素子2を搭載した面の反対側の面
の電極部4にはんだペーストを印刷し、はんだペースト
上に外部端子となるはんだボール5、6を搭載する。な
お、ここで、はんだボール6は、回路基板1の複数の電
極部4の中でその周辺部に位置する4つの電極部4(図
1においては2つのみ図示)に対応して搭載されたもの
であり、はんだボール5はその他の電極部4に対応して
搭載されたものである。はんだボール5は通常一般に用
いられているSn−37%Pbで作製してあるが、前述し
た周辺部の4つのはんだボール6は、他のはんだボール
5の材料(Sn−37%Pb)よりも引張強度や伸びの大
きい材料(例えば、Sn−3.5 %Ag−0.5 %Cu)で
作製する。
In FIG. 1A, a semiconductor element (semiconductor chip) 2 is die-bonded and wire-bonded to one surface of a circuit board (interposer) 1 having a circuit pattern and electrode portions formed on both front and rear surfaces. After that, the semiconductor element 2 is sealed by transfer molding with a resin 3, and then a solder paste is printed on the electrode portion 4 on the surface opposite to the surface on which the semiconductor element 2 is mounted, and external terminals are formed on the solder paste. Solder balls 5 and 6 are mounted. Here, the solder balls 6 are mounted corresponding to the four electrode portions 4 (only two are shown in FIG. 1) located in the peripheral portion among the plurality of electrode portions 4 of the circuit board 1. The solder balls 5 are mounted corresponding to the other electrode portions 4. The solder balls 5 are made of Sn-37% Pb which is generally used. However, the four solder balls 6 in the peripheral portion described above are smaller than the material of other solder balls 5 (Sn-37% Pb). It is made of a material having high tensile strength and elongation (for example, Sn-3.5% Ag-0.5% Cu).

【0025】その後、リフロー工程により、はんだペー
ストとはんだボール5、6を溶融させて、はんだボール
5、6を電極部4にそれぞれ付着させて外部端子とす
る。そしてその後、洗浄してはんだペーストのフラック
スを除去して、半導体装置(半導体パッケージ)7を形
成する。
Thereafter, in a reflow process, the solder paste and the solder balls 5, 6 are melted, and the solder balls 5, 6 are respectively attached to the electrode portions 4 to form external terminals. Thereafter, the semiconductor device (semiconductor package) 7 is formed by washing and removing the flux of the solder paste.

【0026】以上のように構成された半導体装置(半導
体パッケージ)7は、図1の(b)に示すように、両面
に回路パターンと電極部を有する第2の回路基板(実装
基板)8に接合される。ここで、第2の回路基板8の半
導体装置7を接合する側の電極部9、10において、半
導体装置7のはんだボール5の搭載部分に対応した電極
部9の部分には通常の方法でSn−37%Pbのはんだペ
ーストを塗布し、その後、半導体装置7の周辺部の4つ
のはんだボール6を搭載した部分に対応する周辺部の電
極部10(図1においては2つのみ図示)にはディスペ
ンサーでSn−3.5 %Ag−0.5 %Cuのはんだペース
トを塗布する。
The semiconductor device (semiconductor package) 7 configured as described above is mounted on a second circuit board (mounting board) 8 having circuit patterns and electrode portions on both surfaces, as shown in FIG. Joined. Here, in the electrode portions 9 and 10 of the second circuit board 8 on the side where the semiconductor device 7 is joined, the Sn portion is formed by a usual method on the electrode portion 9 corresponding to the mounting portion of the solder ball 5 of the semiconductor device 7. A solder paste of -37% Pb is applied, and then the peripheral electrode portion 10 (only two are shown in FIG. 1) corresponding to the portion on which the four solder balls 6 are mounted in the peripheral portion of the semiconductor device 7. A solder paste of Sn-3.5% Ag-0.5% Cu is applied with a dispenser.

【0027】次いで、半導体装置7の電極部4の外部端
子であるはんだボール5、6と第2の回路基板8の電極
部9、10をそれぞれ位置決めし、半導体装置7のはん
だボール5、6を第2の回路基板8のはんだペースト上
に搭載し、その後、リフロー加熱を経て、はんだボール
5、6とはんだペーストを溶融させてはんだ付けを行な
い、半導体装置7の電極部4と第2の回路基板8の電極
部9、10をはんだボール5、6を介して電気機械的に
接合する。
Next, the solder balls 5, 6 as external terminals of the electrode portion 4 of the semiconductor device 7 and the electrode portions 9, 10 of the second circuit board 8 are positioned, respectively, and the solder balls 5, 6 of the semiconductor device 7 are positioned. The solder paste is mounted on the solder paste of the second circuit board 8 and then soldered by reflow heating to melt the solder balls 5 and 6 and the solder paste, thereby forming the electrode portion 4 of the semiconductor device 7 and the second circuit. Electrodes 9 and 10 of substrate 8 are electromechanically joined via solder balls 5 and 6.

【0028】以上のように、複数の電極部のうち周辺部
に位置する電極部に対応するはんだボールおよびはんだ
ペーストの材料として引張強度の大きい材料(Sn−3.
5 %Ag−0.5 %Cu)を用い、内側の他のはんだボー
ルおよびはんだペーストの材料として通常の材料(Sn
−37%Pb)を用い、半導体装置と第2の回路基板をこ
れらのはんだボールを介して接合して構成した接合構造
を、信頼性試験(−25℃〜125℃の温度変化を10
00サイクル)を行なった後に、電気特性を測定したと
ころ、良好な結果が得られた。
As described above, as a material of the solder ball and the solder paste corresponding to the electrode portion located in the peripheral portion among the plurality of electrode portions, a material having a high tensile strength (Sn-3.
5% Ag-0.5% Cu) and a normal material (Sn) as a material for other solder balls and solder paste inside.
(-37% Pb), and a reliability test (a temperature change of -25 ° C. to 125 ° C. of 10 ° C.) was performed using a bonding structure in which the semiconductor device and the second circuit board were bonded via these solder balls.
(00 cycles), the electrical characteristics were measured, and good results were obtained.

【0029】すなわち、周辺部のはんだボール(6)お
よびはんだペーストを内側の他のはんだボール(5)お
よびはんだペーストの材料よりも引張強度の大きい材料
を用いて接合構造を構成することにより、熱膨張係数差
によって生じる熱応力がはんだボール接合部に集中して
かかることを避けることができ、アンダーフィルなしで
も、耐クラック性が良く、接合寿命を向上させることが
できる。
That is, by forming the solder ball (6) and the solder paste in the peripheral portion using a material having a higher tensile strength than the material of the other solder balls (5) and the solder paste inside, a joint structure is formed. It is possible to prevent thermal stress caused by a difference in expansion coefficient from being concentrated on the solder ball joint, and to improve the crack resistance and improve the joint life without underfill.

【0030】上述した実施例では、外周部の4つのはん
だボールに引張強度が大きい材料を用いたが、4つに限
定されるものではなく、いずれかの端部の1つでもよ
く、また、外周辺すべてのはんだボールに引張強度が大
きい材料を用いてよく、この場合には、耐クラック性お
よび接合寿命をより一層向上させることができる。
In the above-described embodiment, a material having high tensile strength is used for the four solder balls on the outer peripheral portion. However, the material is not limited to four, and any one of the ends may be used. A material having high tensile strength may be used for all the outer and peripheral solder balls, and in this case, crack resistance and joining life can be further improved.

【0031】(第2の実施例)本実施例では、外周部の
はんだボールおよびはんだペーストをともにSn−2.0
%Ag−0.75%Cu− 3%Biの材料で作製し、内側の
他のはんだボールおよびはんだペーストを通常のSn−
37%Pbで作製し、その他の構成は図1に図示する実施
例と同様の構成とした。
(Second Embodiment) In this embodiment, both the solder balls and the solder paste on the outer peripheral portion are made of Sn-2.0.
% Ag-0.75% Cu-3% Bi, and the other solder balls and solder paste inside are made of normal Sn-
It was made of 37% Pb, and the other configuration was the same as that of the embodiment shown in FIG.

【0032】本実施例においても、信頼性試験(−25
℃〜125℃の温度変化を1000サイクル)を行なっ
た後に、電気特性を測定したところ、良好な結果が得ら
れ、耐クラック性および接合寿命を向上させることがで
きた。
Also in this embodiment, the reliability test (−25)
After 1000 cycles of a temperature change of from 125 ° C. to 125 ° C.), good results were obtained, and crack resistance and joining life could be improved.

【0033】以上のように、はんだボールには通常Sn
−37%Pbが用いられているが、このSn−37%Pbの
材料よりも引張強度や伸びがともに大きい材料として
は、Sn−Ag系、Sn−Ag−Cu系、Sn−Ag−
Cu−Bi系、Sn−Zn系、Sn−Zn−Bi系等の
材料があり、これらの内のいかなる組成のものであって
も、通常のSn−37%Pbよりも引張強度が大きい材料
であれば、本発明におけるはんだボールの材料として用
いることができる。
As described above, the solder balls usually have Sn
Although -37% Pb is used, materials having higher tensile strength and elongation than the material of Sn-37% Pb include Sn-Ag, Sn-Ag-Cu, and Sn-Ag-
There are Cu-Bi-based, Sn-Zn-based, Sn-Zn-Bi-based and other materials, and any material of these materials has a higher tensile strength than ordinary Sn-37% Pb. If there is, it can be used as a material of the solder ball in the present invention.

【0034】[0034]

【発明の効果】以上説明したように、本発明によれば、
BGA型、CSP型等の半導体装置の外部端子である複
数の金属ボールのうち少なくとも一つの金属ボールの材
料を他の金属ボールの材料よりも引張強度の大きい材料
とすることにより、熱膨張係数差によって生じる熱応力
が金属ボール接合部に集中してかかることを避けること
ができ、接合部のクラックや破断による重大なはんだ付
けによる欠陥をなくすることができ、耐熱衝撃性に優
れ、接合寿命を向上させる接合構造を得ることができ
る。
As described above, according to the present invention,
By making at least one metal ball of a plurality of metal balls, which are external terminals of a semiconductor device such as a BGA type or a CSP type, a material having a higher tensile strength than a material of other metal balls, a difference in thermal expansion coefficient is obtained. The thermal stress caused by the metal ball joint can be prevented from being concentrated on the joint, the joint can be prevented from serious defects due to soldering due to cracks or breakage, and it has excellent thermal shock resistance and longer joint life. An improved bonding structure can be obtained.

【0035】さらに、他の金属ボールの材料よりも引張
強度の大きい材料で作製した金属ボールをBGA型、C
SP型等の半導体装置の周辺部に配設することにより、
効果が一層顕著になる。
Further, a metal ball made of a material having a higher tensile strength than that of the other metal balls is a BGA type,
By arranging it around the semiconductor device such as SP type,
The effect becomes more pronounced.

【図面の簡単な説明】[Brief description of the drawings]

【図1】(a)は、本発明の第1の実施例における半導
体装置の断面図であり、(b)は、半導体装置を第2の
回路基板に接合させた接合構造を示す断面図である。
FIG. 1A is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention, and FIG. 1B is a cross-sectional view illustrating a bonding structure in which the semiconductor device is bonded to a second circuit board. is there.

【図2】(a)は、従来の一般的な半導体装置の断面図
であり、(b)は、従来の一般的な半導体装置を第2の
回路基板に接合させた接合構造を示す断面図である。
2A is a cross-sectional view of a conventional general semiconductor device, and FIG. 2B is a cross-sectional view illustrating a bonding structure in which the conventional general semiconductor device is bonded to a second circuit board. It is.

【符号の説明】[Explanation of symbols]

1 回路基板 2 半導体素子 3 (封止)樹脂 4 電極部 5 はんだボール 6 はんだボール 7 半導体装置(半導体パッケージ) 8 第2の回路基板(実装基板) 9、10 電極部 DESCRIPTION OF SYMBOLS 1 Circuit board 2 Semiconductor element 3 (sealing) resin 4 Electrode part 5 Solder ball 6 Solder ball 7 Semiconductor device (semiconductor package) 8 Second circuit board (mounting board) 9, 10 Electrode part

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】 表裏両面に多数の電極部を有する回路基
板の一方の面の電極部に電子回路素子を接合して電子回
路を構成し、他方の面に外部端子である金属ボールを多
数有する半導体装置において、少なくとも一つの金属ボ
ールが他の金属ボールよりも引張強度が大きい材料で作
製されていることを特徴とする半導体装置。
An electronic circuit is formed by bonding an electronic circuit element to an electrode portion on one surface of a circuit board having a large number of electrode portions on both front and back surfaces, and has a plurality of metal balls as external terminals on the other surface. In a semiconductor device, at least one metal ball is made of a material having higher tensile strength than other metal balls.
【請求項2】 他の金属ボールよりも引張強度が大きい
材料で作製された金属ボールは、前記回路基板の端部に
配置されることを特徴とする請求項1記載の半導体装
置。
2. The semiconductor device according to claim 1, wherein a metal ball made of a material having higher tensile strength than other metal balls is disposed at an end of the circuit board.
【請求項3】 他の金属ボールよりも引張強度が大きい
材料で作製された金属ボールは、前記回路基板の外周辺
に配列されることを特徴とする請求項1記載の半導体装
置。
3. The semiconductor device according to claim 1, wherein metal balls made of a material having a higher tensile strength than other metal balls are arranged around the outer periphery of the circuit board.
【請求項4】 表裏両面に多数の電極部を有する回路基
板の一方の面の電極部に電子回路素子を接合して電子回
路を構成する半導体装置の多数の外部端子である金属ボ
ールを第2の回路基板の電極部にそれぞれ対応させては
んだ接合する半導体装置の接合構造において、 前記半導体装置における多数の金属ボールのうち少なく
とも一つを他の金属ボールよりも引張強度が大きい材料
で作製し、該少なくとも一つの金属ボールを前記第2の
回路基板の電極部のうち前記少なくとも一つの金属ボー
ルの位置に対応する電極部にはんだ接合して構成するこ
とを特徴とする半導体装置の接合構造。
4. A metal ball which is a large number of external terminals of a semiconductor device forming an electronic circuit by joining an electronic circuit element to an electrode portion on one surface of a circuit board having a large number of electrode portions on both front and back surfaces. In a bonding structure of a semiconductor device, which is solder-bonded corresponding to each of the electrode portions of the circuit board, at least one of a large number of metal balls in the semiconductor device is made of a material having a higher tensile strength than other metal balls, A bonding structure for a semiconductor device, wherein the at least one metal ball is solder-bonded to an electrode portion of the electrode portion of the second circuit board corresponding to the position of the at least one metal ball.
【請求項5】 他の金属ボールよりも引張強度が大きい
材料で作製された金属ボールは、前記回路基板の端部に
配置されることを特徴とする請求項4記載の半導体装置
の接合構造。
5. The bonding structure for a semiconductor device according to claim 4, wherein a metal ball made of a material having higher tensile strength than other metal balls is disposed at an end of the circuit board.
【請求項6】 他の金属ボールよりも引張強度が大きい
材料で作製された金属ボールは、前記回路基板の外周辺
に配列されることを特徴とする請求項4記載の半導体装
置の接合構造。
6. The bonding structure for a semiconductor device according to claim 4, wherein metal balls made of a material having higher tensile strength than other metal balls are arranged on the outer periphery of said circuit board.
JP32632999A 1999-11-17 1999-11-17 Semiconductor device and bonding structure thereof Pending JP2001144214A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP32632999A JP2001144214A (en) 1999-11-17 1999-11-17 Semiconductor device and bonding structure thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP32632999A JP2001144214A (en) 1999-11-17 1999-11-17 Semiconductor device and bonding structure thereof

Publications (1)

Publication Number Publication Date
JP2001144214A true JP2001144214A (en) 2001-05-25

Family

ID=18186567

Family Applications (1)

Application Number Title Priority Date Filing Date
JP32632999A Pending JP2001144214A (en) 1999-11-17 1999-11-17 Semiconductor device and bonding structure thereof

Country Status (1)

Country Link
JP (1) JP2001144214A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6879041B2 (en) 2002-04-17 2005-04-12 Renesas Technology Corp. Semiconductor device with joint structure having lead-free solder layer over nickel layer
US6900551B2 (en) 2002-05-21 2005-05-31 Renesas Technology Corp. Semiconductor device with alternate bonding wire arrangement
JP2008192859A (en) * 2007-02-06 2008-08-21 Matsushita Electric Ind Co Ltd Semiconductor device and its manufacturing method
JP2009182172A (en) * 2008-01-31 2009-08-13 Hitachi Ltd Electronic component circuit board
US7656019B2 (en) 2005-09-30 2010-02-02 Renesas Technology Corp. Semiconductor device and a manufacturing method of the same
US7683485B2 (en) 2007-03-07 2010-03-23 Nec Electronics Corporation Semiconductor device

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6879041B2 (en) 2002-04-17 2005-04-12 Renesas Technology Corp. Semiconductor device with joint structure having lead-free solder layer over nickel layer
US6900551B2 (en) 2002-05-21 2005-05-31 Renesas Technology Corp. Semiconductor device with alternate bonding wire arrangement
US7656019B2 (en) 2005-09-30 2010-02-02 Renesas Technology Corp. Semiconductor device and a manufacturing method of the same
US7879655B2 (en) 2005-09-30 2011-02-01 Renesas Electronics Corporation Semiconductor device and a manufacturing method of the same
JP2008192859A (en) * 2007-02-06 2008-08-21 Matsushita Electric Ind Co Ltd Semiconductor device and its manufacturing method
US9018761B2 (en) 2007-02-06 2015-04-28 Panasonic Corporation Semiconductor device
US7683485B2 (en) 2007-03-07 2010-03-23 Nec Electronics Corporation Semiconductor device
JP2009182172A (en) * 2008-01-31 2009-08-13 Hitachi Ltd Electronic component circuit board

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