JP2001022718A - Parallel processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a standby processor to take over the processing of one of in-use processors speedily without losing multiple processing requests if the in-use processor gets out of order and to avoid deterioration in system performance due to access convergence on a common memory at the time of normal operation. SOLUTION: The parallel processor is equipped with processors 11 to 18; and the N processors 11 to 16 are in-use processor and the remaining processors 17 and 18 are standby processors. The in-use processors 11 to 16 process external processing requests and the standby processors 17 and 18 temporarily store processing requests addressed to the in-use processors 11 to 16 in a main storage part 102, and read out and process the processing request to one of the in-use processors 11 to 16 which is stored in the main storage part 10 if the in-use processor gets out of order.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-processor information processing device (for example, a communication control device) comprising N active processor modules and M spare processor modules when the active processor module fails. The present invention also relates to a technique for transferring an unprocessed processing request held by a failed processor to a spare processor module.

[0002]

2. Description of the Related Art In an information processing apparatus for processing a large number of processing request commands at a high speed, a multiprocessor configuration has conventionally been employed in order to increase the processing capacity. Further, since such an information processing apparatus is required to be fault-tolerant, fault-tolerance is realized by allowing one or two processors to be on standby and taking over the processing when the active processor fails. Is often used.

Japanese Patent Application Laid-Open No. 4-217059 discloses a method in which a spare processor takes over the processing of a failed active processor in such a working / standby multiprocessor system.

FIG. 7 shows the configuration of this multiprocessor system, in which four processor cards 11 to 14 are provided.
Are connected to the shared memory card 21. Each processor has the same configuration and includes a CPU 101, a random access memory 102, and a memory interface 109.

FIG. 8 is an operation image diagram of software operating on the hardware configuration shown in FIG. The shared memory 21 has a shared message queue 2111 to 2114 for transmitting a message to each processor card.
Is realized by software. On each processor card, two tasks 1011 and 1012 for actually processing a message are operating, and local message queues 1001 and 1002 for transmitting a message to each task are provided. Also task 1
021 monitors the shared message queues 211 to 2114, and when a message is stored, checks the destination task of the message and copies the message to the local message queue of the task. However, when the message is copied, the copy source message stored in the shared message is not deleted.

Next, the task 10 of the processor card 11
The operation when transmitting a message from the task 12 to the task 1012 of the processor card 13 will be described.

The task 1012 of the processor card 11
Writes the transmission message to the shared message queue 2113 on the shared memory 21. The task 1021 on the processor card 13 detects that the message has been written to the shared message queue 2113, determines that the destination is the task 1012, and transfers the message stored in the shared message queue 2113 to the processor card 1313. Is copied to the local message queue 1002, and the message on the shared message queue 2113 is set with a copied flag. Next, the task 1012 of the processor card 13 is
02, the message is read, and processing is performed in accordance with the content. When the processing is completed, a message deletion request is sent to the task 1021. The task 1021 deletes the corresponding message from the shared message queue 2113.

Next, the operation when one of the processor cards fails will be briefly described. First, in FIG. 8, the processor card 14 is a spare processor card,
Assume that tasks 1011 and 1012 on processor card 14 are waiting as backup tasks. When the processor card 13 fails, the message held in the shared message queue 2113 is copied to the message queue 2114, and the message queue 211
The message in 3 is discarded. Further, the copied flag is reset when the message is copied. In this manner, unprocessed messages stored in the local message queues 1001 and 1002 and the shared message queue 2113 of the processor card 13 are transferred to the backup tasks 1001 and 10
02, the processing of the message addressed to the failed processor card 13 is normally continued on the processor card 14.

[0009]

When a message is transmitted / received via such a shared memory, even if an arbitrary processor fails, a message for that processor is stored in a shared memory accessible from another processor. Therefore, there is an advantage that the processing of the failed processor can be relatively easily taken over. However, since data for processing a message received by each processor is also stored in the shared memory at the same time, access to the shared memory is concentrated and the overall system performance is degraded.

As one of the methods for solving this problem, there is a method of having a queue for storing a message for each processor in a processor module. However, in such a configuration, when any processor module fails, it is necessary to transfer a message held in the module to a spare processor,
There is a problem that the takeover processing time becomes long. Further, depending on the content of the failure, it is not possible to transfer a message to be taken over, and there is a problem that a plurality of messages held in the failed module are lost.

The present invention has been made in view of the above points, and when one of the active processors fails, the processing is immediately transferred to a spare processor without losing a plurality of processing requests. It is another object of the present invention to provide a parallel processing apparatus capable of avoiding deterioration of system performance due to concentrated access to a shared memory during normal operation.

[0012]

A parallel processing apparatus according to the present invention includes a plurality of processors, a failure detecting means, and a takeover control means, each of which includes a storage means, an operation mode determining means, and a self processor identification. A processor having an operating mode determining means for N processors among the plurality of processors and an operating mode determining means for the remaining M processors as spares, The processing request sent from the outside to its own processor is processed, and the processor (spare processor) whose operation mode determination means is a spare temporarily stores the processing request addressed to the working processor in the storage means, When one of the processors fails, one of the spare processors determined by the takeover control means to take over the processing of the failed active processor is stored in the memory. In the processing request addressed active processor failed is stored in, but which is adapted to process the processing request outstanding.

[0013] In the parallel processing device of the present invention, in the parallel processing device, the processor includes a processing request buffer and a general-purpose storage means, and the active processor temporarily stores a processing request addressed to its own processor in the processing request buffer. After that, the processing request is read from the processing request buffer and the processing corresponding to the request is performed, and the spare processor temporarily stores the processing request addressed to the active processor in the processing request buffer,
Thereafter, the processing request is read from the processing request buffer and temporarily stored in the storage unit, and when one of the active processors fails, one of the spare processors determined by the takeover control unit to take over the processing of the failed active processor. Indicates that only the processing request addressed to the failed processor is kept stored in the processing request buffer, and the processing request that was being processed when the failure occurred is selected from the processing requests addressed to the failed active processor stored in the storage means. A request and a processing request stored thereafter are read out and processed in the order of storage, and after all the processing is completed, processing of a processing request addressed to the failed active processor stored in the processing request buffer is started. It is.

According to the parallel processing apparatus of the present invention, in the above-mentioned parallel processing apparatus, when one of the active processors fails, one of the spare processors determined by the takeover control means to take over the processing of the failed active processor is replaced by the failed processor. Only the processing request addressed to the failed processor is continuously stored in the processing request buffer, and among the processing requests addressed to the failed active processor stored in the storage unit, the processing request that was being processed when the failure occurred is selected. The processing requests stored after the next processing request are read out in the storage order and processed, and after the processing is completed, processing of the processing request addressed to the failed active processor stored in the processing request buffer is started. It is.

[0015] In the parallel processing device of the present invention, in the parallel processing device, when one of the active processors fails, one of the spare processors determined by the takeover control means to take over the processing of the failed active processor is replaced by the failed processor. Only the processing request addressed to the failed processor is kept stored in the processing request buffer, and the processing request that was being processed when the failure occurred is selected from among the processing requests addressed to the failed active processor stored in the storage means. Is read, and it is determined whether the processing request can be continued or re-executed.If the processing request can be continued or re-executed, the processing is continued or re-executed. Discard, read out the processing requests stored after the next processing request of the processing request that was being processed next and process them, and after the processing is completed, Is obtained so as to start processing of the processing request of the failed active addressed processor is stored in the management request buffer.

In the parallel processing apparatus of the present invention, in the above-mentioned parallel processing apparatus, the active processor notifies the standby processor of the completion of the processing every time the processing of the processing request read from the processing request buffer is completed. Each time a notification of processing completion is given, a processing request addressed to the working processor for which processing has been completed among processing requests stored in the storage means is discarded.

The parallel processing device according to the present invention, in the above-mentioned parallel processing device, includes a shared storage unit that can be referred to by all the active processors and all the spare processors, and the shared storage unit has a counter area corresponding to each of the active processors. The working processor counts up the value of the corresponding counter area every time the processing of the processing request read from the processing request buffer is completed, and the spare processor sets the corresponding counter every time the processing request is discarded. The value of the area is counted down.

In the parallel processing apparatus according to the present invention, in the above-described parallel processing apparatus, a shared storage unit which can be referred to by all the active processors and all the spare processors is provided. A processing request identifier area for storing an identifier for identifying a request is provided, and each time the active processor starts processing a processing request read from the processing request buffer, the identifier of the processing request that has started processing in the corresponding processing request identifier area. Remember
When one of the active processors has failed, one of the spare processors determined by the takeover control means to take over the processing of the failed active processor reads the value of the processing request identifier area corresponding to the failed active processor, and stores the data in the storage means. Is determined from the processing requests stored in the active processor.

[0019]

(Embodiment 1) FIG. 1 is a block diagram of a parallel processing apparatus according to Embodiment 1 of the present invention.

In FIG. 1, 11 to 18 are processors having the same configuration, 11 to 16 are working processors, 17 to
It is assumed that 18 is operating as a spare processor. 21 is a shared memory card for storing shared data, 3
1 is a command relay card for controlling transmission / reception of control commands to / from the outside; 61 is a failure monitoring card for monitoring the occurrence of a failure in the processor cards 11 to 16 and the shared memory card 21 and determining a spare processor to take over the processing of the failed active processor It is.

The processors 11 to 18 include a CPU 101,
Randomly accessible main storage unit 102, IO bus 41
A reception control unit 103 for controlling reception of a control command from the
A reception FIFO 104 for storing received control commands in a first-in-first-out manner, a mode flag 105 for identifying whether the processor operates as a working processor or a spare processor, a processor ID register for storing an ID for identifying a processor, and control. A transmission control unit 107 that controls the output of a command to the IO bus, a G bus control unit 108, and a failure detection unit 109 that detects a failure that has occurred inside the processor such as a parity error that occurs in the main storage unit 102 or an internal bus.
It is composed of Reference numeral 41 denotes an IO bus that connects the processors 11 to 18 to the command relay card 31, and 51 denotes a G that connects the processors 11 to 18 and the shared memory card 21.
The bus 71 is a failure detection unit and a failure monitoring card 6 for each card.
1 is a monitoring bus for connecting to the monitoring bus.

It is to be noted that reference numerals 11 to 16 denote working processors, and 17
18 are assumed to be spare processors, the mode flags 105 of the active processors 11 to 16 are reset to 0, and the mode flags 105 of the spare processors 17 to 18 are set to 1. The reception control unit 103
When the mode flag 105 is reset, only the control command addressed to the own processor is received, and the mode flag 1
When 05 is set, control commands addressed to all active processors are received. Further, the processing content of the processing program operating on the CPU 101 also changes depending on the value of the mode flag.

FIG. 2 shows a format of a control command transmitted and received between the command relay card and the processors 11 to 18. Reference numeral 401 denotes a transmission destination ID field indicating the transmission destination of the command, 402 denotes a transmission source ID field indicating the transmission source of the command, 403 denotes a size field indicating the size of the entire control command, and 404 denotes a serial number for uniquely identifying the control command. A number field, 405 is a processing type field indicating the contents of the processing request, 406 is a data field for storing parameters and the like when the processing specified in the processing type field 405 is performed, and 407 is an end code field indicating the end of the control command. is there.

FIG. 3 shows a data structure for temporarily storing control commands addressed to the active processors 11 to 16 constructed by software on the main storage units 102 of the standby processors 17 and 18. Reference numeral 201 denotes a first-in-first-out control command transmitted to the active processor 11.
This is a reception queue that stores data in the reception FIFO 104
Has the capacity of the maximum size of the control command added to the capacity of the control command. Similarly, reference numerals 202 to 206 denote active processors 1 respectively.
The control commands transmitted to addresses 2 to 16 are stored.

FIG. 4 shows a data structure for notifying completion of control command processing, which is constructed on the shared memory 21 by software. A processing completion counter 211 is incremented each time the active processor 11 completes processing of the control command, and decremented each time the standby processor 17 reads out the control command from the reception queue 201 and discards it. Similarly, 212 to 216 are incremented by the working processors 12 to 16 and decremented by the spare processor 17. Also, 221 to 226
Is incremented by the active processors 11 to 16 and decremented by the standby processor 18.

The operation of the first embodiment will be described below with reference to FIGS.

First, when a control command arrives at the command relay card 31 from the outside, the command relay card 31
Selects one working processor from the working processors 11 to 16. In the command relay card 31 according to the first embodiment, the active processor 11 is selected first, and then the active processors 12, 13, 14, 15, and 16 are selected in order to select the active processor in a round-robin manner. , The working processor 11 is selected again.
Now, assuming that the control command arrives from the outside for the first time, the active processor 11 is selected, so that the command relay card 31 transmits the control command destination ID field 4
01 is written into the processor ID of the active processor 11,
The control command is transmitted to the IO bus 41. Note that various embodiments are conceivable as a method for selecting the active processor, such as selecting a processor having a small number of residual control commands in the reception FIFO 104. In the initial state, the reception FIFO 104 and the reception queue 2 of the processors 11 to 18 are used.
01 to 206 are all empty and the processing completion counter 21
1 to 216 and 221 to 226 are all 0.

The reception control unit 103 of the working processor 11 in which the mode flag 105 is reset always transmits the transmission destination ID of the control command transmitted on the IO bus and the processor ID stored in the processor ID register 106.
Are compared. Now, the active processor 11 is added to the transmission destination ID.
, The control command having the processor ID of "1" is transmitted to the IO bus 41, and the control command up to the end code 407 is stored in the reception FIFO 104. At this time, the active processors 12 to 16 do not receive the control command transmitted to the IO bus 41 because the processor ID stored in each processor ID register 106 and the transmission destination ID do not match.

On the other hand, the reception control units of the spare processors 17 and 18 in which the mode flag 105 is set receive all the processor-directed control commands regardless of the processor ID stored in the processor ID register 106. The control command addressed to the working processor 11 is received.

Active processor 1 that has received the control command
1 receives the command reception interrupt signal C
Output to PU101. The CPU 101, which has received the command reception interrupt signal, reads the oldest control command stored in the reception FIFO 104 and performs the requested processing according to the contents of the processing type field 405 and the data field 406. Although the processing content changes depending on the content of the processing type field 105, a typical processing flow is to read data in the shared memory 21, perform a series of processing, write the result back to the shared memory 21 again, and Is created and sent to the outside via the transmission control unit 107. Therefore, by examining the data on the shared memory 21, it is possible to know the processing progress of the control command being processed. Then, when the processing of the control command is completed, the value of the processing completion counter 211 on the shared memory 21 is counted up.

On the other hand, the reception control units of the standby processors 17 and 18 that have received the control command similarly output a command reception interrupt signal to the CPU 101, and the CPU 101 that has received the command reception interrupt signal transmits the command reception interrupt signal to the reception FIFO 10
4 is read out. But,
The processing from here is different between the spare processors 17 and 18 in which the mode flag 105 is set. CPU 101
Reads the value of the transmission destination ID field of the read control command, and determines to which active processor the control command was addressed. Since the processor ID of the active processor 11 is stored in the transmission destination ID field, the read control command is stored in the main storage unit 10.
2 is stored in the reception queue 201 for the active processor 11 on the second. The spare processor 17 checks the value of the processing completion counter 211 for the working processor 11 on the shared memory 21. When the value of the processing completion counter 211 is positive, the control command whose processing has been completed is
To mean that it remains in the receive queue 201 of
The control command is read from the reception queue 201 and discarded, and the value of the processing completion counter 211 is decremented.
This process is repeated until the value of the process completion counter becomes zero. However, the value of the processing counter 211 is now 0, which is the initial value.
Therefore, this process is not performed. Spare processor 18
Similarly, the same control command is stored in the reception queue 201.

Next, it is assumed that the second control command has arrived at the command relay card 31. Command relay card 3
1 selects the working processor 12 as the next destination, the control command is stored in the receiving FIFO 104 of the working processor 12 and processed similarly. Also,
The control commands are similarly stored in the respective reception queues 202 in the spare processors 17 and 18.

Similarly, the control commands arriving at the command relay card 31 one after another are the active processors 13, 14,
15 and 16 are stored and processed in the reception FIFOs 104 and the reception queues 2 of the standby processors 17 and 18
03, 204, 205, and 206.

Next, the operation when the seventh control command arrives at the command relay card 31 will be described.

The seventh control command is stored again in the receiving FIFO in the active processor 11 and processed in the same manner.

Similarly, the backup processors 17 and 18 store the seventh control command in the reception queue 201. However, the last processing differs from the processing of the sixth control command. When the spare processor stores the seventh control command in the reception queue 201, the processing of the first control command has already been completed on the active processor 11, and the processing completion counters 211 and 221 are 1. This indicates that one control command for which processing has been completed remains in the reception queue 201.
U101 reads out and discards this control command, and decrements the processing completion counters 211 and 221. At this point, only the seventh control command that has not been processed or is being processed is stored in the reception queue 201.

Next, a description will be given of the processing when the control commands arrive at the command relay control card 31 one after another and the processing of the active processors 11 to 16 is temporarily out of time.

The command relay card 31 sends a control command onto the IO bus 41 irrespective of the state of the working processors 11 to 16, and the reception control unit 103 of each of the working processors 11 to 16 is executed by the CPU 101. Irrespective of processing, receive control command addressed to own processor
It is stored in O104. However, since the CPU 101 prohibits the input of a command reception interrupt from outside during the processing of the control command, even if the reception control unit 103 outputs the command reception interrupt to the CPU 101, the processing of the control command currently being processed is not performed. At the end, the control command read processing from the reception FIFO is not executed until the command reception interrupt input is permitted. Therefore, in such a case, the control commands stay in the reception FIFO one after another.

On the other hand, the operation of the spare processors 17 and 18 in such a state is as follows. All control commands addressed to the active processors 11 to 16 are stored in the reception FIFO 104 of the standby processors 17 and 18. As with the working processors 11 to 16, the reception FIFO
While the control command is read from the command queue 104 and stored in the corresponding reception queues 201 to 206, the command reception interrupt input from the reception control unit 103 to the CPU 101 is prohibited, but this process is performed in the process type field 405 of the control command. Compared to the designated process, the process is completed in an extremely short time, and thus the control command does not stay in the reception FIFO 104 and is stored in the reception queues 201 to 206 one after another. Further, as described above, the reception queue 201
Each time a control command is stored in each of the receiving queues 201 to 206
Means that the control commands being processed by the active processors 11 to 16 and staying in the reception FIFO are always stored.

Next, it is assumed that the fault detection unit 109 of the active processor 11 detects a parity error in the main storage unit 102 in such a state.

The failure detection unit 109 of the working processor 11 that has detected the parity error outputs a failure detection interrupt signal to the CPU 101. C to which failure detection interrupt signal is input
The PU 101 suspends the processing of the control command and enters an idle state. Further, the reception control unit 103 stops receiving control commands from the IO bus.

The failure monitoring card 61 is provided with the monitoring bus 7
1 to detect that the working processor 11 has failed, and first determine a spare processor to take over the processing.
Since no failure has been detected in the spare processors 17 and 18, the spare processor 17 having the smaller processor ID is selected, and a mode switching interrupt is output to the spare processor 17 via the G bus 51. The CPU 101 of the spare processor 17 that has received the mode switching interrupt reads the processor ID of the failed active processor card from the failure monitoring card 61 via the G bus 51. The processor ID (the processor I of the active processor 11)
D) is written and the mode flag is reset. At this point, the reception control unit 103 sets the active processor 11
Of the active processor 11
The control command addressed to is stored in the reception FIFO 104. However, at this time, since the CPU 101 has not permitted the input of the command reception interrupt, the processing of the control command stored in the reception FIFO has not been started yet.

Next, the CPU 101 of the processor 17
The value of the processing completion counter 211 for the active processor 11 is read out. If the value is positive, the processing completion control command is read out from the reception queue 201 and discarded, and the processing completion counter 211 is discarded by the number of control commands discarded. Decrement. At this point, the reception queue 201 stores the control command being processed by the failed active processor 11 and the control command staying in the reception FIFO 104.

Next, the CPU 101 reads a control command from the reception queue 201. Since it is considered that the active processor 11 is processing this control command, it is determined whether or not the data on the shared memory 21 has been updated at the time of failure. If the data on the shared memory 21 has not been updated, the processing of this control command is executed again from the beginning. If the data on the shared memory 21 has been updated, it is determined that the control command cannot be re-executed, and the control command is discarded.

Subsequently, the CPU 101 sets the reception queue 20
The control command is read from 1 and processing is performed according to the content. This process is continued until the reception queue 201 becomes empty. When the processing of the last control command in the reception queue 201 is completed, the CPU 101 permits command reception interrupt input. At this time, the working processor 11 completes the processing of the control command held at the time of occurrence of the failure,
The processing of the control command transmitted to the active processor 11 is started after the occurrence of the failure, and the takeover of the active processor 11 is completed. Thereafter, the processor 17 having the processor ID of the working processor 11 operates as the working processor 11.

Note that, depending on the timing of the occurrence of a failure,
There is a possibility that a control command other than that directed to the active processor 11 may remain in the reception FIFO 104. In this case, the control packet destined for the active processor 11 is discarded. When the operation as the active processor 11 is started, the reception queues 201 to 206 of the main storage unit 102 are cleared and become a general-purpose storage area.

The spare processor 18 continues the same operation as before, and takes over the processing when another working processor fails.

As described above, according to the present invention, it is possible to quickly take over the processing of the failed active processor to the spare processor without increasing the load on the shared bus. In addition, even in the worst case, only one control command being processed is lost, and loss of a plurality of control commands can be prevented.

In the first embodiment, it is determined whether or not the failed working processor can re-execute the control command being processed, and the control command is discarded only when the re-execution is not possible. If the recovery process for the command has been sufficiently realized, or if it is difficult to determine the possibility of re-execution, the control command being processed unconditionally may be discarded.

In the first embodiment, a queue for each active processor is constructed in the main memory of the spare processor in order to store a control command addressed to the active processor. However, the control command is stored in one area of the main memory. And memorize them together.
Various storage methods are conceivable, such as managing a pointer to each control command for each active processor.

In the first embodiment, the standby processors 17 and 18 have received the control commands addressed to all the active processors 11 to 16. However, the number of the active processors is extremely small compared to the processing capabilities of the processors. In such a case, the processing may be shared such that the standby processor 17 receives a control command addressed to the active processors 11 to 13 and the standby processor 18 receives a control command applied to the active processors 14 to 16. However, in this case, there is a demerit that the number of options of the spare processor taking over the processing is reduced.

Embodiment 2 Hereinafter, Embodiment 2 of the present invention will be described. The second embodiment differs from the first embodiment only in the data structure on the main storage unit, the data structure on the shared memory, and the method of accessing the data. Therefore, only portions different from the first embodiment will be described below.

FIG. 5 shows a data structure for storing control commands, which is constructed by software on the main storage unit 102 of the backup processors 17 and 18. A reception buffer 231 stores the control command transmitted to the active processor 11 in a ring buffer system. Receive buffer 2
Reference numeral 31 has a capacity obtained by adding the maximum size of the control command to the capacity of the reception FIFO 104, stores the control command from the head of the reception buffer, and overwrites the control command from the head again when the capacity becomes full. Similarly 232-
Reference numeral 236 stores control commands transmitted to the working processors 12 to 16, respectively.

FIG. 6 shows a data structure for storing the serial numbers of the control commands being processed by the active processors 11 to 16, which is constructed by software on the shared memory. A serial number area 241 stores the value of the serial number field 404 of the control command each time the active processor 11 starts processing the control command. Similarly 2
42 to 246 are updated by the working processors 12 to 16.

First, a control command from the outside arrives at the command relay card 31, and the reception FI of the active processor 11
Stored in the FO 104, the CPU 101
Up to the point where the control command is read out from step 04, it is the same as the first embodiment. The CPU 101 performs the requested processing according to the contents of the processing type field 105 of the control command, but stores the value of the serial number field 404 in the serial number area 241 on the shared memory 21 immediately before starting the processing. The CPU 101 which has completed the processing of the control command permits the reception interrupt input, but does not access the shared memory 21 at the time of completion of the processing as in the first embodiment.

On the other hand, the standby processors 17 and 18 transmit the control command stored in the reception FIFO to the transmission destination ID thereof.
According to the values of the receiving buffers 231 to 2
36 is stored in the order of reception. And the receiving buffers 231 to 231
When 236 is full, control commands are stored again from the beginning while overwriting. At this time, as in the first embodiment, the processing completion counter 21 on the shared memory 21
With reference to 1 to 226, it is not possible to discard the processed control commands stored in the reception queues 201 to 206. Therefore, the reception buffers 231 to 236 store the control commands most recently received by the active processors 11 to 16 in an amount corresponding to the capacity.

Next, it is assumed that the fault detection unit 109 of the working processor 11 detects a fault in such a state.
As in the first embodiment, a mode switching interrupt is input to the standby processor 17, and the CPU 101 writes the processor ID of the active processor 11 in the processor ID register and resets the mode flag. At this point, the standby processor 17 starts storing the control command addressed to the active processor 11 in the reception FIFO 104. However, as in the first embodiment, the CPU 101 has not yet read out the control command stored in the reception FIFO.

Next, the CPU 101 reads the value of the serial number area 241 on the shared memory 21 and, when a failure occurs, acquires the serial number of the control command that is being processed by the active processor 11 or that has completed the processing. Next, CPU
Reference numeral 101 denotes a serial number field 40 in the order from the newest control command stored in the reception buffer 231.
4 is compared with the read serial number, and the corresponding control command is read.

Next, by examining the data on the shared memory 21, it is determined whether the read control command is re-executable in the processing, is not re-executable in the processing, or is completed. I do. If re-executable, the control command is re-executed. Otherwise,
Discard the control command.

Next, the control command newly received next is read from the reception buffer 231 and the processing is performed. The same processing is performed up to the newest control command, and when the processing is completed, the reception interrupt is permitted. The subsequent operation is the same as in the first embodiment.

As described above, the same effects as in the first embodiment can be obtained by the second embodiment.

Note that if a processing flag is added to the serial number area of the second embodiment and the working processor sets the processing flag before starting the processing and resets the processing flag after the processing is completed, the serial number can be changed. Processing completion determination of the matched control command becomes easy.

As in the first embodiment, the in-process control command may be discarded unconditionally, and there are various methods for realizing the reception buffer.

[0064]

As described above, the present invention makes it possible to efficiently take over to a spare processor. In a parallel processing apparatus having a multi-processor configuration of a working / spare configuration, the spare processor is always used as the working processor. By storing the control command addressed to the storage unit in the spare processor, it is possible to quickly read the unprocessed processing request of the failed active processor and increase the load without increasing the load on the shared bus. . Moreover, even in the worst case, only one control command being processed at the time of occurrence of a failure is lost, and loss of a plurality of control commands can be prevented.

When the processor operates as a standby processor, it uses a processing request buffer and general-purpose storage means used when operating as an active processor.
By storing the control command addressed to the working processor, the above-mentioned effect can be obtained without increasing new hardware.

Each time the processing of the control command is completed in the active processor, the completed control command stored in the storage unit in the standby processor is discarded, so that the standby processor can control the unprocessed control command. Only the command can be stored in the storage unit, and the control command that was being processed by the failed active processor can be read at high speed and the processing can be taken over.

Further, by notifying the completion of the processing using the shared storage unit used by the working processor for processing the control command, the new processor does not increase in new hardware.
The control command that was being processed by the failed active processor can be read at high speed and the processing can be taken over.

Also, by storing an identifier for identifying the control command being processed by the active processor in the shared storage unit, the frequency of reference to the shared storage unit for notification of processing completion occurring during normal operation can be reduced. Can be.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a parallel processing device according to Embodiments 1 and 2 of the present invention;

FIG. 2 shows the I of the parallel processing device according to the first and second embodiments of the present invention;
Data structure diagram showing control command format transmitted and received on O bus

FIG. 3 is a data structure diagram for temporarily storing a control command addressed to an active processor, configured on a main memory of a spare processor, in the parallel processing device according to the first embodiment of the present invention;

FIG. 4 is a data structure diagram for processing completion notification configured on a shared memory of the parallel processing device according to the first embodiment of the present invention;

FIG. 5 is a data structure diagram for temporarily storing a control command addressed to an active processor, which is configured on a main memory of a spare processor, in the parallel processing device according to the second embodiment of the present invention;

FIG. 6 is a data structure diagram for storing a serial number of an in-process control command configured on a shared memory in the parallel processing device according to the second embodiment of the present invention;

FIG. 7 is a block diagram showing a hardware configuration of a conventional parallel processing device.

FIG. 8 is an image diagram showing an operation of software of a conventional parallel processing device.

[Explanation of symbols]

 11-16 Active processor 17-18 Spare processor 21 Shared memory 31 Command relay card 41 IO bus 51 G bus 61 Failure monitoring card 71 Monitoring bus 101 CPU 102 Main storage unit 103 Reception control unit 104 Reception FIFO 105 Mode flag 106 Processor ID register 107 Transmission control unit 108 G bus control unit 109 Memory interface 201 to 206 Reception queue 211 to 216 Processing completion counter area 221 to 226 Processing completion counter area 231 to 236 Receiving buffer 241 to 246 Serial number area 401 Destination ID field 402 Transmission Source ID field 403 Size field 404 Serial number field 405 Processing type field 406 Data field 407 End code field

Claims (7)

[Claims] 1. A processor comprising: a plurality of processors; a failure detection unit; and a takeover control unit. The processor includes a storage unit, an operation mode determination unit, and a self-processor identification unit. N (N is a positive integer)
Of the remaining processors (M is a positive integer) as spares, and the processor whose operation mode is current (hereinafter referred to as the current processor) A processing request sent from the outside to its own processor, and the processor whose operation mode is a spare (hereinafter referred to as a spare processor) temporarily stores the processing request addressed to the working processor in the storage means, When the failure detecting means detects that one of the active processors has failed, the takeover control means stores one of the spare processors determined to take over the processing of the failed active processor in the storage means. Reading and processing an unprocessed processing request among the processing requests addressed to the failed working processor. Parallel processing apparatus. 2. The processor according to claim 1, wherein the processor includes a processing request buffer for holding a plurality of external processing requests and general-purpose storage means, and the working processor temporarily stores only processing requests addressed to its own processor in the processing request buffer. After that, the processing request is read from the processing request buffer and the processing is performed according to the request, and the spare processor temporarily stores the processing request addressed to the active processor in the processing request buffer, Reading the processing request from the processing request buffer and temporarily storing the processing request in the storage unit, and when one of the active processors fails, the takeover control unit determines that the processing of the failed active processor is to be taken over. One of the spare processors continues to store only the processing request addressed to the failed processor in the processing request buffer. And among the processing requests addressed to the failed working processor stored in the storage means, the processing requests being processed when the failure occurred and the processing requests stored thereafter are read out in the order of storage. 2. The parallel processing apparatus according to claim 1, wherein after processing is completed, processing of the processing request addressed to the failed active processor stored in the processing request buffer is started. 3. When one of said working processors fails,
One of the spare processors determined to take over the processing of the failed working processor by the takeover control means continues to store only the processing request addressed to the failed processor in the processing request buffer, and stores the processing request in the storage means. From among the stored processing requests addressed to the failed working processor, the processing requests stored after the processing request following the processing request being processed at the time of occurrence of the failure are read and processed in the order of storage, and 3. The parallel processing apparatus according to claim 2, wherein after completion of the processing, processing of the processing request addressed to the failed active processor stored in the processing request buffer is started. 4. A process continuation determining means for determining whether a process being processed at the time of occurrence of a failure can be continued or re-executed,
When one of the working processors has failed, the takeover control means determines that one of the spare processors takes over the processing of the failed working processor, and stores only the processing request addressed to the failed processor in the processing request buffer. First, from among the processing requests addressed to the failed working processor stored in the storage unit, the processing request that was being processed when the failure occurred is read out, and the processing continuation determining unit Determines whether the processing request can be continued or re-executed.If the processing request can be continued or re-executed, the processing is continued or re-executed.If neither continuation nor re-execution is possible, the processing request is discarded. Next, the processing requests stored after the processing request following the processing request being processed are read and processed in the order of storage, and after the processing is completed. Parallel processor according to claim 2, wherein the start processing of the processing request for the failed working addressed processor is stored in the processing request buffer. 5. The working processor notifies the spare processor of the completion of processing each time the processing of the processing request is completed, and the spare processor stores the processing completion in the storage means every time the completion of processing is notified. The parallel processing device according to claim 1, wherein the processing request destined for the working processor for which the processing has been completed among the processing requests that have been completed is discarded. 6. A shared storage unit that can be referred to by all of the active processors and all of the spare processors, and a counter area corresponding to each of the active processors is provided in the shared storage unit. Each time the processing of the processing request read from the processing request buffer is completed, the value of the corresponding counter area is counted up, and each time the spare processor discards the processing request, the value of the corresponding counter area is 6. The parallel processing device according to claim 5, wherein: 7. A shared storage unit that can be referred to by all of the active processors and all of the spare processors, and stores an identifier for identifying a processing request being processed by each of the active processors in the shared storage unit. A processing request identifier area is provided, and whenever the processing of the processing request is started, the working processor stores the processing request identifier that started the processing in the corresponding processing request identifier area, and one of the working processors When a failure occurs, one of the spare processors determined by the takeover control unit to take over the processing of the failed active processor reads the value of the processing request identifier area corresponding to the failed active processor, and Out of the processing requests stored in the means, Parallel processing apparatus according to any one of claims 1 to 4, characterized in that the separate.