JP2001015552A - Flip-chip mounting method - Google Patents
Flip-chip mounting methodInfo
- Publication number
- JP2001015552A JP2001015552A JP11188939A JP18893999A JP2001015552A JP 2001015552 A JP2001015552 A JP 2001015552A JP 11188939 A JP11188939 A JP 11188939A JP 18893999 A JP18893999 A JP 18893999A JP 2001015552 A JP2001015552 A JP 2001015552A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- height
- substrate
- electrode pad
- electric connection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/1401—Structure
- H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/145—Material
- H01L2224/14505—Bump connectors having different materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
- H01L2224/1751—Function
- H01L2224/17515—Bump connectors having different functions
- H01L2224/17517—Bump connectors having different functions including bump connectors providing primarily mechanical support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8112—Aligning
- H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
- H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
- H01L2224/81139—Guiding structures on the body
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、ＩＣチップを基板
にフェースダウンで接続するフリップチップ実装方法に
関する。The present invention relates to a flip-chip mounting method for connecting an IC chip to a substrate face-down.
【０００２】[0002]
【従来の技術】従来、ＩＣチップを基板にフェースダウ
ンで接続するフリップチップ実装方法として、例えば特
開平５−２１８１３５号公報があげられる。この方法
は、電極パッド（ランド）が設けられた基板に高さ規制
部材（硬化層）を設け、ＩＣチップの電極パッドに電気
接続部材（半田バンプ）を設け、ＩＣチップを基板上に
搭載して前記高さ規制部材でＩＣチップの基板上の高さ
を規制し、前記電気接続部材の加熱接続を行うことによ
り、基板の電極パッドとＩＣチップの電極パッドとを電
気接続部材を介して電気的に接続する。2. Description of the Related Art Conventionally, as a flip chip mounting method for connecting an IC chip to a substrate face down, for example, Japanese Patent Application Laid-Open No. Hei 5-218135 is known. In this method, a height regulating member (hardened layer) is provided on a substrate provided with electrode pads (lands), an electric connection member (solder bump) is provided on an electrode pad of an IC chip, and the IC chip is mounted on the substrate. The height of the IC chip on the substrate is regulated by the height regulating member, and the electric connection member is heated and connected, so that the electrode pads of the substrate and the IC chip are electrically connected via the electric connection member. Connection.
【０００３】[0003]
【発明が解決しようとする課題】ところで最近、ＩＣの
動作周波数を１ギガヘルツを超えるような高周波化が進
展し、静電容量や誘電率の影響を受け易くなっている。
このＩＣの高周波化に伴い、ＩＣチップと基板間の間隔
を±５μｍ以下に規制することが要求されるようになっ
た。しかし、従来技術のように、基板に設けた高さ規制
部材でＩＣチップの高さを規制するには、基板の表面は
悪く、またフォトレジストで形成すると、電気的特性を
満足させるために必要な±５μｍ以内の高さ精度に規制
することは困難である。By the way, recently, the operating frequency of the IC has been increased to a frequency exceeding 1 gigahertz, and the influence of the capacitance and the dielectric constant has been increased.
With the increase in the frequency of the IC, it has been required to regulate the distance between the IC chip and the substrate to ± 5 μm or less. However, as in the prior art, the surface of the substrate is poor in order to regulate the height of the IC chip by the height regulating member provided on the substrate, and when formed of photoresist, it is necessary to satisfy the electrical characteristics. It is difficult to regulate the height accuracy to within ± 5 μm.
【０００４】本発明の課題は、ＩＣチップの高さ制御を
容易に一定にすることができるフリップチップ実装方法
を提供することにある。[0004] It is an object of the present invention to provide a flip chip mounting method capable of easily controlling the height of an IC chip to be constant.
【０００５】[0005]
【課題を解決するための手段】上記課題を解決するため
の本発明の手段は、ＩＣチップには、電極パッドに設け
られた電気接続部材と高さ規制部材とを設け、前記ＩＣ
チップに設けられた電気接続部材を基板上の電極パッド
上に位置決め搭載し、前記ＩＣチップに設けられた高さ
規制部材でＩＣチップの高さ制御を行い、前記電気接続
部材の加熱接続を行ってＩＣチップの電極パッドと基板
の電極パッドとを接続することを特徴とする。According to the present invention, there is provided an IC chip comprising: an IC chip provided with an electric connection member provided on an electrode pad and a height regulating member;
The electric connection member provided on the chip is positioned and mounted on the electrode pad on the substrate, the height of the IC chip is controlled by the height regulating member provided on the IC chip, and the heating connection of the electric connection member is performed. And connecting the electrode pads of the IC chip to the electrode pads of the substrate.
【０００６】[0006]
【発明の実施の形態】本発明の一実施の形態を図１によ
り説明する。図１（ａ）に示すように、基板１には電極
パッド２が形成されている。ＩＣチップ３には、電極パ
ッド２に対応して電極パッド４が形成され、電極パッド
４には半田、スタッドバンプ、導電接着剤等よりなる電
気接続部材５が設けられている。またＩＣチップ３に
は、電気接続部材５より硬質の高さ規制部材６が設けら
れている。ここで、高さ規制部材６の高さは、電極パッ
ド４の高さに電気接続部材５の高さを加えた高さより低
く形成されている。DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described with reference to FIG. As shown in FIG. 1A, an electrode pad 2 is formed on a substrate 1. An electrode pad 4 is formed on the IC chip 3 in correspondence with the electrode pad 2, and the electrode pad 4 is provided with an electrical connection member 5 made of solder, stud bump, conductive adhesive or the like. Further, the IC chip 3 is provided with a height regulating member 6 which is harder than the electric connection member 5. Here, the height of the height regulating member 6 is formed to be lower than the height obtained by adding the height of the electric connection member 5 to the height of the electrode pad 4.
【０００７】そこで、図１（ａ）に示すように、基板１
に設けられた電極パッド２にＩＣチップ３に設けられた
電気接続部材５を位置合わせし、続いて図１（ｂ）に示
すように搭載し、電気接続部材５を加熱する。これによ
り、ＩＣチップ３の自重又は加圧により電気接続部材５
が沈み込み、ＩＣチップ３は高さ規制部材６が基板１に
接して高さが規制される。一例として、高さ規制部材６
に銅を、電気接続部材５に共晶半田を用いた場合、接続
のために２００°Ｃ程度に加熱すると、１００ｇ程度の
加圧力で所定の目的を達成することができる。Therefore, as shown in FIG.
The electrical connection member 5 provided on the IC chip 3 is positioned with respect to the electrode pad 2 provided on the IC chip 3, and then mounted as shown in FIG. 1B, and the electrical connection member 5 is heated. As a result, the weight of the IC chip 3 or the pressurization of the electrical connection member 5
Sinks, and the height of the IC chip 3 is regulated by the height regulating member 6 being in contact with the substrate 1. As an example, the height regulating member 6
In the case where copper is used and eutectic solder is used for the electric connection member 5, if the connection is heated to about 200 ° C., a predetermined object can be achieved with a pressure of about 100 g.
【０００８】図２は本発明の第２の実施の形態を示す。
前記実施の形態においては、電気接続部材５は半田等の
ように、例えば２００°Ｃの加熱によって変形する材質
の場合である。本実施の形態においては、電気接続部材
５が例えば２００°Ｃの加熱では変形しない銅等の場合
を示す。FIG. 2 shows a second embodiment of the present invention.
In the above-described embodiment, the electric connection member 5 is made of a material such as solder which is deformed by heating at 200 ° C., for example. In the present embodiment, a case is shown in which the electric connection member 5 is made of copper or the like that does not deform when heated at, for example, 200 ° C.
【０００９】図２（ａ）に示すように、高さ規制部材６
を電気接続部材５より長く形成する。そして、電気接続
部材５の先端に半田ペースト又は導電接着剤等のように
流動性を有する導電部材７を設け、電極パッド４、電気
接続部材５及び導電部材７を加えた高さを高さ規制部材
６より長く形成する。このように形成しても、前記と同
様に、図２（ｂ）に示すように、基板１に設けられた電
極パッド２にＩＣチップ３に設けられた電気接続部材５
を位置合わせして搭載し、導電部材７を加熱して接合す
る。これにより、ＩＣチップ３の自重又は加圧により導
電部材７が沈み込み、ＩＣチップ３は高さ規制部材６が
基板１に圧接して高さが規制される。As shown in FIG. 2A, the height regulating member 6
Is formed longer than the electrical connection member 5. A conductive member 7 having fluidity such as a solder paste or a conductive adhesive is provided at the tip of the electric connection member 5, and the height of the electrode pad 4, the electric connection member 5, and the conductive member 7 is regulated. It is formed longer than the member 6. Even when formed in this manner, similarly to the above, as shown in FIG. 2B, the electric connection members 5 provided on the IC chip 3 are provided on the electrode pads 2 provided on the substrate 1.
Are mounted in alignment, and the conductive member 7 is heated and joined. As a result, the conductive member 7 sinks due to its own weight or pressure of the IC chip 3, and the height of the IC chip 3 is regulated by the height regulating member 6 being pressed against the substrate 1.
【００１０】図３は本発明の第３の実施の形態を示す。
前記各実施の形態のように、高さ規制部材６をＩＣチッ
プ３に設けると、そのためのスペースが必要となり、Ｉ
Ｃチップ３の利用効率が低下する。本実施の形態は、高
さ規制部材６を電気的導電材として電気接続に用いるも
のである。そこで、図２で用いた導電部材７を高さ規制
部材６に設けた。その他の構成は図２と同じである。高
さ規制部材６は、該高さ規制部材６に設けた導電部材７
で基板１の電極パッド２に接続されるので、高さ規制部
材６を電気接続に用いることができる。FIG. 3 shows a third embodiment of the present invention.
When the height regulating member 6 is provided on the IC chip 3 as in each of the above embodiments, a space for the height regulating member 6 is required.
The utilization efficiency of the C chip 3 decreases. In the present embodiment, the height regulating member 6 is used for electrical connection as an electrically conductive material. Therefore, the conductive member 7 used in FIG. Other configurations are the same as those in FIG. The height regulating member 6 includes a conductive member 7 provided on the height regulating member 6.
Thus, the height regulating member 6 can be used for electrical connection.
【００１１】[0011]
【発明の効果】本発明によれば、ＩＣチップには、電極
パッドに設けられた電気接続部材と高さ規制部材とを設
け、前記ＩＣチップに設けられた電気接続部材を基板上
の電極パッド上に位置決め搭載し、前記ＩＣチップに設
けられた高さ規制部材でＩＣチップの高さ制御を行い、
前記電気接続部材の加熱接続を行ってＩＣチップの電極
パッドと基板の電極パッドとを接続するので、ＩＣチッ
プの高さ制御を容易に一定にすることができる。According to the present invention, the IC chip is provided with an electric connection member provided on the electrode pad and a height regulating member, and the electric connection member provided on the IC chip is connected to the electrode pad on the substrate. Positioning and mounting on the IC chip, the height of the IC chip is controlled by a height regulating member provided on the IC chip,
Since the electrode connection of the IC chip is connected to the electrode pad of the substrate by performing the heating connection of the electric connection member, the height control of the IC chip can be easily made constant.
【図１】本発明のフリップチップ実装方法の一実施の形
態を示し、（ａ）は実装前の説明図、（ｂ）は実装後の
説明図である。FIG. 1 shows an embodiment of a flip-chip mounting method according to the present invention, in which (a) is an explanatory diagram before mounting and (b) is an explanatory diagram after mounting.
【図２】本発明のフリップチップ実装方法の第２の実施
の形態を示し、（ａ）は実装前の説明図、（ｂ）は実装
後の説明図である。FIGS. 2A and 2B show a flip-chip mounting method according to a second embodiment of the present invention, wherein FIG. 2A is an explanatory diagram before mounting and FIG. 2B is an explanatory diagram after mounting.
【図３】本発明のフリップチップ実装方法の第３の実施
の形態を示し、（ａ）は実装前の説明図、（ｂ）は実装
後の説明図である。3A and 3B show a third embodiment of the flip-chip mounting method of the present invention, wherein FIG. 3A is an explanatory diagram before mounting, and FIG. 3B is an explanatory diagram after mounting.
１ 基板 ２ 電極パッド ３ ＩＣチップ ４ 電極パッド ５ 電気接続部材 ６ 高さ規制部材 ７ 導電部材 DESCRIPTION OF SYMBOLS 1 Substrate 2 Electrode pad 3 IC chip 4 Electrode pad 5 Electric connection member 6 Height regulation member 7 Conductive member
Claims (1)
た電気接続部材と高さ規制部材とを設け、前記ＩＣチッ
プに設けられた電気接続部材を基板上の電極パッド上に
位置決め搭載し、前記ＩＣチップに設けられた高さ規制
部材でＩＣチップの高さ制御を行い、前記電気接続部材
の加熱接続を行ってＩＣチップの電極パッドと基板の電
極パッドとを接続することを特徴とするフリップチップ
実装方法。An IC chip includes an electric connection member provided on an electrode pad and a height regulating member. The electric connection member provided on the IC chip is positioned and mounted on an electrode pad on a substrate. The height of the IC chip is controlled by a height regulating member provided on the IC chip, and the electrode connection of the IC chip is connected to the electrode pad of the substrate by heating and connecting the electric connection member. Flip chip mounting method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11188939A JP2001015552A (en) | 1999-07-02 | 1999-07-02 | Flip-chip mounting method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11188939A JP2001015552A (en) | 1999-07-02 | 1999-07-02 | Flip-chip mounting method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2001015552A true JP2001015552A (en) | 2001-01-19 |
Family
ID=16232557
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11188939A Pending JP2001015552A (en) | 1999-07-02 | 1999-07-02 | Flip-chip mounting method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2001015552A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103887191A (en) * | 2012-12-20 | 2014-06-25 | 新科金朋有限公司 | Semiconductor device and method of making bumpless flipchip interconnect structures |
| WO2019008816A1 (en) * | 2017-07-06 | 2019-01-10 | 株式会社フジクラ | Substrate module, and method for producing substrate module |
| CN113594119A (en) * | 2021-06-25 | 2021-11-02 | 苏州汉天下电子有限公司 | Semiconductor package and method of manufacturing the same |
| CN114005930A (en) * | 2021-10-19 | 2022-02-01 | 北京量子信息科学研究院 | Superconducting quantum chip and flip chip pitch control method |
| CN114023733A (en) * | 2021-11-03 | 2022-02-08 | 材料科学姑苏实验室 | Three-dimensional packaging structure and packaging method of superconducting quantum chip |
-
1999
- 1999-07-02 JP JP11188939A patent/JP2001015552A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103887191A (en) * | 2012-12-20 | 2014-06-25 | 新科金朋有限公司 | Semiconductor device and method of making bumpless flipchip interconnect structures |
| WO2019008816A1 (en) * | 2017-07-06 | 2019-01-10 | 株式会社フジクラ | Substrate module, and method for producing substrate module |
| EP3629367A4 (en) * | 2017-07-06 | 2020-10-14 | Fujikura Ltd. | Substrate module, and method for producing substrate module |
| CN113594119A (en) * | 2021-06-25 | 2021-11-02 | 苏州汉天下电子有限公司 | Semiconductor package and method of manufacturing the same |
| CN113594119B (en) * | 2021-06-25 | 2024-05-14 | 苏州汉天下电子有限公司 | Semiconductor package and method of manufacturing the same |
| CN114005930A (en) * | 2021-10-19 | 2022-02-01 | 北京量子信息科学研究院 | Superconducting quantum chip and flip chip pitch control method |
| CN114023733A (en) * | 2021-11-03 | 2022-02-08 | 材料科学姑苏实验室 | Three-dimensional packaging structure and packaging method of superconducting quantum chip |
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