JP2001013926A - Control circuit of display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make various control methods of various numbers of pixels correspond to an LCD, by making video signals corresponding to two adjoining areas to be outputted from one of the two memory parts in order of input, and from the other in reverse order of input. SOLUTION: A 1st- and a 2nd memory parts 2, 3 have respective write line memories 2a, 3a at 1st write devices and respective read line memories 2b, 3b as 2nd storage devices to/from which the data of the write line memory are inputted in parallel and outputted serially. Each of the read line memories has an Out4. The Out4 is an output terminal for outputting from a 1st address of the read line memory. Contrary to Out1-Out3, the outputs from Out4 are serially outputted in the reverse order from the 1st address. And, selectors 8a, 8b select any output terminal of the Out1-Out4, and when the selectors select Out4, a data line selector selects pixels in the reverse order.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control circuit for a display device, such as a liquid crystal display (LCD), which controls each pixel based on a digital video signal to perform display. More particularly, the present invention relates to a control circuit of a display device that performs display by dividing a digital video signal into multiple phases in the horizontal direction.

[0002]

2. Description of the Related Art A control circuit of an active matrix LCD will be described below as an example of a conventional display device.
FIG. 12 is a block diagram of a conventional LCD and its driving circuit. A conventional driving circuit includes a driver 101 to which a video signal is input, a plurality of data lines 102 extending in a vertical direction, a plurality of gate lines 103 extending in a horizontal direction, and a data line 102.
A data line selector 104 for sequentially selecting one of the
One of the gate lines 103 is sequentially selected, and a gate driver 105 for applying a gate voltage thereto and a data line 10
The pixel electrode 107 formed together with a thin film transistor (TFT) 106, a common line 108 connected to a driver 101, and a TFT 109 whose gate is connected to a data line selector 104 are provided at lattice points of the gate line 103 and a gate line 103. are doing.

A video signal, which is a digital signal, is input to the driver 101 from the outside, and is temporarily stored (buffered) and is applied to the pixel electrode of each pixel by performing digital-to-analog conversion (DA conversion). Pixel voltages to be sequentially output. The gate driver 105 selects one gate line 103 every horizontal scanning period, applies a gate voltage, and turns on the TFTs 106 in that row. The data line selector 104 selects one of the plurality of connected TFTs 109, activates one of the data lines 102, and applies a pixel voltage to the data line 104. As a result, a pixel voltage is applied to the pixel electrode connected thereto via the TFT 106 at the intersection of the selected data line 102 and gate line 103. When the shift clock goes high, the data line selector 104 selects the next data line 102 and applies a pixel voltage to this. Similarly, the data line selector 104 sequentially selects the data line from the left end during one horizontal scanning period, and selects the next pixel each time the shift clock goes high.
Sequentially outputs the pixel voltages applied to the respective pixels.

[0004] With the recent increase in the number of display pixels and higher definition of LCDs, the number of pixels that must be written during one horizontal scanning period has increased. For example, the number of pixels in the horizontal direction is 640 in VGA, but
It is twice as large as 80 pixels. At this time, if the number of vertical lines is the same, the length of one horizontal period does not change. Therefore, as the number of pixels increases, the frequency of the shift clock increases, and the time required to apply a voltage to each pixel decreases. I do. Further, as the number of vertical lines increases, one horizontal period itself is shortened. However, the operation speed of the driver 101 has an upper limit, and the response speed of the liquid crystal also has an upper limit.

On the other hand, a control method has been proposed in which a video signal for one row is divided into a plurality of video signals and a voltage is applied in parallel to a plurality of pixel electrodes. Hereinafter, a control method for dividing a video signal into two phases will be described as an example.

FIG. 13 is a block diagram of a control circuit of an LCD divided into two phases. This control circuit has a multiplexer 121 and a two-stage driver 122, and differs from the control circuit in FIG. 12 in that a data line selector 123 is configured to select two data lines at a time.

A video signal input from the outside is alternately divided into two phases for each pixel by a multiplexer 121 and input to a two-stage driver 122. Two-stage driver 122
Simultaneously processes data for two pixels and outputs pixel voltages for two pixels. The data line selector 123 is connected to the adjacent TF
T109 is simultaneously selected, two adjacent data lines 102 are simultaneously activated, and two pixel voltages are simultaneously applied. For example, the data line selector 123 first selects the first and second data lines. Two-stage driver 1
Reference numeral 22 outputs the pixel voltages of the first and second columns, and the pixel voltage is applied to this pixel electrode. Next, after two cycles of the shift clock, the data line selector 123 simultaneously selects the data lines of the third and fourth columns, and the second-stage driver 122 outputs the pixel voltages of the third and fourth columns. Hereinafter, a voltage is applied for each two pixels in the same manner. In this way, by simultaneously applying and controlling the voltage to the plurality of pixel electrodes, the pixel voltage can be continuously applied for the plurality of cycles of the shift clock, and the pixel voltage application time is sufficiently secured even when the number of pixels increases. can do.

Further, a control method has been proposed in which a display area is divided into several parts in the horizontal direction and a voltage is applied to a plurality of pixels in parallel. Hereinafter, as an example of this, the display area is set to horizontal 2
A control method for division will be described.

FIG. 14 is a block diagram of a control circuit of an LCD divided into two horizontal areas. This control circuit differs from the control circuit in FIG. 12 in that a multiplexer 131, a memory unit 132, and a two-stage driver 133 are provided, and a data line selector 134 is configured to select two data lines at a time.

[0010] An image signal for one line input from the outside is:
The signal is input to the multiplexer 131. Multiplexer 1
Numeral 31 outputs the first half of the video signal, that is, the data of the left half of the screen, to the memory unit 132, and the memory unit 132 temporarily stores this. The memory unit 132 outputs the first half data to the two-stage driver 133 in synchronization with the second half data, that is, the data on the right half of the screen. Two-stage driver 133
Outputs pixel voltages V1 and V2 based on the first half and second half data, respectively.

The data line selector 134 has a data line 135
Are simultaneously selected, and two pixel voltages are simultaneously applied. For example, first, the data line selector 123 selects the first data line in the first column and the right half, for example, the data line 134a in the 401st column in the case of an LCD having 800 pixels horizontally. The two-stage driver 122 outputs pixel voltages of the first column and the 401st column, and the pixel voltage is applied to this pixel electrode. Next, the data line selector 134 simultaneously selects the data lines of the second and 402 columns, and the second-stage driver 133 outputs the pixel voltages of the second and 402 columns. Hereinafter, similarly, 2
Voltage is applied to each pixel. With this control method,
Similarly, by simultaneously applying and controlling voltages to a plurality of pixel electrodes, the pixel voltage can be continuously applied for a plurality of cycles of the shift clock, and a sufficient pixel voltage application time can be secured even when the number of pixels increases. Can be.

Thus, the video signal is divided into polyphases,
By applying pixel voltage to multiple pixels simultaneously,
Even if the number of pixels increases, the application time of the pixel voltage can be secured.

[0013]

In order to cope with various driving methods and display devices having various numbers of pixels as described above, separate control circuits are manufactured. However, when a different control circuit is produced for each driving method and each pixel number, the production amount of each type of control circuit is reduced, resulting in a problem that the manufacturing cost of each control circuit is increased.

An object of the present invention is to provide a control circuit for driving an LCD which is divided into a plurality of horizontal areas as described above, and which is efficient and versatile. I do.

[0015]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems. A digital video signal is inputted, the digital video signal is divided into a predetermined number, and an area to be displayed is horizontally arranged based on the digital video signal. A control circuit that divides a digital video signal according to a predetermined rule, a plurality of memory units each storing the divided digital video signal, and a control unit that divides the digital video signal according to a predetermined rule. A driver for converting an output to output a control signal of the display device, wherein the memory unit has a predetermined number of words of write line memory into which the divided digital video signals are serially input; Is connected to a read line memory having the same number of words as the write line memory transferred in parallel, and a predetermined address of the read line memory. In each of the two memory units, a divided digital video signal of a different part is input to each memory unit, and a divided digital video signal of an adjacent part is input to each memory unit. The read line memory of the memory unit outputs the digital video signal input first to the memory unit in the order of input, and the read line memory of the other memory unit traces back from the digital video signal last input to the memory unit. And a control circuit of the display device for sequentially outputting the data.

Each of the read line memories has an output terminal at an address at which the first input video signal is stored and an output terminal at an address at which the last input video signal is stored. And a selector for selecting one of the output terminals.

The display area controlled by the output of the readout line memory which outputs in the input order performs a normal scan,
The display area controlled by the output of the read-out line memory that sequentially outputs the data in the backward direction performs reverse scanning.

When a mirror image signal is input to the selector, the selector performs a mirror image display by changing the selection order of the memory unit.

[0019]

First, as a first embodiment, a control circuit for controlling an SVGA panel of 800 pixels horizontally by two horizontal phases divided into a single phase and a total of two phases will be described. FIGS. 1A and 1B are block diagrams of a control circuit for performing horizontal two-region two-phase division. The control circuit according to the present embodiment applies the input signal to the first half and the second half of the horizontal scanning period.
A first multiplexer 1 as a dividing unit for dividing, a first memory unit 2 to which a first half signal is inputted, a second memory unit 3 to which a second half signal is inputted, and a first and a second memory unit A second multiplexer 4 for integrating and outputting the outputs, two signals are inputted at the same time, a buffer is provided, and a two-stage driver 5 for performing digital-to-analog conversion is provided.

The first and second memory sections 2 and 3 are respectively serially input write line memories 2a and 3a as first storage devices, and write line memory data is input in parallel and serially output. And read line memories 2b and 3b as second storage devices.

When the video signal is input to the multiplexer 1, the multiplexer 1 outputs the signal of the first half of each horizontal scanning period, ie, 400 pixels displayed in the first area of the left half of the screen, of the video signal for one row. The video signals are sequentially output to the write line memory 2a of the first memory unit 2. The write line memory is a line memory having a capacity of 400 words, and an input signal is first written to the first address. In this specification, a line memory also refers to a predetermined number of storage areas arranged in series. Then, when the next signal is input, the signal written to the first address is transferred to the adjacent second address, and the next signal is written to the first address instead. Similarly, every time a new signal is input, the stored signal is transferred to the next numbered address and serially input. When a video signal for 400 pixels is input, the entire storage area of the write line memory 2a is written. Next, a signal in the latter half of the horizontal scanning period, that is, a video signal for 400 pixels displayed in the second area in the right half of the screen, starts to be input to the multiplexer 1, and the multiplexer 1 converts the signal into the second memory unit 3. Are sequentially output to the write line memory 3a. When signals for 400 pixels are input to the write line memories 2a and 3a, respectively, and the signals are input up to the 400th address, the write line memories 2a and 3a read out all the stored contents and read in parallel to the line memories 2b and 3b. Transfer to The read line memory 2b has the same number of words (400 words in this embodiment) as the write line memory 2a, and each address of the write line memory 2a is connected to the same numbered address of the read line memory 2b. Each address is transferred simultaneously. This transfer is performed during the horizontal blanking period, and after the transfer is completed, when the video signal of the next row starts to be input to the multiplexer 1, the same processing is repeated.

On the other hand, the data stored in the read line memories 2b and 3b is such that the data of the 400th address is output from the output terminals of A-Out1 and B-Out1 to the multiplexer 4.
And is serially input to the two-stage driver 5.
Out-1 (here, Out-1 is a generic term for A-Out1 and B-Out1) is an output terminal connected to 400 addresses. The driver is a circuit that generates a control signal for the display device based on data output from the memory unit. Fortieth
By outputting the data of the 0 address, the data of the first to 399th addresses are transferred one by one to the next numbered address. The two-stage driver 5 buffers the data for two pixels and performs digital-to-analog conversion, etc.
A voltage V1 according to the output of A-Out1 and a voltage V2 according to the output of B-Out1 are output to the selected pixel electrode as control signals.

FIG. 2 shows an LCD having two horizontal areas and two phases. The data line selector 11 is a selector that sets two of the 800 output terminals to high and simultaneously selects two of the data lines 12 extending in the vertical direction. The gate driver 13 selects one of the plurality of gate lines 14,
This is a driver that applies a gate voltage to this. Now, it is assumed that the gate line 14a and the data lines 12a and 12A are selected. Now, V1 and V2 are data stored at the first address of each line memory. The output V1 of the control circuit in FIG. 1 is applied to the pixels in the first column (hereinafter, the pixel in the nth column may be referred to as a pixel n) via a data line 12a, and another output V2 is applied to the data line 12a. 12A
Is applied to the pixel 401 via the.

Next, after two cycles of the shift clock, the data of the 400th address of the read line memories 2b and 3b is read again and input to the driver 5. At this time
The data written at address 0 is the data written at address 399 immediately after the parallel transfer. Then, by reading the data at the 400th address, one data at the second to 399th addresses is transferred. V1 and V2 are output from the driver 5 again based on the output data of the 400th address. In FIG. 2, after two cycles of the shift clock, the data line selector 11 switches and selects the data lines 12b and 12B. As a result, a voltage is applied to the pixels on the second and 402 columns.

Similarly, in the third and 403rd columns,
The voltage is applied as in the column and the 404th column. When the voltage is applied to the pixels in the 400th and 800th columns, the voltage application in one row is completed. Thereafter, a horizontal synchronization signal is output, and the gate driver selects the gate line 14b in the next row and continues writing.

Next, the role of the memory units 2 and 3 in the first embodiment will be described. The video signal is continuously
Is input to the control circuit. This is temporarily stored in the memory units 2 and 3 in order to divide the screen into two right and left areas and temporarily store the data in the memory units 2 and 3 so that the data to be applied to the pixels in the first column and the pixels in the 401st column can be simultaneously transmitted to the driver 5 can be output. In addition, since data is input serially to the write line memory and transferred in parallel to the read line memory, data can be written without delay.

Next, the read operation from the read line memories 2b and 3b will be described more specifically with reference to the timing chart of FIG. First, until the timing A, the write line memories 2a, 3a to the read line memories 2b,
It is assumed that the parallel transfer to 3b has been completed and the pixel data for one horizontal line has been stored in the readout line memories 2b and 3b. When the shift clock goes high at the timing A, the 2b read clock input to the read line memory 2b goes high. Then, the read line memory 2b outputs the data of the pixel 1. At this time, the memory selection signal is high, the multiplexer 4 in FIG. 1 has selected the output of the read line memory 2b, and the data of the pixel 1 is output from the multiplexer 4. Next, at the timing B when the once-low shift clock goes high again, the 3b read clock input to the read line memory 3b goes high.
Then, the read line memory 3b outputs the data of the pixel 401. The memory selection signal is low at timing B, and the multiplexer 4 reads the read line memory 3
b, and outputs this data. Next, at timing C when the shift clock, which once becomes low, becomes high again, the 2b read clock becomes high, and similarly, the data of the pixel 2 is output from the multiplexer 4. The pixel 1 is used as the control voltage V1 and the pixel 401 is used as the control voltage V2.
Is output from the driver 5. V
The outputs of 1, V2 are continuously output for two cycles of the shift clock. Hereinafter, as shown in FIG. 3, the read operation similarly continues.

Next, a description will be given of a control circuit for controlling a UXGA panel having 1600 pixels in the horizontal direction by dividing the UXGA panel into four horizontal regions and a single phase, that is, a total of four phases. FIG.
FIGS. 4A and 4B are block diagrams of a control circuit for performing a horizontal four-region four-phase division. A first multiplexer 21 for dividing the video signal into four, first to fourth memory units 22, 23, 24 to which the divided video signals are respectively input;
25, a second multiplexer 26 that integrates and outputs the outputs of the respective memory units, a buffer for this, and a four-stage driver 27 that performs digital-to-analog conversion. Each memory unit has the same configuration as the memory units 2 and 3 in FIG.

When a video signal is input, the multiplexer 2
1 stores the video signal of the first 400 pixels, that is, the video signal of the first area on the left 1/4 of the screen in the first memory unit 22, and the video signal of the next 400 pixels, that is, the video signal of the second area on the center left of the screen. The second memory unit 23 stores the next 400 pixels, that is, the video signal of the third region on the right side of the center of the screen, in the third memory unit 24. Are divided and output to the fourth memory unit 25, respectively.
Each write line memory 22a, 23a, 24a, 25
a are serially input to the respective line memories 22b, 23b, and 24 during the horizontal blanking period.
b and 25b. The data of each first address is sequentially output from the output terminals A-Out, B-Out, C-Out, and D-Out to the multiplexer 26 and serially input to the four-stage driver 27. The four-stage driver 27 buffers the data for four pixels, performs digital-to-analog conversion, and applies voltages V1, V2, V3, and V applied to the pixel electrodes.
4 is output.

FIG. 5 shows an LCD having four horizontal areas and four phases. The data line selector 15 is a selector for simultaneously selecting four out of 1600 data lines. The gate driver 13 is a driver that selects one of the gate lines 14 and applies a gate voltage thereto. Now, assume that the gate line 14a and the four data lines 12a are selected. The pixel voltage V1, which is a control signal output by the control circuit of FIG. 1, is applied to the pixel in the first column via the data line 12a, the output V2 is applied to the pixel in the 401st column, V3 is applied to the pixel in the 801st column, and V4 is applied to the pixel in the 801st column. Is applied to the pixels in the 1201st column.

Next, the multiplexer 26 shown in FIG. 4 again reads the read line memories 22b, 23b, 24b and 25b.
Of the 400th address (the data written to the 399th address immediately after the parallel transfer) is read out and input to the four-stage driver 27. In FIG. 5, the data line selector 15 switches and selects four data lines 12b after four cycles of the shift clock. Thus, a voltage is applied to the pixel 2, the pixel 402, the pixel 802, and the pixel 1202.

In the same manner, a voltage is applied, and when a voltage is applied to the pixel 400, the pixel 800, the pixel 1200, and the pixel 1600, the voltage application for one row is completed. afterwards,
The horizontal synchronization signal is output, and the gate driver selects the next gate line 14b and continues writing.

Next, as a third embodiment, an SVGA panel of 800 pixels horizontally is divided into three phases in two horizontal areas, for a total of 6 pixels.
A control circuit that performs control by phase division will be described. FIG.
FIGS. 1A and 1C are block diagrams of a control circuit for performing horizontal two-region six-phase division. The method of outputting data from the read line memory and the point of having the six-stage driver 7 are different from the first embodiment.

When the video signal is input to the multiplexer 1, the write line memory 3a in the first half of the horizontal scanning period is stored in the write line memory 2a in the same manner as in the first embodiment.
The video signals of the latter half are respectively stored in a, and are respectively transferred in parallel to the readout line memories 2b and 3b.
The multiplexer 6 is connected to the first line memory 2b of the read line memory 2b.
, The data of the third address is read serially, and then the data of the first to third addresses of the read line memory 3 b are read serially and output to the six-stage driver 7. The six-stage driver 7 generates and outputs pixel voltages V1 to V6 based on the input data for the six pixels.

FIG. 6 shows an LCD having two horizontal areas and six phases. The data line selector 16 is a selector for simultaneously selecting six of the 800 data lines. The gate driver 13 is a driver that selects one of the plurality of gate lines 14 and applies a gate voltage thereto. now,
It is assumed that six data lines connected to the gate line 14a and the output terminals 12a and 12A are selected. FIG. 1 (c)
V1, V2, and V3 output by the control circuit of FIG.
5, V6 are 401, 402, 4 via data line 12A.
It is applied to the pixels in the 03rd column.

Next, the multiplexer 6 shown in FIG.
The data of the first to third addresses (data written to the fourth to sixth addresses immediately after the parallel transfer) of the read line memories 2b and 3b are read again, input to the six-stage driver 7, and based on this. V1 to V6 are output from the driver 7 again. In FIG. 6, the data line selector is
After six cycles of the shift clock, the data lines 12b and 12B
Is switched to and selected. Thus, 4, 5, 6
A voltage is applied to the pixels in the columns 404, 405, and 406.

Thereafter, a voltage is applied in the same manner, and 400
When the voltage is applied to the pixels in the column and the 800th column, the voltage application in one row is completed. Thereafter, a horizontal synchronization signal is output, and the gate driver selects the next gate line 14b and continues writing.

Next, the read operation from the read line memories 2b and 3b will be described more specifically with reference to the timing chart of FIG. First, until the timing A, the write line memories 2a, 3a to the read line memories 2b,
It is assumed that the parallel transfer to 3b has been completed and the pixel data for one horizontal line has been stored in the readout line memories 2b and 3b. When the shift clock goes high at timings A, B, and C, the read line memory 2b
The 2b read clock input to the clock signal goes high in synchronization with this. Then, the read line memory 2b sequentially outputs data of the pixels 1, 2, and 3. During this time, the memory selection signal is continuously high, the multiplexer 6 in FIG. 1C selects the output of the readout line memory 2b, and the data of the pixels 1, 2, and 3 is sequentially output from the multiplexer 6. Is output. Next, at timings D, E, and F when the shift clock goes high, the 3b read clock input to the read line memory 3b goes high in synchronization with the timing. Then, the read line memory 3b stores the pixel 40
The data of 1, 402 and 403 are output. During this time, the memory selection signal is continuously low, and the multiplexer 6 selects the read line memory 3b and outputs this data. Next, at timing G, the 2b read clock goes high, and the data of the pixel 4 is similarly output from the multiplexer 6. Although not shown, the control voltages V1, V2, V3, V4,
Pixels 1, 2, 3, 401, 402, and 4 as V5 and V6
The voltage corresponding to the data 03 is output from the driver 7. Outputs of V1 to V6 are continuously output for six cycles of the shift clock. Hereinafter, the read operation is similarly continued.

Incidentally, the number of horizontal pixels of the LCD may be different from that described above, such as a 640 horizontal VGA pixel and a 1024 horizontal XGA pixel. In order to control an LCD having a different number of pixels for each of these, the number of words (total number of addresses) of the write and read line memories may be formed in accordance with the number of pixels. That is, if the VGA is controlled to be divided into two horizontal areas, the number of words in the line memory is １ ／ that of 320 words, X
If the control is divided into four horizontal areas by GA, 1 /
4 and 256 words.

However, when a control circuit is formed for each LCD having a different number of pixels, the production amount of each control circuit decreases, and the manufacturing cost of each control circuit increases. If the control circuit is provided with versatility and can be controlled using the same control circuit for LCDs having different numbers of pixels, the production amount of the control circuit increases and the manufacturing cost can be reduced.

For this purpose, the read-out line memory of FIG. 1 has second and third output terminals Out2 and Out3, respectively. (Here, for example, Out1 is a general term for A-Out1 and B-Out1.) The output terminals of Out1 to Out3 serially output data of addresses with numbers smaller than the addresses to which the output terminals are connected. Then, as shown in FIG. 1D, the multiplexer 4 and the read line memories 2b, 3b
b, selectors 8a and 8b are provided, and one of the output terminals is selected and activated. The multiplexer integrates the incoming data, and the driver
The number of drivers is six, six, or other.
Before being incorporated in the LCD, the selectors 8a and 8b are set so as to select any one output terminal in accordance with the number of pixels of the incorporated LCD and the control method.

The first output terminal Out1 is an output terminal used as an output terminal in the above-described embodiment, and is an output terminal when all 400 words of the line memories 2b and 3b are used. The output terminal Out1 is used when the SVGA of 800 pixels in the horizontal direction is divided into two horizontal areas as in the first embodiment, or when the UXGA of 1600 pixels in the horizontal direction is divided into four horizontal areas as in the second embodiment. .

The second output terminal Out2 outputs from the 320th address of the line memory. That is, the number of words of the line memory used in this case is 320 words,
The memory area from address 1 to address 400 is not used. The output terminal Out2 is used when dividing a VGA with 640 pixels horizontally into two regions or when dividing an SXGA with 1280 pixels horizontally into four regions.

The third output terminal Out3 outputs from the 256th address of the line memory. That is, the number of words of the line memory used in this case is 256 words,
The memory area from address 57 to address 400 is not used. When the XGA of 1024 pixels in the horizontal direction is divided into four horizontal areas, the output terminal Out3 is used.

The position of the output terminal is not limited to the above example. For example, if an 800-pixel SVGA is divided into four horizontal areas, the required number of words is 200 words. In this case, an output terminal is provided at the 200th address. In addition, output terminals may be provided at all addresses where it is considered necessary.

The total number of words in the line memory is 400
It is not limited to words. For example, when the XGA is divided into two horizontal areas, the total number of words of the line memory needs to be 512 words. For this purpose, a line memory having a total number of words of 512 words is required. Then, a plurality of similar output terminals may be provided on the way.

The position where the output terminal is provided may be connected to an arbitrary address if necessary.
/ 4 and 1/2 of VGA are the same 320, and UX
１ ／ of GA and の of SVGA are the same 400. Further, when processing a video signal with a computer or the like, 256 pixels are one standard. That is, the standard of the current display device is often a multiple of 256, 320, or 400, and it is considered that this will be followed in the future. Therefore, by providing an output terminal at an address having a sufficient number of words capable of storing data for 256, 320, and 400 pixels, the possibility of supporting a display device with various numbers of horizontal pixels is increased. Control circuit with a high level of performance. This is the significance of setting the number of words of the line memory to 400 in this specification. That is, if 400 words are set as the number of words of the line memory, any of the above-described 256, 320, and 400 pixels can be flexibly handled. Also, 2
In many cases, the number of pixels is set in units of 56 times and 512 pixels. Therefore, if the number of words in the line memory is, for example, 512, it can correspond to any of the numbers of pixels described above. However, it goes without saying that increasing the number of words increases the circuit area accordingly, so it is better to keep the number of words in the line memory to the minimum necessary.

Instead of providing the selectors 8a and 8b, unnecessary output terminals may be destroyed by laser irradiation or the like.

By the way, as shown in FIG. 8A, when the image is divided into two horizontal regions, voltages are applied sequentially from the leftmost pixel. (Hereinafter, the direction of scanning from left to right is referred to as forward scan, and right to left is referred to as reverse scan.) When forward scanning is performed in two regions, the left region ends at the center pixel of the screen, and conversely, the right region displays the screen. A voltage is first applied to the center pixel. This application time difference causes a brightness difference in the center of the screen,
Deteriorate display quality. 8 (b) and 8 (c).
When the voltage is applied to the center of the screen at the same timing by reverse scanning either the left or right area as shown in
This luminance difference does not appear.

For this purpose, each of the readout line memories of FIG. 1A has Out4. Out4 is an output terminal that outputs from the first address of the read line memory. The output from Out4 is serially output in reverse order from the first address, contrary to Out1 to Out3. Then, the selectors 8a and 8b in FIG. 1D select one of the output terminals Out1 to Out4. Selector 8a, 8b is Out4
Is selected, the data line selector selects pixels in reverse order.

An example of the control of a three-phase, six-phase divided LCD in two horizontal areas will be described with reference to FIGS. 1 (a), (d) and FIG.
Now, it is assumed that the selector 8a selects A-Out1 and the selector 8b selects B-Out4. When the video signal is input to the multiplexer 1, the first half of the video signal is stored in the write line memory 2a and the second half of the video signal is stored in the write line memory 3a, and transferred to the read line memories 2b and 3b, respectively, as in the first embodiment. Is done. Multiplexer 9
Are read line memories 2b, 3b to 3
Each pixel data is read. Here, the 400th, 399th, and 398th address data are read from the read line memory 2b, and the first, second, and third data are read from the read line memory 3b. Based on these data, the driver 10 sequentially operates V1 to V1.
A pixel voltage of V6 is generated and output to the LCD of FIG. The data line selector 16 'includes left and right ends 12a, 12a.
Six data lines connected to A are selected. Thus, V1, V2, and V3 generated from the data at the 400th, 399th, and 398th addresses of the read line memory 2b via the three data lines connected to 12a.
Is applied to the pixel electrodes in the first, second, and third columns, respectively.
In addition, V6, V5, and V4 generated from the data of the first, second, and third addresses of the read line memory 3b via three data lines connected to 12A are stored in columns 800, 799, and 798, respectively. It is applied to the pixel electrode of the eye.

After six cycles of the shift clock, the 400th, 399, and 398th of the read line memory 2b are again read.
The data at the address (397 immediately after the parallel transfer,
396, 395th address) and the data of the first, second, and third addresses (4th, 5th, and 6th addresses) of the read line memory 3b are read, and the pixel voltage generated based on these is 4, 5, 6, 897, 896, 895 via six data lines connected to 12b and 12B.
It is applied to the pixel electrode in the column.

The display control shown in FIG. 8C can be performed by repeating the same operation.

The display control shown in FIG. 8B can be performed in substantially the same manner as shown in FIG. 1D if the selector 8a selects A-Out4 and the selector 8b selects B-Out1.

Next, referring to the timing chart of FIG. 10, the read line memories 2b and 3b for performing the reverse scan will be described.
The operation of reading from will be described more specifically. First, by timing A, it is assumed that the parallel transfer from the write line memories 2a, 3a to the read line memories 2b, 3b is completed, and that pixel data for one horizontal line is stored in the read line memories 2b, 3b. I do.
When the shift clock goes high at the timings A, B, and C, the 2b read clock input to the read line memory 2b goes high in synchronization with the shift clock. Then, the read line memory 2b stores the pixel 1,
A few data are sequentially output. During this time, the memory selection signal is continuously high, the multiplexer 9 in FIG. 1D selects the output of the read line memory 2b, and the data of the pixels 1, 2, and 3 is sequentially output from the multiplexer 9. Is output. Next, at timings D, E, and F, the 3b read clock input to the read line memory 3b goes high in synchronization with the read clock. Then, the read line memory 3b stores the pixel 80
0, 799 and 798 are output. During this time, the memory selection signal is continuously low, and the multiplexer 6 selects the read line memory 3b and outputs this data. Next, at timing G, the 2b read clock goes high, and the data of the pixel 4 is similarly output from the multiplexer 6. Although not shown, the control voltages V1, V2, V3, V4,
Pixels 1, 2, 3, 800, 799, 7 as V5 and V6
A voltage corresponding to the data 98 is output from the driver 7. Outputs of V1 to V6 are continuously output for six cycles of the shift clock. Hereinafter, the read operation is similarly continued.

The point of this embodiment is that it is possible to control the LCD for performing the reverse scan by only changing the selection of the selectors 8a and 8b without largely changing the control circuit. Therefore, the same control circuit can be used for the LCD that performs the reverse scan and the LCD that does not perform the reverse scan, and the manufacturing cost can be suppressed.

Incidentally, an electronic view finder (EV) such as a digital video camera is used.
In the case of F) or the like, there is a type in which the EVF can be inverted and the display area of the EVF can be turned to the photographing lens side in order to photograph the photographer himself. The display of the EVF at this time is mainly a mirror image in which the left and right are inverted. According to the LCD control circuit of the present invention shown in FIGS. 1 (a) and 1 (d),
Such a mirror image display can be supported. Hereinafter, the control operation of the mirror image display will be described.

When the video signal is input to the multiplexer 1, the first half video signal is stored in the write line memory 2a and the second half video signal is stored in the write line memory 3a in the same manner as in the first embodiment.
3b. Now, the selector 8a selects A-Out1 and the selector 8b selects B-Out4. The multiplexer 9 reads the output of the selector 8b first, and then reads the output of the selector 8a. Therefore, the data
400th, 399, 398 of the read line memory 2b
Address data, the first of the read line memory 3b,
Data is read out in the order of a few addresses. And
Based on these data, pixel voltages V1 to V6 are generated in order. This is applied to the LCD of FIG. First, six data lines 12a and 12A are selected in the same manner as described above. The first, second, third, 798, 799, and 800th column pixel electrodes are sequentially provided with data of the 400th, 399, and 398th addresses of the readout line memory 2b,
A pixel voltage generated based on the data of the third, second, and first addresses of the read line memory 3b is applied.

Next, the fourth, fifth, sixth, 797, 796, and 79 are connected via six data lines connected to 12b and 12B.
The data of the 400th, 399, and 398th addresses (397, 396, and 395 addresses immediately after the parallel transfer) of the readout line memory 2b and the third, second, and first addresses of the readout line memory 3b (the 6th address) are sequentially applied to the pixel electrodes in the fifth column. , 5,
(4 addresses) are applied. The mirror image display can be controlled by applying the voltage in the same manner.

For switching between the normal display and the mirror image display, for example, an output circuit for outputting a mirror image signal for displaying a mirror image when the EVF is rotated is provided, and the operation of the control circuit is also switched accordingly. Keep it.

Next, the operation of reading from the read line memories 2b and 3b when a mirror image is displayed will be described more specifically with reference to the timing chart of FIG. The difference from the timing chart of FIG. 10 is that the read clocks 2b and 3b are switched and the phase of the memory selection signal is reversed. First, up to timing A, the parallel transfer from the write line memories 2a, 3a to the read line memories 2b, 3b has been completed.
Assume that pixel data for one horizontal line is stored in all of b and 3b. When the shift clock goes low at the timings A, B, and C, the 3b read clock input to the read line memory 3b goes high in synchronization with the shift clock. Then, the read line memory 3b sequentially outputs data of the pixels 800, 799, and 798. During this time, the memory selection signal is continuously low, the multiplexer 9 in FIG. 1D selects the output of the readout line memory 3b, and the multiplexer 9 sequentially outputs data of the pixels 800, 799, and 798. Is output. Next, at timings D, E, and F, the 2b read clock input to the read line memory 2b goes high in synchronization with the read clock. Then, the read line memory 2b outputs the data of the pixels 1, 2, and 3. During this time, the memory selection signal is continuously high, and the multiplexer 9 selects the read line memory 2b and outputs this data. Next, at timing G, the 3b read clock goes high, and the data of the pixel 797 is similarly output from the multiplexer 9. Although not shown, from timing G, the control voltages V1, V2, V3, V4, V5, and V6 are set to the pixels 8
The voltage corresponding to the data of 00, 799, 798, 1, 2, and 3 is output from the driver 10. Outputs of V1 to V6 are continuously output for six cycles of the shift clock. Hereinafter, the read operation is similarly continued.

The above description is provided for easy understanding.
Although described separately for each driving method, by using a single control circuit implemented by combining each driving method, one pixel can be used for any display method with various pixel numbers, reverse scan, and mirror image display. This can be handled by a control circuit. That is, for example, the control circuit of FIG. 1B omits the selectors 8a and 8b, and the driver 5
This is a multi-stage driver 10 that does not use terminals at and after the stage.

Although the above description has been made with reference to a monochrome display device for easy understanding, it is of course applicable to a color display device. In this case, as many memory units as the product of the number of divided areas and the number of primary colors for color display are required. For example, when there is data of three colors of RGB and the image is divided and displayed in two horizontal areas, two sets of memory units are required for three colors, that is, a total of six sets of memory units are required.

In the above embodiment, an LCD is used as an example of the display device. However, the present invention is not limited to this.
For example, in the case of a display device using an organic EL (Electro Luminescence) element, the control signal is not “the voltage V1 applied to each pixel electrode” but “the voltage applied to the organic EL element of each pixel”. Cathode ray tube (CRT; Cathode Ray
A display device using (tube) can be read as “electron acceleration voltage” and used as a control circuit of various display devices.

[0065]

As described above, according to the present invention, the first storage device that is serially input and the second storage device that has its storage contents transferred in parallel are provided, and the second storage device is provided. Since it has a memory unit that serially outputs data from a predetermined address of the device, it can correspond to various control methods LCD with various numbers of pixels. Therefore, the manufacturing cost can be kept low.

In the two memory units to which the divided digital video signals of the adjacent portions are input, one is output in the input order and the other is output in the retrospective order, so that a so-called reverse scan or mirror image display is performed. It can also correspond to the display device to be performed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a control circuit of the present invention.

FIG. 2 is a diagram showing a display device for horizontal two-region single-phase display.

FIG. 3 is a timing chart of data output of the control circuit of the present invention.

FIG. 4 is a block diagram showing another embodiment of the present invention.

FIG. 5 is a diagram showing a display device for horizontal four-region single-phase display.

FIG. 6 is a diagram showing a display device for horizontal two-region three-phase display.

FIG. 7 is a timing chart of data output of the control circuit of the present invention.

FIG. 8 is a diagram for explaining reverse scanning.

FIG. 9 is a diagram illustrating a display device that performs reverse scanning.

FIG. 10 is a timing chart of data output of the control circuit of the present invention.

FIG. 11 is a timing chart of data output of the control circuit of the present invention.

FIG. 12 is a diagram showing a conventional active matrix LCD and its control circuit.

FIG. 13 is a diagram showing a conventional two-phase display LCD and its control circuit.

FIG. 14 is a view showing a conventional horizontal two-region single-phase display LCD and its control circuit.

[Explanation of symbols]

1, 4, 6: multiplexer, 2, 3, 22, 23,
24, 25: memory unit 2a, 3a: write line memory, 2b, 3b: read line memory 5, 7, 10: driver

Continued on the front page (72) Inventor Makoto Kitagawa 2-5-5 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. F-term (reference) 5C006 AA01 AF06 BB14 BB16 BC12 BC16 BF05 BF24 FA08 5C058 AA09 BA03 BA06 BA20 BA21 BA25 BB11 5C080 AA10 BB05 DD21 EE17 FF11 GG07 GG08 JJ02 JJ04

Claims (4)

[Claims] 1. A control circuit which receives a digital video signal, divides the digital video signal into a predetermined number, and divides a display area based on the digital video signal into the predetermined number of areas in the horizontal direction to perform control. A dividing unit that divides the digital video signal according to a predetermined rule; a plurality of memory units each storing the divided digital video signal; and a control unit that converts an output of the memory unit and outputs a control signal to the display device. And a driver that outputs the divided digital video signals corresponding to two adjacent areas is input to two of the plurality of memory units, and from one of these two memory units, The digital video signals are output in the order of input,
A control circuit for a display device, wherein the digital video signal is output from the other side in the reverse order of the input order. 2. Each of the read line memories has an output terminal at an address where a first input video signal is stored and an output terminal at an address where a last input video signal is stored, The control circuit according to claim 1, further comprising a selector for selecting one of the plurality of output terminals. 3. The display area controlled by the output of the readout line memory that outputs in the input order performs a normal scan, and the display area controlled by the output of the readout line memory that sequentially outputs the output performs a reverse scan. The control circuit for a display device according to claim 1, wherein: 4. The control of the display device according to claim 2, wherein when a mirror image signal is input to the selector, the selector performs a mirror image display by changing a selection order of the memory unit. circuit.