JP2001007742A - Bidirectional transmission circuit and bus system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily realize impedance matching, and to quicken a signal transmitting speed. SOLUTION: In this circuit, a switch 107 is connected with a resistor 108 side at outputting of an input/output circuit 120, and the switch 107 is connected with a short wire 109 side at inputting of the input/output circuit 120. An impedance between a transceiver and a bidirectional transmission line is change at outputting and inputting, so that impedance matching can be easily realized independently at inputting and outputting.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a bidirectional transmission circuit for inputting and outputting signals to and from a bidirectional transmission line, and a bus system for connecting LSIs.

[0002]

2. Description of the Related Art In recent years, as MPUs and memories have become faster,
There has been an increasing demand for increasing the data transmission speed of the bus, but as the data transmission speed has increased, it has become difficult to reliably transmit data. This is because the influence of signal reflection and crosstalk between adjacent lines caused by mismatching of the characteristic impedance of the transmission line becomes remarkable as the speed increases.

In order to solve this problem, impedance is matched by performing series termination in which a resistor is inserted in series in a transmission line or parallel termination in which a resistor is connected in parallel to a power supply or a GND plane to eliminate signal reflection. Measures are commonly taken. The series termination has a role of matching the output impedance of the output buffer with the impedance of the transmission line and suppressing the output amplitude by inserting a resistor in series between the output buffer (also called a driver) and the transmission line. . In the case of a unidirectional transmission line, it is effective to insert it at the output end of the output buffer to be connected. Here, the unidirectional transmission line refers to a transmission line that transmits a signal in only one direction.

FIG. 1 shows an example of a circuit terminated in series in a unidirectional transmission line. Referring to FIG.
A resistor 804 is inserted in series immediately after the output buffer 801 in order to eliminate the impedance mismatch between 1 and the transmission line 803 connected thereto. Output buffer 80
Assuming that the on-resistance value of No. 1 is Ro1 and the characteristic impedance of the transmission line 803 is Zo, the output buffer side impedance (Rs1 + Ro1) and the transmission line side impedance (Zo) are matched (the relationship of Rs1 + Ro1 = Zo is established). , The value Rs1 of the resistor 804 is Rs
It is determined that 1 = Zo−Ro1. With this resistor 804, the impedance is matched between the output buffer 801 side and the transmission line 803 side from the connection point between the resistor 804 and the transmission line 803.

However, when the series termination as shown in FIG. 1 is applied to a bidirectional transmission line for transmitting signals in both directions, there is a problem because both ends of the transmission line can be output terminals. FIG. 2 shows a circuit in which a resistor is inserted in series at one end of a bidirectional transmission line. If the resistance value Rs1 of the resistor 906 is determined in the same manner as in FIG.
When transmitting a signal from the first side, impedance is matched at a connection point between the output buffer 901 and the bidirectional transmission line 905. However, when transmitting a signal from the output buffer 903 side, there is no series termination resistor for matching the impedance at the connection point between the output buffer 903 and the bidirectional transmission line 905, so that impedance mismatch occurs and reflection occurs. .

In recent years, there has been a method of matching impedance by devising a bus topology and a termination method in a bidirectional transmission line. For example, RSL (Rambus Signaling Logic) shown in FIG. 3 proposed by Rambus in the United States and SST shown in FIG.
L (Stub Series Terminated Logic) [EIAJED-
5512]. Each broken line in FIGS. 3 and 4 shows the combination of an output buffer (driver) and an input buffer (receiver) in detail. The output buffer in the broken line in FIG. 3 is an open drain output, and the output buffer in the broken line in FIG. 4 is a three-state output.

The RSL shown in FIG. 3 is characterized in that a bus topology is limited by adopting a one-stroke structure without a branch line for the bus line, thereby achieving impedance matching. In the case of the SSTL shown in FIG. 4, the bus line is terminated in parallel, and a series termination resistor is arranged at a branch point of the branch line which is not matched, whereby impedance matching between the bus line and the branch line is achieved. ,
Impedance matching is possible even in a bus topology with branch lines.

[0008]

However, in the conventional bus interface, it is difficult to increase the clock frequency to increase the signal transmission speed and to achieve impedance matching. RSL shown in FIG.
In the example of (1), when connecting an LSI on a substrate, the lead line of the LSI package becomes a branch line, so that it is impossible to completely eliminate the branch line and form a one-stroke structure bus line. If the frequency is on the order of 100 MHz, it operates without any problem. However, there is a problem that the effect of reflection cannot be ignored at higher frequencies (on the order of GHz) because there are actually a few mismatched branch lines (lead lines). .

Further, in the case of the SSTL shown in FIG. 4, the function of the series termination disposed at the branch point is to perform impedance matching when a signal is transmitted from the branch line to the bus line (output to the bus line). To measure
In the case where a signal is transmitted from the bus line to the branch line (when input is made from the bus line), impedance matching is not achieved, so that there is a problem that the effect cannot be ignored at a high frequency (GHz order).

An object of the present invention is to provide a bidirectional transmission circuit and a bus system which can easily achieve impedance matching and are suitable for increasing a signal transmission speed.

[0011]

According to the present invention, there is provided a bidirectional transmission circuit comprising: a transceiver for inputting and outputting a signal; a first element having an impedance; a second element serving as a shorting wire;
The first element is used for output of the transceiver, and the second element is used for input of the transceiver.
A switching unit for connecting the element between the transceiver and the bidirectional transmission line.

[0012] The impedance of the first element is a value that matches the combined impedance of the impedance of the first element and the output impedance of the transceiver with the characteristic impedance of the bidirectional transmission line. Here, the first element may be constituted by any one of a resistance element, a driver element for amplifying an output current of the transceiver, and a set of a driver element and a resistance element.

In the bus system according to the present invention, a first LSI serving as a subject of access and a second LSI serving as a subject of access are provided.
A bus system for transmitting addresses and data between the first LSI and a first unidirectional bus for unidirectionally transmitting addresses and write data output from a first LSI to a second LSI, and read data output from a second LSI Is the first LS
A first unidirectional bus for transmitting an address and write data at the time of write access by the first LSI, and a first unidirectional bus at the time of read access by the first LSI. Is configured to transmit a read address, and the second bus is configured to transmit read data.

The main signal lines included in the first unidirectional bus may be alternately wired to the signal lines included in the second unidirectional bus. Furthermore, at least one of the first and second LSIs may be configured such that input terminals and output terminals corresponding to the alternately wired signal lines are alternately arranged.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. <First Embodiment> FIG. 7 shows a configuration of a bidirectional signal transmission circuit according to a first embodiment of the present invention. In the figure, 1
Reference numeral 05 denotes a bidirectional transmission line (characteristic impedance is Zo) for transmitting signals bidirectionally. FIG. 1 shows a portion related to one line in a bidirectional bus such as a data bus connecting IC1 and IC2.

Reference numeral 120 denotes an input / output circuit (also referred to as a transceiver) provided inside the semiconductor element IC1 for inputting / outputting a signal.
1 (the on-resistance value is Ro1) and an input buffer (also called a receiver) 102. 121 is a semiconductor element I
This is an input / output circuit provided inside C2 for inputting / outputting signals, and includes an output buffer 103 (the on-resistance value is Ro2) and an input buffer 104.

Reference numeral 106 denotes a switching unit that switches between serial termination and short-circuit between the bidirectional transmission line 105 and the input / output circuit 120. The switching unit 106 includes a series termination resistor 108 (resistance value is Rs1), a short wire line (hereinafter, referred to as a short wire) 109, and a switch 1
07. The switch 107 connects the resistor 108 at the time of output of the input / output circuit 120, and connects the short wire 109 at the time of input (or other than output) of the input / output circuit 120.

Reference numeral 110 denotes a switching unit for switching between serial termination and short-circuit between the bidirectional transmission line 105 and the input / output circuit 121. The switching unit 110 includes a resistor 112 for series termination (resistance value is Rs2), a short line 113 for short, and a switch 111. Switch 1
11 connects the resistor 112 at the time of output of the input / output circuit 121, and connects the short wire 113 at the time of input (or other than output) of the input / output circuit 121.

Here, the resistor 108 has a value of Rs1 = Z
It has a resistance value determined by o-Ro1. This allows the output of the input / output circuit 120 (input / output circuit
(When 1 is input), impedance matching can be performed at the left end of the bidirectional transmission line 105. Similarly, the resistor 112 has a resistance value determined by Rs2 = Zo−Ro2. In addition, short lines 109 and 11
Reference numeral 3 may be a pattern on a printed circuit board or a resistor having a resistance value of 0Ω.

FIG. 8 is a diagram showing a circuit example of the switching unit 106. In the figure, the switching unit 106 is the switch 107 of FIG.
FET switches 201 and 202 are provided. F
Read / write signals are input to the gates of the ET switches 201 and 202. The read / write signal is output from the IC 1 as a bus master, and means a write at a low level and a signal other than read or write at a high level.

When the input / output circuit 120 outputs (writes), the FET switch 201 is turned on, so that the input / output circuit 120 and the resistor 108 are connected. When the input / output circuit 120 is input (read), the FET switch 202 is turned on, so that the input / output circuit 120 and the short line 109 are connected. In FIG. 8, F
Although an ET switch is used, another switch such as another TTL switch or an optical switch may be used as long as it can be turned on / off. Further, the switching unit 110 can have the same configuration as that of FIG.

In FIG. 7, the switches 107 and 11
1 are disposed on the input / output circuits 120 and 121 side, respectively, but may be disposed on the bidirectional transmission line 105 side. Further, although a resistor is used for series termination, another impedance element such as an inductor or a capacitor may be used. The operation of the bidirectional signal transmission device according to Embodiment 1 of the present invention configured as described above will be described.

When a signal is transmitted from the output buffer 101, the switch 107 in the switching unit 106 is connected to a resistor 108
And the switch 111 in the switching unit 110 connects the short line 113. This connection is made in a section where output data is determined because of the read / write signal as shown in FIG. In this state, the impedance between the output buffer 101 and the bidirectional transmission line 105 is matched by the resistor 108. The signal output from the output buffer 101 is a resistor 108, a bidirectional transmission line 105,
The data is transmitted to the input buffer 104 via the short line 113 in order.

Conversely, when transmitting a signal from the output buffer 103, the switch 111 in the switching unit 110 connects the resistor 112, and the switch 107 in the switching unit 106 connects the short line 109. In this state, resistor 1
12, the output buffer 103 and the bidirectional transmission line 105
The impedance between them is matched. Output buffer 10
3 is transmitted to the input buffer 102 via the resistor 112, the bidirectional transmission line 105, and the short line 109 in this order.

As described above, in the bidirectional signal transmission circuit of the present embodiment, at either end of the bidirectional transmission line, either the serial termination or the short circuit is appropriately switched depending on the signal transmission direction. There is an effect that impedance matching can be performed independently in both directions at the end point. Also, instead of a resistor for series termination, EM
An EMI suppression component such as an I filter may be used. In this case, there is an effect of suppressing EMI in addition to impedance matching.

<Second Embodiment> FIG. 9 is a diagram showing a configuration of a bidirectional signal transmission circuit according to a second embodiment of the present invention. The configuration of FIG. 11 is different from that of FIG.
The configuration is such that switching units 301 and 303 are provided instead of 0. Hereinafter, the description of the same points as in FIG. 7 will be omitted, and different points will be mainly described.

The switching units 301 and 303 are different from the switching units 106 and 110, respectively, in that amplification units 302 and 304 for amplifying signals are provided instead of the resistors 108 and 112, respectively. The amplification buffer 302 is an amplification buffer having an on-resistance value equal to the impedance Zo of the bidirectional transmission line 105. Thereby, impedance matching between the amplification buffer 302 and the bidirectional transmission line 105 can be achieved at the time of output. In addition, the amplification buffer 3
It is desirable that the amplification degree (drive capability) of 02 is determined according to the load of the bidirectional transmission line 105, that is, the number of circuits connected to the bidirectional transmission line 105.

The amplification buffer 304 is the same as the amplification buffer 302. As described above, the bidirectional signal transmission circuit according to the present embodiment not only performs impedance matching, but also changes the type of amplification buffer according to the signal transmission direction and the load on the transmission line to amplify the signal. The degree (current driving capability) can be changed.

Further, since the bidirectional signal transmission circuit according to the present embodiment includes the amplification buffers 302 and 304, it is suitable when the output buffer 101 in the IC1 and the output buffer 103 in the IC2 have low driving capabilities. . <Third Embodiment> FIG. 10 is a diagram showing a configuration of a bidirectional signal transmission circuit according to a third embodiment of the present invention. The configuration shown in FIG. 11 is different from that shown in FIG. 7 in that switching units 401 and 403 are provided instead of the switching units 106 and 110. Less than,
The description of the same points as in FIG. 7 will be omitted, and different points will be mainly described.

The switching units 401 and 403 are different from the switching units 106 and 110 respectively in that
02, 404, and resistors 108, 112
Is different from the resistance value. Amplification buffers 402, 40
4 is a stage preceding the resistors 108 and 112 for series termination (I
C1, IC2 side). Amplification buffer 402,
The on-resistance values of 404 are Ro11 and Ro22, respectively.

The resistance values Rs1, R of the resistors 108, 112
s2 is Rs1 = Zo-Ro11 and Rs2 = Z, respectively.
It is determined so as to satisfy o-Ro22. The configuration in FIG. 10 is different from the configuration in FIG. 9 in that resistors 108 and 112 are added. Here, the resistor 108,
Reference numeral 112 denotes an adjustment for matching the on-resistance of the amplification buffers 402 and 404 with the impedance of the bidirectional transmission line 105. Since the resistors 108 and 112 only need to have a resistance value that satisfies the above expression, the resistors 108 and 112 may be formed by a pattern on a printed circuit board instead of a physical resistance element. In that case, the resistance values Rs1 and Rs2 can be obtained by appropriately adjusting the width and length of the pattern.

As described above, according to the bidirectional signal transmission circuit of the present embodiment, the output buffers 101, 10
3, the amplification buffers 402 and 404 are provided at the subsequent stage.
The output buffers 101 and 103 may have low drive capability. Furthermore, resistors 108 and 112 for matching the impedance between the amplification buffer side and the bidirectional transmission line 105 are used.
Is provided, the range of elements that can be selected as the amplification buffers 402 and 404 increases (Ro11 <Zo, Ro22
<Zo).

<Fourth Embodiment> FIG. 11 shows a structure of a bidirectional signal transmission circuit according to a fourth embodiment of the present invention. The configuration shown in FIG. 13 is different from that of FIG. 7 in that switching units 501 and 503 are provided instead of the switching units 106 and 110. Hereinafter, the description of the same points as in FIG. 7 will be omitted, and different points will be mainly described.

The switching units 501 and 503 include the switching unit 106,
The difference is that switches 107a and 111a and terminating resistors 502 and 504 are added as compared with 110. The switch 107a switches the connection in conjunction with the switch 107. Similarly, the switch 111a is
Works with 1. Either switch may have the configuration shown in FIG.

The terminating resistor 502 is connected to the short line 109 as a parallel terminating resistor, and its resistance value is represented by Rt1.
And the terminating potential is Vt1. The resistance value Rt1 is Rt1 = Zo so that impedance can be matched at the end. The terminating resistor 504 is connected to the short line 113 as a parallel terminating resistor, and its resistance value is Rt2 and its terminating potential is Vt2. The resistance value Rt2 is Rt2 = Zo so that impedance can be matched at the end.

In the configuration of this embodiment, since the resistors 504 and 502 for parallel termination are provided, the resistors 108 and 112 for series termination may be replaced with short lines. In this embodiment, a resistor termination is used as a parallel termination, but another parallel termination such as a Thevenin termination shown in FIG. 5 or a diode termination shown in FIG. 6 may be used.

As described above, in the bidirectional signal transmission system according to the present embodiment, one of the parallel terminations can be selected according to the signal transmission direction. Therefore, impedance matching is performed independently at both ends of the bidirectional transmission line in both directions. There is an effect that can be. <Fifth Embodiment> FIG. 12 shows a structure of a bidirectional signal transmission circuit according to a fifth embodiment of the present invention. This figure is different from FIG.
3, the output enable signals 603 and 606 input to I
It is configured to supply the switches 107 and 111 from C1 and IC2. Further, the circuit example of FIG. 8 has a configuration in which read / write signals input to the gates of the switches 107 and 111 are replaced with output enable signals 603 and 606.

According to this configuration, the switching units 106 and 110 are switched in synchronization with the output enable signals of the output buffers in the IC1 and IC2 connected to the bidirectional transmission line. Alternatively, when a signal is received at the input buffer, the determined data can be transmitted more quickly and more reliably.

In the present embodiment, the output enable is set to low active, but a high active output enable may be used. In this case, the configuration in FIG. 8 may be a configuration in which the FETs 201 and 202 are interchanged. This embodiment may be applied to any of the second to fourth embodiments as well as the first embodiment.

Also, in each of the above embodiments, the switching units at both ends of the bidirectional transmission line are of the same type, but the switching unit 106 in the first embodiment and the switching unit 403 in the fourth embodiment, etc. Different types of switching units may be provided at both ends of the bidirectional transmission line. <Embodiment 6> In this embodiment, a configuration in the case of a bidirectional transmission line having a branch will be described. FIG. 13 shows a configuration of the bidirectional signal transmission circuit according to the sixth embodiment of the present invention. FIG. 1 shows one of the lines constituting the bus.

In the figure, a bus line 722 is terminated at both ends by resistors 723 and 724 for parallel termination, and switching units 707, 714 and 72 connected to the bus line 722.
1, and input / output circuits 730, 731 and 732 are connected via stub lines 703, 710 and 717, respectively. The input / output circuits 730, 731 and 732 are provided inside the semiconductor elements IC1, IC2 and IC3, respectively.

The input / output circuit 730 includes an output buffer 701
(The on-resistance is assumed to be Ro1) and the input buffer 702
Consisting of The input / output circuits 731 and 732 have the same configuration. The on-resistance values of the output buffers 708 and 715 are Ro2 and Ro3, respectively. Stub lines 703, 710,
717, Z1 is the bus line 72
Assuming that the characteristic impedance of Zo is Zo, Zo = 2 × Z
Z1 and Rt are determined so as to satisfy 1. The resistance value Rt of the parallel termination resistors 723 and 724 is Rt =
It is determined so as to satisfy Zo.

The switching units 707, 714, and 721 have the same configuration as the switching unit 106 shown in FIG. However, the resistance values Rs1, Rs1 of the resistors 706, 713, 720
s2 and Rs3 are stub lines 703 and 710, respectively.
Output buffers 701, 708, 71 connected to 717
Assuming that the on-resistance values of No. 5 are Ro1, Ro2 and Ro3, R
s1 = Z1-Ro1, Rs2 = Z1-Ro2, Rs3 =
It is determined so as to satisfy Z1-Ro3.

The operation of the bidirectional transmission line according to the present embodiment configured as described above will be described. When transmitting a signal from the output buffer 701, the switching unit 7
07 switch 704 to the resistor 706 side,
06, and is transmitted to the bus line 722. Zo = 2
× Z1, the stub line 703 and the bus line 722
The impedance at the T branch connection point between them is matched.
The signal flowing into the bus line 722 is transmitted in both directions, and is matched at the ends by the parallel terminating means 723 and 724.

Some of the signals are supplied to the switching units 714 and 721.
Via the stub lines 710 and 717. Here, the switches 711 and 718 of the switching units 714 and 721 are set to the short lines 712 and 719, respectively, and guided to the input buffers 709 and 716 via the short lines. As described above, since the bidirectional signal transmission system of the present embodiment has at least one parallel termination element in the bidirectional transmission line, impedance matching at the end of the transmission line can be achieved, and the switching unit and the stub Since the input / output circuit is connected to the bidirectional transmission circuit via the line, the impedance at the connection point on the bidirectional transmission line side and the input / output circuit side can be matched.

In the first to sixth embodiments, each switching unit is a circuit external to IC1 and IC2.
1. It may be configured to be built in the IC2. Further, in the case where each of the switching units is built in the IC in the first to sixth embodiments, the output line of the output buffer and the input line of the input buffer are separated as shown in FIG. The configuration may be as follows. 7, the switches 107 and 111 in each switching unit can be omitted as compared with FIG. <Seventh Embodiment> FIG. 15 is a diagram showing a configuration of a bus system according to a seventh embodiment of the present invention.

In FIG. 10, reference numeral 1001 denotes a master L such as a CPU or a memory controller, which is a subject of access.
SI and 1002 are slave LSIs to be accessed via a bus such as a memory. Master LSI 100
1 and the slave LSI 1002 are connected by two unidirectional buses, that is, a bus ADW [15: 0] and a bus ADR [15: 0]. The number in [] indicates the bit weight of the transmission line. For example, [15: 0] means a weight from 2 15 to 2 0, and [15] means 2 15 Means weight. Although not shown, the bus ADW [15: 0] has a series termination resistor as shown in FIG. 1 on the master LSI 1001 side or a parallel termination resistor as shown in FIGS. 5 and 6 on the slave LSI 1002 side. It is assumed that Also bus AD
Although not shown, the slave LSI 10
02 or a master L as shown in FIG.
It is assumed that the SI 1001 has a parallel termination resistor as shown in FIGS. It is desirable to place these series termination resistors as close as possible to the output terminal and the parallel termination resistors as close as possible to the input terminal. As a result, the master LSI 1001 and the slave LSI 1002 are connected only by a unidirectional bus without the bidirectional bus.
Impedance matching can be achieved very easily.
However, when the on-resistance of the output buffer is substantially equal to the impedance of each line of the bus, the terminating resistor may not be provided.

Reference numeral 1009a denotes a unidirectional transmission line for a clock signal output from the master LSI 1001 to the slave LSI 1002. 1009b is the master LSI
This is a transmission path for a strobe signal that is output from the slave LSI 1001 to the slave LSI 1002 and indicates the start of access and the output timing of the determined address. It should be noted that other transmission paths for control signals such as read / write are omitted because they are not the gist of the present invention.

The bus ADW [15: 0] is connected to the master LSI 100
1 is a unidirectional bus from 1 to the slave LSI 1002,
In the write access of the master LSI 1001, the address
It is for transmitting [13: 0] and write data [15: 0], and is for transmitting address [13: 0] at the time of reading. Bus ADR [15: 0]
From the slave LSI 1002 to the master LSI 100
This is a unidirectional bus to 1 and is not used for write access, and is for transmission of read data [15: 0] in read access. It is preferable that the bus ADW [15: 0] and the bus ADR [15: 0] are alternately patterned by one bit on a printed circuit board. Crosstalk can be reduced.

The master LSI 1001 includes an output switching unit 1003, selectors 1004a to 1004n, output buffers (also called drivers) 1005a to 1005r, and input buffers (also called receivers) 1006a to 1006p as circuits for the bus interface. However, part of the output buffer and the input buffer are omitted in FIG. In the figure, Address [13: 0] is a write / read address generated inside the master LSI 1001, Dataout [15: 0] is write data supplied from a register or the like inside the master LSI 1001, Datain [1].
[5: 0] means read data to be input to a register or the like in the master LSI 1001.

The master LSI 1001 has an input buffer and an input terminal connected to the input buffer, and an output buffer and an output terminal connected to the output buffer connected to the input buffer, similarly to the alternately wired transmission line. It is desirable to be arranged. The output switching unit 1003 controls selection of the selectors 1004a to 1004n. That is, the output switching unit 1003 selects the selector 1 in the write access.
004a to 1004n select Address [13: 0],
Subsequently, Dataout [15: 2] is selected, and in read access, Address [13: 0] is selected. Selection of Address [13: 0] is performed in synchronization with the strobe signal. In other words, the output switching unit 1003 operates during the period when the strobe signal is valid.
Select s [13: 0].

The selectors 1004n to 1004a are connected to Addr
ess [13: 0] and Dataout [15: 2] are input and output switching unit 1
Either one is selected by the control of 003. Specifically, the selectors 1004n to 1004a output Address [13:
0] and Dataout [15: 2] function as a multiplexer that performs time division multiplexing on the bus ADW [15: 2]. Output buffer 10
05r and 1005q output the clock signal CLK and the strobe signal STRB to the transmission lines 1009a and 1009b, respectively. Address output and data input / output of the master LSI 1001 are performed in synchronization with a clock signal.

The output buffers 1005p to 1005c are
Address [1] selected by selectors 1004a to 1004n
3: 0] or Dataout [15: 2] is output to the bus ADW [15: 2]. The output buffers 1005b and 1005a output Dataout [1: 0] to the bus ADW [1: 0] in the write access. The input buffers 1006p to 1006a input read data from the bus ADR {15: 0] in read access, and
The data is output as a register in the master LSI 1001 as in [15: 0].

The slave LSI 1002 includes input buffers 1007a to 1007a as circuits for a bus interface.
007r, output buffers 1008a to 1008p. However, part of the output buffer and the input buffer are omitted in FIG. In the figure, ADin [15: 2] is a 14-bit address input by time division multiplexing and the upper 14 bits of input data, ADin [1: 0] is lower 2 bits of input data, ADout [15: 0]. ] Means read data supplied from inside the slave LSI 1002.

The slave LSI 1002 has an input buffer and an input terminal connected thereto, and an output buffer and an output terminal connected thereto connected alternately, similarly to the transmission lines alternately wired. It is desirable to be arranged. Input buffer 1007r, 10
07q receives the clock signal CLK and the strobe signal STRB transmitted from the transmission lines 1009a and 1009b, respectively. Address input and data input / output of the slave LSI 1002 are performed in synchronization with the clock signal CLK.

The input buffers 1007p to 1007c are
Address and data are input from bus ADW [15: 2] and ADin [15:
2] to the internal latch circuit and the like. The address output to ADin [15: 2] is held at the timing indicated by the strobe signal STRB in an address latch (not shown) inside the slave LSI 1002 to separate it from the data input in a time-division manner. The data output following the address output to ADin [15: 2] is the memory cell specified by the address via the internal circuit (data latch, data register, write data buffer, etc.) of the slave LSI 1002. Is written to.

The input buffers 1007b and 1007a
Data is input from the bus ADW [1: 0]. Output buffer 10
08p to 1008a output the read data ADout [15: 0] to the bus ADR [15: 0]. The operation of the bus system according to the present embodiment configured as described above will be described.

FIGS. 16A and 16B are timing charts showing write access and read access, respectively. In the figure, both write access and read access are 4
Data burst transfer, that is, slave LSI 1002
Indicates an operation of writing and reading four consecutive data in synchronization with the clock signal after the address input. In the figure, hatched portions indicate Don't care, that is, any of a high level, a low level, and a high impedance may be used.

First, the write access in FIG. 16A will be described. <Cycles T0 and T1> The master LSI 1001 asserts the Address [13: 0] output and the strobe signal STRB at the timing of the leading edge of the clock at the beginning of the cycle T0. In the figure, the strobe signal is low active.

More specifically, the output switching unit 1003 sends Address [13: 0] to the selectors 1004n to 1004a with the rising edge of the clock at the beginning of the cycle T0 as a trigger.
To select. As a result, Address [13: 0] is output to ADW [15: 2] via output buffers 1005p to 1005c. At the same time, a strobe signal STRB indicating that the address is valid is also asserted. During this period, ADW [1: 0] and ADR [15: 0] are not used and Don't car
e. The output of Address [13: 0] and the assertion of the strobe signal are terminated by the rising edge at the beginning of cycle T2 as a trigger.

The master LSI 1001 outputs a read / write signal or the like (not shown) to the slave LSI 1002 to notify the slave LSI 1002 of write access. <Cycle T2, T3> After that, the master LSI 100
1 outputs Dataout [15: 0] to the bus ADW [15: 0] as data in a state determined at the timing of the leading edge of the cycle T3 (W1 [15: 0] in the figure).

More specifically, the output switching unit 1003 sets the clock before the leading edge of the clock at the beginning of the cycle T3.
The selectors 1004n to 1004a select Dataout [15: 2]. As a result, Dataout [15: 0] is output buffer 1
W1 [15: 0] to ADW [15: 0] via 005p-1005a
Is output as <Cycle T4 to T6> Hereinafter, similarly, cycle T4,
At the timing of each leading edge of T5 and T6, the master LSI 1001 operates so that the data becomes determined at the timing of each rising edge.
Is the value of Dataout [15: 0] (w2 [15: 0], W3 [15: 0], W4 [1
5: 0]) is output to ADW [15: 0].

On the other hand, in the slave LSI 1002, in cycles T3 to T6, w1 [15: 0] to W4 [15: 0] from the bus ADW [15: 0] via the input buffers 1007p to 1007a.
Are sequentially taken into an internal register or the like. Next, the read cycle of FIG. 16B will be described. <Cycles T0 and T1> The master LSI 1001 asserts the Address [13: 0] output and the strobe signal STRB at the timing of the leading edge of the clock at the beginning of the cycle T0. In the figure, the strobe signal is low active.
This is the same as the cycles T0 and T1 of the write access.

The master LSI 1001 outputs a read / write signal or the like (not shown) to the slave LSI 1002 to notify the slave LSI 1002 of the read access. <Cycle T2 to T6> The slave LSI 1002 outputs data Rl [15: 0] to ADR [15: 0] so that the data is determined before and after the leading edge of the cycle T3.
At this time, ADW [15: 0] is an unused bus and becomes Don't care.

Similarly, the slave L is set so that data is determined before and after each rising edge of each of the cycles T4 to T6.
The SI 1002 has read data R2 [15: 0] and R3 [1
5: 0] and R4 [15: 0] are sequentially output to the bus ADR [15: 0]. On the other hand, the master LSI 1001 sequentially reads the read data R1 [15: 0] to R4 [15: 0] input from the bus ADR [15: 0] via the input buffers 1006p to 1006a as Datain [15: 0]. Take it into a register or the like.

As described above, in the bus system according to the present embodiment, since the address, write data, and read data are transmitted using only the one-way bus, impedance matching can be extremely easily achieved, The speed of the clock signal can be increased. In this embodiment, the address is 14 bits and the data is 16 bits. However, the present invention is not limited to this, and any number of bits may be used.

Each bit is multiplexed in order from the MSB of the address (Address [13]) and the MSB of the data (Data [15]). One bit of the address and one bit of the data are multiplexed. Any bit may be multiplexed as long as the configuration is multiplexed. In this embodiment, the address is output for two clocks, and the data is input / output one clock after that. However, the output timing of the address and the data and the output period are determined by the Setup Time and the time between the LSIs performing the data transfer. It is determined in consideration of Hold Time and the like, and is not limited to the one shown in the present embodiment.

Further, in this embodiment, the strobe signal
The STRB is a signal indicating that data (address, etc.) other than data is output on the bus.
RAS and CAS for M, FR for PCI interface
It corresponds to a signal such as AME #. Further, as shown in FIG. 17, the holding circuit 130 shown in FIG.
9p to 1309a and 2309p to 2309a may be added.

Referring to FIG. 17, holding circuits 1309p-13
09a is the output buffer 1 in the master LSI 1001.
005p to 1005a, which are inserted on the input side and hold the previous address or data as they are, so that the bus ADW is output via the output buffer in a section not used for address transmission or data transmission (idle period of the bus).
[15: 0] is fixed to high level or low level.

The holding circuits 2309p to 2309a are output buffers 1008p to 1008 of the slave LSI 1002.
a, the bus ADR [15: 0] is set to a high level or a low level via an output buffer in a section not used for address transmission or data transmission by retaining the previous address or data as it is. Fixed to.

Each holding circuit may use a D-type flip-flop, a latch, a transparent latch, or the like.
18A and 18B show timing charts of write access and read access in the configuration of FIG. FIGS. 18A and 18B will be described in comparison with FIGS. 16A and 16B. The valid address and data timings are the same, but differ in the following respects. 18A and 18B
Then, the bus ADW [15: 0] in FIGS. 16A and 16B and the bus
In ADR [15: 0], the section has become Don't care and the section (hatched section with hatching) has been eliminated. That is, the hatching section is fixed to the same level as the address or data output immediately before in FIGS. 18A and 18B.

The bus ADW [15: 0] and the bus ADR [15: 0] are alternately wired one bit at a time, so that a level-fixed transmission line exists on both sides of each wiring in use. A guard ring (also called a guard trace) of the transmission line is formed. This makes it possible to reduce noise such as crosstalk generated when the transfer speed is increased. Further, since the same value as that of the previous transfer is output, unnecessary charge / discharge of the transmission line can be suppressed, and an increase in power consumption can be prevented. <Eighth Embodiment> FIG. 19 shows a structure of a bus system according to an eighth embodiment. 15, the same horizontal components as those in FIG. 15 are denoted by the same reference numerals, and therefore the description of the same components will be omitted, and different points will be mainly described below.

FIG. 19 is different from FIG.
The difference is that a master LSI 2001 and a slave LSI 2002 are provided instead of the 001 and the slave LSI 1002. Master LSI 2001 is a master LSI
Compared with the output switching unit 1003, the output switching unit 5003 is replaced by selectors 1004n to 1004a.
In that selectors 5004p to 5004c are provided instead of, and selectors 5004b and 5004a are newly added.

Output switching section 5003 is provided with selector 5004
Address [13: 0] and Dataout [15: 2] in p ~ 5004c
Is controlled in the same manner as the output switching unit 1003 in FIG. In addition, the output switching unit 5003 controls the selectors 5004p to 5004a to select the ground level (low level) when the bus ADW [15: 0] is not used.

The selectors 5004p to 5004c are connected to the Addr
ess [13: 0], Dataout [15: 2], and the ground level are input, and any one is selected under the control of the output switching unit 5003.
Bus ADW via output buffers 1005p to 1005c
Output to [15: 2]. Selectors 5004b, 5004a
Dataout [1: 0] and the ground level are input, and one of them is selected under the control of the output switching unit 5003.

The slave LSI 2002 differs from the slave LSI 1002 shown in FIG.
6 and selectors 5007p to 5007a. The output switching unit 5006 includes a selector 500
Control is performed so that the ground level is selected when the bus ADR [15: 0] is not used for 7p to 5007a.

The selectors 5007p to 5007a are
t [15: 0] and the ground level are input, and the output switching unit 5
Either is selected by the control of 006. Regarding the bus system according to the present embodiment configured as described above,
The operation will be described. 20A and 20B show timing charts of write access and read access in the bus system of FIG. 20A and 20B will be described in comparison with FIGS. 16A and 16B. The valid address and data timings are the same, but differ in the following respects. In FIGS. 20A and 20B, FIGS.
Don 'on bus ADW [15: 0] and bus ADR [15: 0] in B
The section (hatched section with diagonal lines) has been eliminated as t care. That is, the hatched section is fixed to the ground level in FIGS. 20A and 20B.

Since the bus ADW [15: 0] and the bus ADR [15: 0] are alternately wired one bit at a time, a transmission line fixed to the ground exists on both sides of each in-use wiring. A guard ring of the transmission line is formed. As a result, not only impedance matching is achieved, but also noise such as crosstalk generated when the transfer speed is increased can be suppressed.

In this embodiment, the buses ADW [15: 0],
The bus ADR [15: 0] is fixed at the LOW level when not in use, but it may be fixed at the High level, and some are mixed such as the LOW level and the rest at the HIGH level. It does not matter. <Ninth Embodiment> FIG. 21 is a diagram showing a configuration of a bus system according to a ninth embodiment. 19, the same horizontal components as those in FIG. 19 are denoted by the same reference numerals, and therefore, the description of the same components will be omitted, and the following description will focus on the differences.

FIG. 21 is different from FIG. 19 in that the master LS
The master LSI 3001 is used instead of the I2001, and the slave LSI 3002 is used instead of the slave LSI 2002.
Is different. Master LSI 3001
Is different from the master LSI 2001 in that the switch 17
The difference is that 10p to 1710a are newly added and that an output switching unit 7003 is provided instead of the output switching unit 5003.

The switches 1710p to 1710a turn on / off between the input lines of the input buffers 1006p to 1006a and the ground line, respectively, under the control of the output switching unit 7003. The output switching unit 7003 includes an output switching unit 500
3 compared with ON / OFF of switches 1710p to 1710a.
A function to control off has been added. That is, while the output switching unit 7003 causes the selectors 5004p to 5004a to select a signal other than the ground level, the output
10p to 1710a are turned on, and the selector 5004p to
While the ground level is selected by the switch 5004a, the switches 1710p to 1710a are turned off.

The slave LSI 3002 has a slave LS
Compared to I2002, new switches 1711p-1
711a is added and an output switching unit 7006 is provided instead of the output switching unit 5006.
The switches 1711p to 1711a are switches for turning on / off between the input lines of the input buffers 1007p to 1007a and the ground line under the control of the output switching unit 7006.

Output switching section 7006 includes output switching section 500
6 compared with ON / OFF of switches 1711p to 1711a.
A function to control off has been added. That is, while the output switching unit 7006 causes the selectors 5007p to 5007a to select a signal other than the ground level, the output
11p to 1711a are turned on, and the selector 5007p to
While the ground level is selected by the switch 5007a, the switches 1711p to 1711a are turned off.

According to the above configuration, when the bus ADW [15: 0] is being used for transmitting an address or data,
Switches 1710p to 1710a are turned on, and selectors 5007p to 5007a select the ground level. As a result, the bus ADR [15: 0] is fixed to the ground level from both ends. As a result, the individual lines included in the bus ADW [15: 0] transmitting the address or the data are interposed between the lines at the ground level.

Conversely, when the bus ADR [15: 0] is being used to transmit an address or data, the switch 171 is not used.
1p to 1711a are turned on, and the selector 5004
p to 5004a select the ground level. As a result, the bus ADW [15: 0] is fixed to the ground level from both ends. As a result, the bus ADW [15: 0] is fixed to the ground level from both ends. As a result, individual transmission lines included in the bus ADR [15: 0] transmitting data are sandwiched between lines at the ground level.

As described above, in the bus system according to the present embodiment, not only impedance matching is facilitated but also signals on both sides of each transmission line of the bus used are fixed to the ground level at both ends. Accordingly, a guard ring of the transmission line is formed, and it is possible to suppress noise such as crosstalk generated when the transfer speed is increased.

In FIG. 21, the switch 1710
p to 1710a, 1711p to 1711a are connected to a power supply line (or high level) instead of a ground line, and selectors 5004p to 5004a, 5007p
It may be configured to connect to a power supply line (or high level) instead of the ground line input of ~ 5007a. In this case, an unused bus is fixed to the power supply level (or high level) instead of being fixed to the ground level.

Further, a configuration may be adopted in which some transmission lines constituting the bus are fixed at the ground level, and the remaining transmission lines are fixed at the power supply level (or high level). Further, the configuration shown in FIG. 22 may be adopted. FIG. 22 is different from FIG. 21 in that an output switching unit 8003 is used instead of the output switching unit 7003.
With the holding circuits (FF in FIG. 22) 1309p to 1309
a, 1810p-1810a, 2309p-2309
a, 1811p to 1811a, and the selector 500
Selectors 1504n-155 instead of 4p5004c
04a instead of the output switching unit 7006
006, and selectors 5004b, a, selector 50
07p to 5007a are deleted (however, illustration is omitted except for the circuit portion corresponding to the MSB).

Holding circuits 1309p to 1309a, 230
9p to 2309a are the same as those in FIG. The holding circuits 1810p to 1810a
It is inserted on the output side of the input buffers 1006p to 1006a, and retains the previous data as it is. Holding circuit 181
0p to 1810a may be constituted by a D-type flip-flop or a latch circuit.

Under the control of the output switching section 8003, the switches 1710p to 1710a are turned off while the bus ADR [15: 0] is used, and the switches A10 [15: 0] are used. ON during no period, that is, the holding circuit 1810p
To the input buffer 100.
Output to input lines 6p to 1006a. Thus, while the bus ADR [15: 0] is not used, the holding circuit 18
The level is fixed at the level of the previously input data held in 10p to 1810a. This allows the bus AD
R [15: 0] indicates that the holding circuit 230 is not being used.
The level is fixed on the output side by 9p to 2309a, and the same level is fixed on the input side by switches 1710p to 1710a.

The holding circuits 1811p to 1811a and the switches 1711p to 1711a are
810a and switches 1710p to 1710a. Thus, the level of the bus ADW [15: 0] can be fixed at the input side. As a result, the bus ADW [15: 0] holds the holding circuits 1309p to 1309 during periods when they are not used.
The level is fixed on the output side by a, and the same level is fixed on the input side by switches 1711p to 1711a.

FIG. 23 shows switches 1710p to 1710
a, a circuit example of one of 1711p to 1711a. The switches in FIG.
3. It is composed of an inverter 904. Note that a configuration other than that shown in FIG. 23 may be used as long as three types of switching, that is, power line connection, ground line connection, and non-connection can be performed according to the value held by the holding circuit and an instruction from the output switching unit.

According to the configuration shown in FIG. 22, not only impedance matching is facilitated but also signals on both sides of the used bus are fixed to a low level or a high level at both ends of the transmission line, thereby enabling transmission. The guard ring of the line is formed, and it is possible to suppress noise such as crosstalk that occurs when the transfer speed is increased. Further, by fixing the potential to the same as the potential of the immediately preceding bus, unnecessary charge and discharge of the transmission line can be suppressed, and an increase in power consumption can be prevented.

In the configuration of FIG. 22, when the on-resistance of each output buffer and the impedance of the transmission line are mismatched, series termination resistors (damping resistors) 1010p to 1010a and 1011p to 1011p as shown in FIG. 10
11a may be used for impedance matching. It is desirable to insert each damping resistor in the immediate vicinity of the output terminal of the LSI. The resistance value R1 of the damping resistors 1010p to 1010a is determined by the characteristic impedance of the transmission line ADW [n] (n = 0 to 15) by Zl, the output impedance of the output buffers 1005p to 1005a by Zo1, and R1 = Z1−Zo1. .

Similarly, the damping resistors 1011p to 1011p to 1011p
The resistance value R2 of 11a is determined by R2 = Z2-Zo2. Here, Z2 is the characteristic impedance of the transmission line ADR [i] (i = 0 to 15), and Zo2 is the output buffer 1008p
-100a.

[0096]

The bidirectional transmission circuit according to the present invention includes a transceiver for inputting and outputting a signal, a first element having impedance, a second element which is a short-circuit wire, and a first element when the transceiver outputs. Sometimes a switching unit is provided for connecting the second element between the transceiver and the bidirectional transmission line.

According to this configuration, the impedance between the transceiver and the bidirectional transmission line can be changed between the time of output and the time of input of the transceiver. Impedance matching can be achieved, and the signal transmission speed can be increased. Here, the impedance of the first element is configured to be a value that matches the combined impedance of the impedance of the first element and the output impedance of the transceiver with the characteristic impedance of the bidirectional transmission line.

Further, the first element may be constituted by a resistance element. According to this configuration, since the first element is a resistive element, an appropriate impedance value can be easily realized, and the second element can be realized very simply because a short line or a printed circuit board pattern is sufficient. Here, the first
The element may be a driver element for amplifying the output current of the transceiver.

According to this configuration, in addition to the above effects, the output impedance value of the driver element is matched with the characteristic impedance value of the bidirectional transmission line, or the characteristic impedance value of the bidirectional transmission line is changed to the output impedance value of the driver element. , Impedance matching can be achieved. Furthermore, even if the current drive capability of the transceiver is low, the drive capability can be appropriately adjusted by mounting a driver element having a drive capability according to the load on the bidirectional transmission line.

Here, the first element may be rehabilitated by a set of a driver element for amplifying an output current of the transceiver and a resistance element. According to this configuration, since the resistance element is provided in addition to the driver element, the impedance value of the first element can be easily adjusted by the resistance element in addition to the effect described above.

Here, the switching unit includes first and second switching elements that are turned on / off in opposite directions, the first switching element and the first element are connected in series, and the second switching element and the second element are connected to each other. The two series-connected element groups may be connected in series, and may be connected in parallel between the transceiver and the bidirectional transmission line. According to this configuration, the first and second elements are connected to the transceiver or the bidirectional transmission line by the first and second switching elements, respectively. Since the first and second switching elements may be FET switches or the like, they can be configured at low cost.

The switching section includes first and second switching elements which are turned on / off contradictoryly, and third and fourth switching elements which are turned on / off contradictoryly. The first switching element, the first element, and the third switching element are connected in series in this order; the second switching element, the second element, and the fourth switching element are connected in series in this order; The two series-connected element groups may be connected in parallel between the transceiver and the bidirectional transmission line.

According to this configuration, the first and second elements are switched by the switching elements connected to both sides thereof.
Because it is connected between the transceiver and the bidirectional transmission line, when the switching element is off, it can be completely disconnected from the transceiver and the bidirectional transmission line, and the floating line portion that is not electrically terminated is removed. It can be completely eliminated.

Here, the first and second switching elements are:
It may be configured to be turned on / off in accordance with any of a write signal indicating a write timing of an output signal of the transceiver and an output enable signal of the transceiver. According to this configuration, since the first and second switching elements are turned on / off by the write signal or the output enable signal,
The first and second elements can be switched in synchronization with the input / output timing of the transceiver.

Further, the system of the present invention comprises a first LSI which is a subject of access and a second LSI which is a subject of access.
A bus system for transmitting addresses and data between SIs, comprising: a first unidirectional bus for unidirectionally transmitting addresses and write data output from a first LSI to a second LSI; and a read system outputting data from the second LSI. First data
A second unidirectional bus for transmitting unidirectionally to the SI, wherein the first unidirectional bus transmits an address and write data at the time of write access by the first LSI, and a first unidirectional bus at the time of read access by the first LSI. Is configured to transmit a read address, and the second bus is configured to transmit read data.

According to this configuration, from the first LSI to the second L
Since both the write access and the read access to the SI are realized only by a unidirectional bus, impedance matching can be extremely easily achieved. Here, the main signal lines included in the first unidirectional bus may be alternately wired to the signal lines included in the second unidirectional bus.

According to this configuration, the main signal lines in the first unidirectional bus are alternately wired to the signal lines in the second bus, so that the effects of crosstalk and the like are suppressed and noise resistance is improved. Can be done. Here, at least one of the first and second LSIs may have a configuration in which input terminals and output terminals corresponding to the alternately wired signal lines are alternately arranged.

According to this configuration, since the input terminals and the output terminals are alternately arranged, the noise resistance can be further improved. Here, the first unidirectional bus may transmit the write data after transmitting the address. According to this configuration, since the write address and the write data are transmitted in a time-division manner on the first unidirectional bus, the number of terminals of the first and second LSIs can be minimized.

Here, the bus system may further comprise a fixing means for fixing the bus potential to a high level or a low level during at least one of the first and second unidirectional buses during an idle period of the bus. Good. According to this configuration, the bus potential is fixed at the high level or the low level during the idle period of the bus, so that the noise resistance can be further improved.

Here, the fixing means may be configured to fix to the fixed level from both ends of the bus. According to this configuration, since the fixing means fixes the bus to the fixed level from both ends of the bus, the time required to reach the fixed level over the entire bus can be reduced, and the transmission speed can be further increased. be able to.

[Brief description of the drawings]

FIG. 1 shows an example of a circuit terminated in series in a unidirectional transmission line.

FIG. 2 shows a circuit in which a resistor is inserted in series at one end of a bidirectional transmission line.

FIG. 3 shows a circuit example of RSL (Rambus Signaling Logic).

FIG. 4 shows a circuit example of SSTL (Stub Series Terminated Logic).

FIG. 5 shows an example of a Thevenin-terminated circuit.

FIG. 6 shows an example of a diode-terminated circuit.

FIG. 7 shows a configuration of a bidirectional signal transmission circuit according to the first embodiment.

FIG. 8 shows a circuit example of a switching unit.

FIG. 9 shows a configuration of a bidirectional signal transmission circuit according to a second embodiment.

FIG. 10 shows a configuration of a bidirectional signal transmission circuit according to a third embodiment.

FIG. 11 shows a configuration of a bidirectional signal transmission circuit according to a fourth embodiment.

FIG. 12 shows a configuration of a bidirectional signal transmission circuit according to a fifth embodiment.

FIG. 13 shows a configuration of a bidirectional signal transmission circuit according to a sixth embodiment.

FIG. 14 shows a modification of the bidirectional signal transmission circuit.

FIG. 15 shows a configuration of a bus system according to a seventh embodiment.

FIG. 16 shows a timing chart of write access and read access.

FIG. 17 shows a modification of the bus system according to the embodiment.

18 shows a timing chart of write access and read access according to the configuration of FIG. 17;

FIG. 19 shows a configuration of a bus system according to an eighth embodiment.

20 shows a timing chart of write access and read access according to the configuration of FIG. 19;

FIG. 21 shows a configuration of a bus system according to a ninth embodiment.

FIG. 22 shows a modification of the bus system in the embodiment.

FIG. 23 shows a circuit example of one switch in FIG. 22;

FIG. 24 shows a circuit example in which a damping resistor is added to the configuration of FIG.

[Explanation of symbols]

101, 103, 701, 702, 708 Output buffer 102, 104, 709 Input buffer 105 Bidirectional transmission line 106, 110, 301, 110, 401, 403, 5
01, 707, 714 switching unit 107, 107a, 111, 111a, switch 108, 112, 504, 706, 723 resistor 109, 113, 712 short line 120, 121 input / output circuit 201, 202 FET switch 302, 304, 402 Amplification buffer 502, 504 Termination resistor 603 Output enable signal 703, 710 Stub line 722 Bus line 723 Parallel termination means 730, 731 Input / output circuit 1001, 2001, 3001 Master LSI 1002, 2002, 3002 Slave LSI 1003, 5003, 5006, 7003, 7006,
8003, 8006 output switching unit 1004n to 1004a selector 1005p to 1005a output buffer 1005p to 1005a output buffer 1006p to 1006a input buffer 1007a to 1007r input buffer 1007p to 1007a input buffer 1008p to 1008a output buffer 1009a transmission line 1010p to 1010a damping 1011a Damping resistor 1309p to 1309a Holding circuit 1504n to 1504a Selector 1710p to 1710a Switch 1711p to 1711a Switch 1810p to 1810a Holding circuit 1811p to 1811a Holding circuit 2309p to 2309a Holding circuit 5004p to 5004a Selector 5007p to 5007a

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H03K 19/00 101S

Claims (34)

[Claims] 1. A bidirectional transmission circuit for inputting / outputting a signal to / from a bidirectional transmission line, a transceiver for inputting / outputting a signal, a first element having impedance, a second element serving as a shorting wire, and a transceiver. The first element at the time of output, and the second element at the time of input.
A bidirectional transmission circuit, comprising: a switching unit that connects an element between a transceiver and a bidirectional transmission line. 2. The impedance of the first element is a value that matches the combined impedance of the impedance of the first element and the output impedance of the transceiver with the characteristic impedance of the bidirectional transmission line. Item 2. The bidirectional transmission circuit according to Item 1. 3. The bidirectional transmission circuit according to claim 2, wherein said first element is a resistance element. 4. The bidirectional transmission circuit according to claim 2, wherein said first element is a driver element for amplifying an output current of said transceiver. 5. The bidirectional transmission circuit according to claim 2, wherein said first element is a set of a driver element and a resistance element for amplifying an output current of said transceiver. 6. The switching unit includes first and second switching elements that are turned on / off in opposition, the first switching element and the first element are connected in series, and the second switching element and the second element are connected in series. 3. The bidirectional transmission circuit according to claim 2, wherein the two serially connected element groups are connected in parallel between the transceiver and the bidirectional transmission line. 7. The switching device according to claim 6, wherein the first and second switching elements are turned on / off in response to one of a write signal indicating a write timing of an output signal of the transceiver and an output enable signal of the transceiver. Bidirectional transmission circuit. 8. The switching unit includes first and second switching elements that are turned on / off contradictoryly, and third and fourth switching elements that are turned on / off contradictoryly. Turning on / off simultaneously with one switching element, the first switching element, the first element, and the third switching element are connected in series in this order; the second switching element, the second element, and the fourth switching element are connected in series in this order; 3. The bidirectional transmission circuit according to claim 2, wherein the two series connection element groups are connected in parallel between the transceiver and the bidirectional transmission line. 9. The first and third switching elements are turned on / off simultaneously in response to one of a write signal indicating a write timing of an output signal of the transceiver and an output enable signal of the transceiver, and the second and fourth switching elements are provided. 9. The bidirectional transmission circuit according to claim 8, wherein the two are turned on / off at the same time. 10. A circuit for transmitting a signal to a bidirectional transmission line, comprising: a first transceiver for inputting and outputting a signal; and a first transceiver provided between the first end of the bidirectional transmission line and the first transceiver. An element, a first impedance unit having a second element having an impedance value smaller than that of the first element, a second transceiver for inputting and outputting a signal, and a second transceiver provided between the second end of the bidirectional transmission line and the second transceiver. And a second impedance section having a third element, four elements having an impedance value smaller than the third element, and a first end and a first end when transmitting a signal from the first transceiver to the second transceiver. When a first element is connected to a transceiver and a signal is transmitted from the second transceiver to the first transceiver, a first element is connected between the first end and the first transceiver. When transmitting a signal from the first transceiver to the second transceiver, a fourth element is connected between the second end and the second transceiver, and the signal is transmitted from the second transceiver to the first transceiver. A bidirectional transmission circuit, comprising: a second switching unit that connects a third element between the second end and the second transceiver. 11. The impedance of the first element is a value that matches the combined impedance of the impedance of the first element and the output impedance of the transceiver with the characteristic impedance of the bidirectional transmission line. The impedance is a value that matches the combined impedance of the impedance of the third element and the output impedance of the transceiver with the characteristic impedance of the bidirectional transmission line. The second and fourth elements are short-circuited wires. The bidirectional transmission circuit according to claim 10, wherein: 12. The bidirectional transmission circuit according to claim 11, wherein said first element is a resistance element. 13. The bidirectional transmission circuit according to claim 11, wherein said first element is a driver element for amplifying an output current of said transceiver. 14. The bidirectional transmission circuit according to claim 11, wherein said first element is a set of a driver element for amplifying an output current of said transceiver and a resistance element. 15. The first switching unit, wherein the switching unit includes first and second switching elements that are turned on / off contradictoryly, the first switching element and the first element are connected in series, and the second switching is performed. An element and a second element are connected in series; the two series-connected element groups are connected in parallel between the first transceiver and the first end of the bidirectional transmission line; The unit includes third and fourth switching elements that are turned on / off contradictoryly, the third switching element and the third element are connected in series, the fourth switching element and the fourth element are connected in series, The bidirectional transmission circuit according to claim 11, wherein a series connection element group is connected in parallel between the two transceivers and a second end of the bidirectional transmission line. 16. The device according to claim 15, wherein the first switching element is turned on / off in response to one of a write signal indicating a write timing of an output signal of the transceiver and an output enable signal for the first transceiver. A bidirectional transmission circuit as described. 17. The first switching unit includes first to fourth switching elements, the second switching unit includes fifth to eighth switching elements, a first switching element, a first element, and a third switching element. The switching element forms a first series circuit connected in series in this order. The second switching element, the second element, and the fourth switching element form a second series circuit connected in series in this order. A series circuit is connected in parallel between the first transceiver and the bidirectional transmission line; the fifth switching element, the third element, and the seventh switching element form a third series circuit connected in series in this order; The sixth switching element, the fourth element, and the eighth switching element form a fourth series circuit connected in series in this order, and the third and fourth series circuits are arranged in parallel between the second transceiver and the bidirectional transmission line. The first switching unit turns on the first and third switching elements when transmitting a signal from the first transceiver to the second transceiver, and transmits the signal from the second transceiver to the first transceiver. The second switching unit turns on the sixth and eighth switching elements when transmitting a signal from the first transceiver to the second transceiver, and turns on the second and fourth switching elements. The bidirectional transmission circuit according to claim 11, wherein when transmitting a signal from the transceiver to the first transceiver, the fifth and seventh switching elements are turned on. 18. A first LSI serving as an access main body,
A bus system for transmitting addresses and data between second LSIs to be accessed, comprising: a first unidirectional bus for unidirectionally transmitting an address and write data output from a first LSI to a second LSI; A second unidirectional bus for transmitting read data output from the 2LSI to the first LSI in a unidirectional manner, wherein at the time of write access by the first LSI, the first unidirectional bus transmits an address and write data;
A first unidirectional bus for transmitting a read address, and a second bus for transmitting read data at the time of read access by the bus system. 19. The bus system according to claim 18, wherein main signal lines included in the first unidirectional bus are alternately wired to signal lines included in the second unidirectional bus. 20. The at least one of the first and second LSIs, wherein input terminals and output terminals corresponding to the alternately wired signal lines are alternately arranged. Bus system. 21. The bus system according to claim 19, wherein the first unidirectional bus transmits write data after transmitting the address. 22. The bus system further comprises a fixing means for fixing the bus potential to a high level or a low level during at least one of the first and second unidirectional buses during an idle period of the bus. 20. The bus system according to claim 19, wherein: 23. The bus system according to claim 22, wherein said fixing means fixes the fixed level from both ends of the bus. 24. A first LSI serving as an access main body,
A bus system for transmitting addresses and data between second LSIs to be accessed, a first unidirectional bus for unidirectionally transmitting an address and write data output from a first LSI to a second LSI, a second LSI A second unidirectional bus that unidirectionally transmits read data output from the first LSI to the first LSI, and is provided in the first LSI, and in a write access by the first LSI, a write address and write data are output to the first unidirectional bus. In the read access by the first LSI, a first input / output means for outputting a read address to a first unidirectional bus and inputting read data from a second unidirectional bus is provided in the second LSI. , A write address and write data are input from a first unidirectional bus, and in the read access, And a second input / output means for inputting a read address and outputting read data to a second unidirectional bus. 25. The bus system according to claim 24, wherein main signal lines in the first unidirectional bus are alternately wired to signal lines in the second bus. 26. The at least one of the first and second LSIs, wherein input terminals and output terminals corresponding to the alternately wired signal lines are alternately arranged. Bus system. 27. The first input / output unit, provided in a first LSI, for multiplexing a write address and write data in a time-division manner, and for the write access, a multiplex result in a first unidirectional direction. A first output means for outputting data to a bus and outputting a read address to a first unidirectional bus for read access; and a first input means for inputting read data from a second unidirectional bus for read access. (2) input / output means for inputting a multiplex result from a first unidirectional bus in the write access, inputting a read address from the first unidirectional bus in read access, and reading data in the read access 26. The bus system according to claim 25, further comprising second output means for outputting in a second unidirectional direction. 28. The system according to claim 27, wherein the first output means outputs a high level or a low level to the first unidirectional bus as a first fixed level during an idle period of the first unidirectional bus. Bus system. 29. The first input / output means further comprises first holding means for holding write data at the time of a previous write access or a read address by a previous read access, and wherein the first output means comprises a first unit. 29. The bus system according to claim 28, wherein the contents of the holding means are output as the first fixed level during the idle period of the direction bus. 30. The multiplexing means, to which a write address, write data and a first fixed level are inputted, outputs a first fixed level during an idle period of a first unidirectional bus, and wherein the first output means comprises: 29. The bus system according to claim 28, wherein a first fixed level is output from the multiplexing means during an idle period of the first unidirectional bus. 31. The apparatus according to claim 28, wherein the second output means outputs a high level or a low level to the second unidirectional bus as a second fixed level during an idle period of the second unidirectional bus. Bus system. 32. The second input / output means further comprises a second holding means for holding read data at the time of a previous read access, wherein the second output means holds the data during an idle period of a second unidirectional bus. 32. The bus system according to claim 31, wherein the content of the bus system is output as a second fixed level. 33. The second input / output means further receives read data and a second fixed level, selects read data at the time of read access, and sets the second fixed level during an idle period of a second unidirectional bus. 32. The bus system according to claim 31, further comprising selection means for selecting, wherein the second output means outputs the selected second fixed level to the selection means during an idle period of the second unidirectional bus. 34. The first fixing means for fixing the second unidirectional bus to the second fixed level on the input side of the first input means during an idle period of the second unidirectional bus. Wherein the second input / output means further comprises second fixing means for fixing the first unidirectional bus to the first fixed level on the input side of the second input means during an idle period of the first unidirectional bus. 32. The bus system according to claim 31, wherein: