JP2001085558A - Semiconductor device and mountig method therefor - Google Patents
Semiconductor device and mountig method thereforInfo
- Publication number
- JP2001085558A JP2001085558A JP25798999A JP25798999A JP2001085558A JP 2001085558 A JP2001085558 A JP 2001085558A JP 25798999 A JP25798999 A JP 25798999A JP 25798999 A JP25798999 A JP 25798999A JP 2001085558 A JP2001085558 A JP 2001085558A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- electrode
- semiconductor device
- bump
- bumps
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置の実装
技術に関し、特に、ＢＧＡ（Ｂａｌｌ ＧｒｉｄＡｒｒ
ａｙ），ＣＳＰ（Ｃｈｉｐ Ｓｉｚｅ Ｐａｃｋａｇ
ｅ）などのバンプを用いて実装される半導体装置に適用
して有効な技術に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device mounting technique, and more particularly to a BGA (Ball GridArr).
ay), CSP (Chip Size Package)
e) The present invention relates to a technique effective when applied to a semiconductor device mounted using bumps such as e).
【０００２】[0002]
【従来の技術】本発明者が検討したところによれば、Ｂ
ＧＡやＣＳＰ形半導体装置では、外部導出用リードの代
わりとして球形のはんだ、いわゆる、はんだボールが用
いられている。2. Description of the Related Art According to studies made by the present inventor, B
In a GA or CSP type semiconductor device, a spherical solder, that is, a so-called solder ball is used instead of an external lead.
【０００３】たとえば、ＢＧＡ形の半導体装置では、半
導体チップに形成された電極部と、該半導体チップが搭
載されたキャリア基板の表面に形成された電極部とがは
んだボールを介して電気的に接続されている。For example, in a BGA type semiconductor device, an electrode portion formed on a semiconductor chip and an electrode portion formed on a surface of a carrier substrate on which the semiconductor chip is mounted are electrically connected through solder balls. Have been.
【０００４】また、キャリア基板の裏面にも、はんだボ
ールがアレイ状に並べられており、それらはんだボール
を該半導体装置が実装されるプリント配線基板に形成さ
れた電極部に重合させ、リフローによりはんだボールを
溶融し、電気的に接続している。[0004] Solder balls are also arranged in an array on the back surface of the carrier substrate. The solder balls are superimposed on an electrode portion formed on a printed wiring board on which the semiconductor device is mounted, and the solder balls are reflowed. The ball is melted and electrically connected.
【０００５】なお、この種の半導体装置について詳しく
述べてある例としては、１９９５年１月１６日、株式会
社日経ＰＢ社発行、「日経エレクトロニクス」Ｐ７９〜
Ｐ８６があり、この文献には、ＣＳＰの半導体装置にお
ける構成などが記載されている。[0005] As an example describing this type of semiconductor device in detail, see "Nikkei Electronics", P79-Jan.
P86, and this document describes the configuration of a CSP semiconductor device.
【０００６】[0006]
【発明が解決しようとする課題】ところが、上記のよう
な半導体装置の実装技術では、次のような問題点がある
ことが本発明者により見い出された。However, it has been found by the present inventors that the following problems are encountered in the above-described semiconductor device mounting technology.
【０００７】近年、半導体装置の小型化に伴い、はんだ
バンプが設けられた半導体装置においても、ピンピッチ
が0.３ｍｍ程度以下の微細ピッチ化が進んでいる。この
場合、の半導体装置は、1.５ｃｍ×1.５ｃｍ程度の半導
体チップサイズに、ピン数が４００ピン程度以上が設け
られた多ピン化となる。In recent years, with the miniaturization of semiconductor devices, fine pitches having a pin pitch of about 0.3 mm or less have been advanced even in semiconductor devices provided with solder bumps. In this case, the semiconductor device has a multi-pin structure in which a semiconductor chip size of about 1.5 cm × 1.5 cm and a number of pins of about 400 or more are provided.
【０００８】このような半導体装置では、実装するプリ
ント配線基板などの反り量が大きい場合に、はんだバン
プの接続不良が発生する恐れがあるために、該プリント
配線基板の反り量を規定しており、半導体装置の製造歩
留まりが低くなってしまうという問題がある。In such a semiconductor device, when the amount of warpage of a printed wiring board to be mounted is large, there is a possibility that a connection failure of a solder bump may occur. Therefore, the amount of warpage of the printed wiring board is specified. In addition, there is a problem that the manufacturing yield of the semiconductor device is reduced.
【０００９】本発明の目的は、反り量の大きな基板であ
っても、確実に、かつ信頼性を確保しながらバンプ接続
することのできる半導体装置およびその実装方法を提供
することにある。An object of the present invention is to provide a semiconductor device capable of securely and reliably connecting bumps even on a substrate having a large amount of warpage, and a method of mounting the same.
【００１０】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述および添付図面から明らかに
なるであろう。The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
【００１１】[0011]
【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば、
以下のとおりである。SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.
【００１２】すなわち、本発明の半導体装置は、キャリ
ア基板の表面に半導体チップが搭載され、キャリア基板
の表面に設けられた接続用電極と半導体チップに設けら
れたチップ電極とがバンプを介して接続された構成から
なり、該バンプを、キャリア基板の反り量に見合った高
さに形成し、該バンプの高さをキャリア基板の反りによ
って生じる勾配に適合させたものである。That is, in the semiconductor device of the present invention, a semiconductor chip is mounted on a surface of a carrier substrate, and a connection electrode provided on the surface of the carrier substrate and a chip electrode provided on the semiconductor chip are connected via a bump. The bumps are formed at a height corresponding to the amount of warpage of the carrier substrate, and the height of the bumps is adapted to the gradient generated by the warpage of the carrier substrate.
【００１３】また、本発明の半導体装置は、キャリア基
板の表面に半導体チップが搭載され、キャリア基板の裏
面に外部接続用電極が設けられ、外部接続用電極にはバ
ンプが形成され、プリント配線基板の基板電極領域に形
成された基板電極にバンプが接続されて構成からなり、
該バンプを、プリント配線基板における基板電極領域の
反り量に見合った高さに形成し、バンプの高さを基板電
極領域の反りによって生じる勾配に適合させたものであ
る。Further, in the semiconductor device of the present invention, a semiconductor chip is mounted on a front surface of a carrier substrate, external connection electrodes are provided on a rear surface of the carrier substrate, bumps are formed on the external connection electrodes, and a printed wiring board is provided. The bumps are connected to the substrate electrodes formed in the substrate electrode region of
The bumps are formed at a height commensurate with the amount of warpage of the substrate electrode region on the printed wiring board, and the height of the bump is adapted to the gradient caused by the warpage of the substrate electrode region.
【００１４】さらに、本発明の半導体装置は、半導体チ
ップの主面にチップ電極が設けられ、チップ電極にバン
プが形成され、プリント配線基板の基板電極領域に形成
された基板電極にバンプが接続される構成であって、該
バンプを、プリント配線基板における基板電極領域の反
り量に見合った高さに形成し、バンプの高さを基板電極
領域の反りによって生じる勾配に適合させたものであ
る。Further, in the semiconductor device of the present invention, a chip electrode is provided on a main surface of a semiconductor chip, a bump is formed on the chip electrode, and the bump is connected to a substrate electrode formed in a substrate electrode region of a printed wiring board. The bumps are formed at a height commensurate with the amount of warpage of the substrate electrode region in the printed wiring board, and the height of the bump is adapted to the gradient caused by the warpage of the substrate electrode region.
【００１５】また、本発明の半導体装置の実装方法は、
基板電極領域に基板電極が形成されたプリント配線基板
を準備する工程と、キャリア基板の表面に半導体チップ
が搭載され、キャリア基板の裏面に外部接続用電極が設
けられ、外部接続用電極にプリント配線基板における基
板電極領域の反りに応じて高さの異なるバンプが形成さ
れた半導体装置を準備する工程と、バンプまたはバンプ
に対応するプリント配線基板の基板電極にフラックスを
塗布する工程と、バンプと基板電極とをリフローにより
接続する工程とを有するものである。Further, a method of mounting a semiconductor device according to the present invention
A step of preparing a printed wiring board having a substrate electrode formed in the substrate electrode area; mounting a semiconductor chip on the surface of the carrier substrate; providing an external connection electrode on the back surface of the carrier substrate; A step of preparing a semiconductor device in which bumps having different heights are formed in accordance with a warp of a substrate electrode region in a substrate; a step of applying flux to the bumps or a substrate electrode of a printed wiring board corresponding to the bumps; Connecting the electrodes by reflow.
【００１６】さらに、本発明の半導体装置は、基板電極
領域に基板電極が形成されたプリント配線基板を準備す
る工程と、主面にチップ電極が設けられ、そのチップ電
極にプリント配線基板における基板電極領域の反り量に
見合った高さにバンプが形成された半導体チップを準備
する工程と、バンプまたはバンプに対応する基板電極に
フラックスを塗布する工程と、バンプと基板電極とをリ
フローにより接続する工程とを有するものである。Further, in the semiconductor device according to the present invention, there is provided a step of preparing a printed wiring board having a substrate electrode formed in a substrate electrode region, a chip electrode being provided on a main surface, and the chip electrode being provided on the substrate electrode. A step of preparing a semiconductor chip having bumps formed at a height corresponding to the amount of warpage of the region, a step of applying flux to the bumps or a substrate electrode corresponding to the bumps, and a step of connecting the bumps and the substrate electrodes by reflow And
【００１７】また、本発明の半導体装置の実装方法は、
キャリア基板の表面に半導体チップが搭載され、キャリ
ア基板の表面に設けられた接続用電極と半導体チップに
設けられたチップ電極と接続されるバンプが、キャリア
基板の反り量に見合った高さに形成された半導体装置を
準備する工程と、バンプに対応した基板電極が形成さ
れ、半導体装置を実装するプリント配線基板を準備する
工程と、バンプまたはバンプに対応するプリント配線基
板の基板電極にフラックスを塗布する工程と、バンプと
基板電極とをリフローにより接続する工程とを有するも
のである。Further, a method of mounting a semiconductor device according to the present invention comprises:
The semiconductor chip is mounted on the surface of the carrier substrate, and the connection electrodes provided on the surface of the carrier substrate and the bumps connected to the chip electrodes provided on the semiconductor chip are formed at a height corresponding to the amount of warpage of the carrier substrate. A step of preparing a semiconductor device that has been formed, a step of forming a substrate electrode corresponding to the bump, and a step of preparing a printed wiring board on which the semiconductor device is mounted, and applying a flux to the bump or the substrate electrode of the printed wiring board corresponding to the bump. And connecting the bump and the substrate electrode by reflow.
【００１８】以上のことにより、多ピン、微細ピッチの
半導体装置を確実に実装することができるので、製造歩
留まりを大幅に向上することができる。また、反り量が
大きいプリント配線基板であっても接続信頼性を損なう
ことがないので、低コストのプリント配線基板を使用で
き、原価コストを低減することができる。As described above, a semiconductor device having a large number of pins and a fine pitch can be reliably mounted, so that the production yield can be greatly improved. Further, even if the printed wiring board has a large amount of warpage, the connection reliability is not impaired, so that a low-cost printed wiring board can be used, and the cost cost can be reduced.
【００１９】[0019]
【発明の実施の形態】以下、本発明の実施の形態を図面
に基づいて詳細に説明する。Embodiments of the present invention will be described below in detail with reference to the drawings.
【００２０】図１は、本発明の一実施の形態による半導
体装置の説明図、図２（ａ），（ｂ）は、本発明の実施
の形態による半導体装置をプリント配線基板に実装する
際の工程説明図、図３は、本発明の一実施の形態による
半導体装置を実装するプリント配線基板における反り量
分布の説明図、図４は、図３のプリント配線基板におけ
る反り量に見合ったはんだバンプが形成された半導体装
置の説明図、図５〜図７は、本発明の一実施の形態によ
るはんだバンプを金属マスクを用いた印刷法により形成
する場合の工程説明図、図８〜図１０は、本発明の一実
施の形態によるはんだバンプを転写法により形成する場
合の工程説明図である。FIG. 1 is an explanatory view of a semiconductor device according to an embodiment of the present invention, and FIGS. 2A and 2B are diagrams showing a case where the semiconductor device according to the embodiment of the present invention is mounted on a printed circuit board. FIG. 3 is an explanatory view of a process, FIG. 3 is an explanatory view of a distribution of warpage in a printed wiring board on which a semiconductor device according to an embodiment of the present invention is mounted, and FIG. FIGS. 5 to 7 are explanatory views of a process in which a solder bump according to an embodiment of the present invention is formed by a printing method using a metal mask, and FIGS. FIG. 4 is a process explanatory view in a case where a solder bump according to an embodiment of the present invention is formed by a transfer method.
【００２１】本実施の形態において、表面実装形の一種
であるＢＧＡ形の半導体装置１は、図１に示すように、
たとえば、ガラス基材からなるキャリア基板２が設けら
れている。このキャリア基板２の表面には、アレイ状に
並べられた接続用電極３、および配線パターンが形成さ
れている。In the present embodiment, a BGA type semiconductor device 1 which is a kind of surface mount type, as shown in FIG.
For example, a carrier substrate 2 made of a glass substrate is provided. On the surface of the carrier substrate 2, connection electrodes 3 arranged in an array and a wiring pattern are formed.
【００２２】キャリア基板２の表面には、絶縁樹脂４を
介して半導体チップ５が搭載されている。半導体チップ
５の主面には、アレイ状に接続用のチップ電極６が形成
されており、これらチップ電極６とキャリア基板２の接
続用電極部３とが、金またはニッケルなどの耐酸化性金
属からなるバンプ７を介してそれぞれ電気的に接続され
ている。On the surface of the carrier substrate 2, a semiconductor chip 5 is mounted via an insulating resin 4. On the main surface of the semiconductor chip 5, connection chip electrodes 6 are formed in an array, and these chip electrodes 6 and the connection electrode portions 3 of the carrier substrate 2 are formed of an oxidation-resistant metal such as gold or nickel. Are electrically connected via bumps 7 made of.
【００２３】キャリア基板２の裏面にも外部接続用端子
となる電極部８が所定のピッチでアレイ状に形成されて
おり、これら電極部８は、キャリア基板２に形成された
スルーホールを介して、該キャリア基板２の表面に形成
された所定の配線パターンにそれぞれ電気的に接続され
ている。Electrodes 8 serving as external connection terminals are also formed on the rear surface of the carrier substrate 2 in an array at a predetermined pitch, and these electrodes 8 are formed through through holes formed in the carrier substrate 2. Are electrically connected to predetermined wiring patterns formed on the surface of the carrier substrate 2, respectively.
【００２４】また、キャリア基板２の電極部８には、球
形のはんだからなるはんだバンプ（バンプ）９がそれぞ
れ形成されている。これらはんだバンプ９は、半導体装
置１が実装される実装基板の反り量に応じてバンプ高さ
（バンプの体積）が異なっている。Further, solder bumps (bumps) 9 made of spherical solder are formed on the electrode portions 8 of the carrier substrate 2. These solder bumps 9 have different bump heights (bump volumes) depending on the amount of warpage of the mounting substrate on which the semiconductor device 1 is mounted.
【００２５】さらに、半導体装置１は、高さのことなる
はんだバンプ９を電子部品などを実装するプリント配線
基板Ｐに形成された電極（基板電極）に重合させて搭載
し、リフローを行うことにより電気的に接続される。Further, the semiconductor device 1 is mounted by superposing solder bumps 9 having different heights on electrodes (substrate electrodes) formed on a printed wiring board P on which electronic components and the like are mounted, and performing reflow. Electrically connected.
【００２６】次に、本実施の形態における半導体装置１
の実装技術について説明する。Next, the semiconductor device 1 according to the present embodiment
Will be described.
【００２７】実装基板であるプリント配線基板Ｐの反り
量に見合った高さの異なるはんだバンプ９が形成された
半導体装置１は、図２（ａ）に示すように、はんだぬれ
を向上するため、フラックス槽ＦＳに貯められた液状の
フラックスＦに、はんだバンプ９が接触するように浸漬
して該はんだバンプ９にフラックスＦが塗布される。As shown in FIG. 2A, the semiconductor device 1 on which the solder bumps 9 having different heights corresponding to the amount of warpage of the printed wiring board P, which is a mounting board, is formed. The flux F is applied to the solder bump 9 by dipping the solder bump 9 into contact with the liquid flux F stored in the flux tank FS.
【００２８】ここでは、フラックス槽ＦＳにはんだバン
プ９を浸す、いわゆるフラックス転写法によりフラック
スＦを塗布したが、フラックスＦの塗布は、たとえば、
フラックス印刷法などの他の方法でもよい。Here, the flux F is applied by a so-called flux transfer method in which the solder bumps 9 are immersed in the flux tank FS.
Other methods such as a flux printing method may be used.
【００２９】このフラックス印刷法は、プリント配線基
板Ｐに形成された電極に対応した位置に孔が設けられた
金属マスクをプリント配線基板Ｐに搭載し、金属マスク
上にフラックスＦを供給し、ステンレスなどの板を押し
て数回移動させるスキージによってフラックスＦの塗布
を行う。In this flux printing method, a metal mask provided with holes at positions corresponding to the electrodes formed on the printed wiring board P is mounted on the printed wiring board P, and the flux F is supplied onto the metal mask, and The flux F is applied by a squeegee that moves several times by pressing a plate such as a sheet.
【００３０】そして、はんだバンプ９にフラックスＦが
塗布された半導体装置１は、図２（ｂ）に示すように、
プリント配線基板Ｐに搭載され、リフローによってはん
だづけを行い、フラックスの残留物を除去するための洗
浄が行われ、図１のように半導体装置１がプリント配線
基板Ｐに実装される。Then, the semiconductor device 1 in which the flux F is applied to the solder bumps 9 is, as shown in FIG.
The semiconductor device 1 is mounted on the printed wiring board P, soldered by reflow, and cleaned to remove the residue of the flux, and the semiconductor device 1 is mounted on the printed wiring board P as shown in FIG.
【００３１】ここで、はんだバンプ９について、図３
（ａ），（ｂ）、図４を用いて説明する。Here, the solder bump 9 is shown in FIG.
This will be described with reference to FIGS.
【００３２】プリント配線基板Ｐにおいて、半導体装置
１のはんだバンプ９が接続される基板電極が形成された
エリアを領域（基板電極領域）Ｒとする。この領域Ｒに
おいて、たとえば、反り量が０μｍの領域Ｒ１、反り量
が３０μｍの領域Ｒ２、反り量が６０μｍの領域Ｒ３、
および反り量が９０μｍの領域Ｒ４があるものとする。In the printed wiring board P, an area where a substrate electrode to which the solder bump 9 of the semiconductor device 1 is connected is formed is defined as a region (substrate electrode region) R. In this region R, for example, a region R1 having a warpage of 0 μm, a region R2 having a warpage of 30 μm, a region R3 having a warpage of 60 μm,
It is assumed that there is a region R4 having a warpage of 90 μm.
【００３３】この場合、プリント配線基板Ｐには、４つ
の反り量の異なる領域Ｒ１〜Ｒ４があるので、図４に示
すような４種類のはんだバンプ９ａ〜９ｄが、印刷法や
転写法、メッキ法などによって半導体装置１に形成され
ることになる。In this case, since the printed wiring board P has four regions R1 to R4 having different amounts of warpage, four types of solder bumps 9a to 9d as shown in FIG. It is formed on the semiconductor device 1 by a method or the like.
【００３４】領域Ｒ１では、反り量が０μｍなので、標
準のあるバンプ高さからなるはんだバンプ９ａが半導体
装置１に形成される。領域Ｒ２においては、反り量が３
０μｍなので、はんだバンプ９ａよりも３０μｍ高いは
んだバンプ９ｂが形成される。In the region R1, since the warpage is 0 μm, the solder bump 9a having a standard bump height is formed on the semiconductor device 1. In the region R2, the warpage amount is 3
Since the thickness is 0 μm, a solder bump 9b 30 μm higher than the solder bump 9a is formed.
【００３５】また、領域Ｒ３においては、反り量が６０
μｍなので、はんだバンプ９ａよりも６０μｍ高いはん
だバンプ９ｃが形成され、領域Ｒ４では、反り量が９０
μｍなので、はんだバンプ９ａよりも９０μｍ高いはん
だバンプ９ｄが形成される。In the region R3, the amount of warpage is 60.
μm, the solder bump 9c 60 μm higher than the solder bump 9a is formed, and in the region R4, the warp amount is 90 μm.
μm, the solder bump 9d is formed 90 μm higher than the solder bump 9a.
【００３６】さらに、前述した印刷法を用いたはんだバ
ンプの形成について説明する。この印刷法においては、
金属マスク方式がある。Further, formation of a solder bump using the above-described printing method will be described. In this printing method,
There is a metal mask method.
【００３７】金属マスク方式によるはんだバンプ９の形
成について説明する。The formation of the solder bump 9 by the metal mask method will be described.
【００３８】この場合、ステンレスなどからなる金属マ
スクＫＭには、図５に示すように、孔Ｈが形成されてい
る。これら孔Ｈは、アレイ状に並べられており、はんだ
バンプ９が形成される位置に設けられている。In this case, holes H are formed in the metal mask KM made of stainless steel or the like, as shown in FIG. These holes H are arranged in an array, and are provided at positions where the solder bumps 9 are formed.
【００３９】ここで、はんだバンプの高さは、孔Ｈの開
孔面積によって調整が行われる。はんだバンプを高くす
る場合には、孔Ｈの開孔面積を大きくし、はんだバンプ
を低くする場合には、孔Ｈの開孔面積を小さくする。Here, the height of the solder bump is adjusted by the area of the hole H. To increase the height of the solder bump, the opening area of the hole H is increased. To decrease the solder bump, the opening area of the hole H is reduced.
【００４０】そして、金属マスクＫＭの孔Ｈが対応する
キャリア基板２の電極部８とそれぞれ重合するように位
置決めし、キャリア基板２の裏面に金属マスクＫＭを搭
載する。金属マスクＫＭ上に、はんだペーストＨＰを供
給し、ステンレスなどの板を押しつけながら数回移動さ
せて、はんだペーストＨＰを孔Ｈに充填させ、金属マス
クＫＭ上の余分なはんだペーストＨＰをかき取るスキー
ジを行う。Then, the holes H of the metal mask KM are positioned so as to overlap with the corresponding electrode portions 8 of the carrier substrate 2, and the metal mask KM is mounted on the back surface of the carrier substrate 2. The solder paste HP is supplied onto the metal mask KM, and is moved several times while pressing a plate such as stainless steel to fill the hole H with the solder paste HP and scrape off the excess solder paste HP on the metal mask KM. I do.
【００４１】その後、図６に示すように、キャリア基板
２上に搭載された金属マスクＫＭをはぎ取り、図７に示
すように、キャリア基板２の電極部８に印刷されたはん
だペーストＨＰをリフローによって溶融させ、はんだバ
ンプ９を形成する。Thereafter, as shown in FIG. 6, the metal mask KM mounted on the carrier substrate 2 is peeled off, and as shown in FIG. 7, the solder paste HP printed on the electrode portions 8 of the carrier substrate 2 is reflowed. The solder bumps 9 are formed by melting.
【００４２】上記金属マスク方式では、孔Ｈの開孔面積
を可変することによってはんだバンプの高さを調整した
が、孔Ｈの深さを可変することにより、はんだバンプの
高さを調整するようにしてもよい。In the above-mentioned metal mask method, the height of the solder bump is adjusted by changing the opening area of the hole H. However, the height of the solder bump is adjusted by changing the depth of the hole H. It may be.
【００４３】さらに、転写によるはんだバンプ９の形成
について説明する。Further, formation of the solder bump 9 by transfer will be described.
【００４４】この場合、シリコン、あるいはガラスなど
からなるバンプ形成用基板ＢＫ上にフォトリソグラフィ
技術により、はんだバンプが形成される部分だけレジス
トが剥離されたレジストパターンを形成し、真空蒸着装
置によってその基板の孔にはんだを蒸着させる。ここで
も、はんだバンプの高さは、レジストが剥離された孔の
開口面積によって調整を行う。In this case, a resist pattern is formed on a bump formation substrate BK made of silicon, glass, or the like by photolithography, in which the resist is stripped only at the portions where the solder bumps are to be formed. The solder is deposited in the holes. Also in this case, the height of the solder bump is adjusted according to the opening area of the hole from which the resist has been removed.
【００４５】そして、バンプ形成用基板ＢＫのレジスト
を除去することによって、図８に示すように、基板上に
はんだバンプ９を形成する。その後、図９に示すよう
に、形成されたはんだバンプ９がキャリア基板２の電極
部８に重合するように位置決めしてバンプ形成用基板Ｂ
Ｋ上にキャリア基板２を搭載し、リフローによって溶融
させた後、図１０に示すように、バンプ形成用基板ＢＫ
をキャリア基板２から分離することによってはんだバン
プ９が形成される。Then, by removing the resist from the bump forming substrate BK, solder bumps 9 are formed on the substrate as shown in FIG. Thereafter, as shown in FIG. 9, the formed solder bumps 9 are positioned so as to overlap the electrode portions 8 of the carrier substrate 2, and the bump forming substrate B is formed.
After the carrier substrate 2 is mounted on K and melted by reflow, as shown in FIG.
Is separated from the carrier substrate 2 to form solder bumps 9.
【００４６】それにより、本実施の形態においては、半
導体装置１におけるはんだバンプ９を、プリント配線基
板Ｐの反りに見合った高さに調整して実装することによ
り、反りの大きなプリント配線基板Ｐであっても、接続
信頼性を損なうことなく確実に実装することができ、製
造歩留まりを大幅に向上することができる。Accordingly, in the present embodiment, the solder bumps 9 in the semiconductor device 1 are adjusted to a height corresponding to the warpage of the printed wiring board P and mounted, so that the printed wiring board P having a large warp is used. Even if there is, the mounting can be surely performed without deteriorating the connection reliability, and the manufacturing yield can be greatly improved.
【００４７】また、本実施の形態によれば、プラスティ
ック基板などの反り量が大きい低コストのプリント配線
基板を使用することもできるので、電子装置などの原価
コストを低減することができる。Further, according to the present embodiment, a low-cost printed wiring board having a large amount of warpage such as a plastic board can be used, so that the cost of electronic devices and the like can be reduced.
【００４８】さらに、本実施の形態では、プリント配線
基板Ｐの反り量に見合ったはんだバンプ９を形成した場
合について記載したが、たとえば、キャリア基板２と半
導体チップ５との接続において、バンプ７を球形のはん
だにより形成し、キャリア基板２の反りに見合った高さ
に形成するようにしてもよい。Further, in the present embodiment, the case where the solder bumps 9 are formed in accordance with the amount of warpage of the printed wiring board P has been described. For example, in the connection between the carrier substrate 2 and the semiconductor chip 5, the bumps 7 are formed. It may be formed of a spherical solder and formed at a height corresponding to the warpage of the carrier substrate 2.
【００４９】この場合、半導体装置１のはんだバンプ９
は、プリント配線基板Ｐに反りがなければ、キャリア基
板２の反りに見合った高さに形成し、プリント配線基板
Ｐに反りがある場合には、キャリア基板２とプリント配
線基板Ｐとの２つの基板の反りを考慮したはんだバンプ
９を形成すればよい。それにより、半導体装置１におけ
る接続信頼性をより向上することができる。In this case, the solder bump 9 of the semiconductor device 1
Is formed at a height commensurate with the warpage of the carrier substrate 2 if the printed wiring board P is not warped, and if the printed wiring board P is warped, the two portions of the carrier substrate 2 and the printed wiring board P What is necessary is just to form the solder bump 9 in consideration of the warpage of the substrate. Thereby, connection reliability in the semiconductor device 1 can be further improved.
【００５０】以上、本発明者によってなされた発明を発
明の実施の形態に基づき具体的に説明したが、本発明は
前記実施の形態に限定されるものではなく、その要旨を
逸脱しない範囲で種々変更可能であることはいうまでも
ない。Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.
【００５１】たとえば、前記実施の形態によれば、ＢＧ
Ａ形半導体装置について記載したが、ＣＳＰ、ＭＣＣ
（Ｍｉｃｒｏ Ｃａｒｒｉｅｒ）、ＰＧＡ（Ｐｉｎ Ｇ
ｒｉｄＡｒｒａｙ）、あるいはプリント配線基板に直接
半導体チップを実装する、いわゆるベアチップ実装など
のバンプを介してプリント基板に接続される構造の半導
体装置であればよい。For example, according to the above embodiment, BG
A type semiconductor device has been described, but CSP, MCC
(Micro Carrier), PGA (Pin G
(ridArray) or a semiconductor device having a structure in which a semiconductor chip is directly mounted on a printed wiring board, that is, a structure connected to the printed board via bumps such as so-called bare chip mounting.
【００５２】ＭＣＣ形の半導体装置１ａは、図１１に示
すように、ムライトセラミックなどからなるキャリア基
板１０の表面に半導体チップ１１が搭載されており、窒
化アルミニウムなどからなるキャップ１３によって封止
されている。キャリア基板１０と半導体チップ１１と
は、はんだバンプ１２によってフリップチップ接続され
ている。As shown in FIG. 11, an MCC type semiconductor device 1a has a semiconductor chip 11 mounted on a surface of a carrier substrate 10 made of mullite ceramic or the like, and is sealed by a cap 13 made of aluminum nitride or the like. I have. The carrier substrate 10 and the semiconductor chip 11 are flip-chip connected by solder bumps 12.
【００５３】キャリア基板１０の裏面には、はんだバン
プ１４がグリッド上に並べて形成されており、これらは
んだバンプ１４を介してプリント配線基板Ｐに半導体装
置１ａが実装される。On the back surface of the carrier substrate 10, solder bumps 14 are formed side by side on a grid, and the semiconductor device 1a is mounted on the printed wiring board P via these solder bumps 14.
【００５４】半導体装置１ａにおいても、はんだバンプ
１４が、プリント配線基板Ｐの反り量に見合った高さに
形成されており、反りの大きなプリント配線基板Ｐであ
っても、接続信頼性を損なうことなく確実に実装するこ
とができる。In the semiconductor device 1a as well, the solder bumps 14 are formed at a height commensurate with the amount of warpage of the printed wiring board P. Even if the printed wiring board P has a large warp, the connection reliability is impaired. Can be implemented without any problems.
【００５５】さらに、ＰＧＡ形の半導体装置１ｂは、図
１２に示すように、積層セラミック基板などからなるキ
ャリア基板１０ａの表面に半導体チップ１１ａが絶縁樹
脂１５を介して搭載されており、キャリア基板１０ａと
半導体チップ１１ａとが、はんだバンプ１２ａによって
フリップチップ接続されている。キャリア基板１０ａの
裏面には、垂直にアレイ状のリードピン１６が取り付け
られており、これらリードピン１６をプリント配線基板
Ｐに設けられたスルーホールなどに挿入することにより
実装される。Further, as shown in FIG. 12, the PGA type semiconductor device 1b has a semiconductor chip 11a mounted on a surface of a carrier substrate 10a made of a laminated ceramic substrate or the like via an insulating resin 15, and the carrier substrate 10a And the semiconductor chip 11a are flip-chip connected by the solder bumps 12a. Arrayed lead pins 16 are vertically attached to the back surface of the carrier substrate 10a, and the lead pins 16 are mounted by inserting these lead pins 16 into through holes provided in the printed wiring board P.
【００５６】半導体装置１ｂでは、はんだバンプ１２ａ
が、キャリア基板１０ａの反り量に見合った高さに形成
されており、キャリア基板１０ａの反り量が大きい場合
であっても接続信頼性を損なうことなく確実にフリップ
チップ接続を行うことができる。In the semiconductor device 1b, the solder bumps 12a
Is formed at a height commensurate with the amount of warpage of the carrier substrate 10a, so that even when the amount of warpage of the carrier substrate 10a is large, flip-chip connection can be reliably performed without impairing connection reliability.
【００５７】[0057]
【発明の効果】本願によって開示される発明のうち、代
表的なものによって得られる効果を簡単に説明すれば、
以下のとおりである。Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.
【００５８】（１）本発明によれば、プリント配線基板
の反りに見合った高さにバンプを形成して実装するの
で、反りの大きなプリント配線基板であっても、接続信
頼性を損なうことなく確実に実装する。(1) According to the present invention, bumps are formed at a height commensurate with the warpage of the printed wiring board and mounted, so that even if the printed wiring board has a large warpage, the connection reliability is not impaired. Make sure it is implemented.
【００５９】（２）また、本発明では、反り量が大きい
低コストのプリント配線基板であっても接続信頼性を低
下させずに半導体装置を実装できるので原価コストを低
減することができる。(2) According to the present invention, even a low-cost printed wiring board having a large amount of warpage can be mounted on a semiconductor device without deteriorating connection reliability, so that cost cost can be reduced.
【００６０】（３）さらに、本発明においては、上記
（１）、（２）により、半導体装置における製造歩留ま
りを大幅に向上することができる。(3) Further, in the present invention, the production yield of the semiconductor device can be greatly improved by the above (1) and (2).
【図１】本発明の一実施の形態による半導体装置の説明
図である。FIG. 1 is an explanatory diagram of a semiconductor device according to an embodiment of the present invention.
【図２】（ａ），（ｂ）は、本発明の実施の形態による
半導体装置をプリント配線基板に実装する際の工程説明
図である。FIGS. 2 (a) and 2 (b) are process explanatory diagrams when the semiconductor device according to the embodiment of the present invention is mounted on a printed wiring board.
【図３】本発明の一実施の形態による半導体装置を実装
するプリント配線基板における反り量分布の説明図であ
る。FIG. 3 is an explanatory diagram of a warpage amount distribution in a printed wiring board on which a semiconductor device according to an embodiment of the present invention is mounted.
【図４】図３のプリント配線基板における反り量に見合
ったはんだバンプが形成された半導体装置の説明図であ
る。FIG. 4 is an explanatory diagram of a semiconductor device in which solder bumps corresponding to the amount of warpage in the printed wiring board of FIG. 3 are formed.
【図５】本発明の一実施の形態によるはんだバンプを金
属マスクを用いた印刷法により形成する場合の工程説明
図である。FIG. 5 is an explanatory diagram of a process in a case where a solder bump according to an embodiment of the present invention is formed by a printing method using a metal mask.
【図６】図５に続くはんだバンプの形成工程の説明図で
ある。FIG. 6 is an explanatory diagram of a solder bump forming step following FIG. 5;
【図７】図６に続くはんだバンプの形成工程の説明図で
ある。FIG. 7 is an explanatory diagram of a solder bump forming step following FIG. 6;
【図８】本発明の一実施の形態によるはんだバンプを転
写法により形成する場合の工程説明図である。FIG. 8 is an explanatory view of a process when a solder bump is formed by a transfer method according to an embodiment of the present invention.
【図９】図８に続くはんだバンプの形成工程の説明図で
ある。FIG. 9 is an explanatory view of the solder bump forming step following FIG. 8;
【図１０】図９に続くはんだバンプの形成工程の説明図
である。FIG. 10 is an explanatory view of the step of forming solder bumps subsequent to FIG. 9;
【図１１】本発明の他の実施の形態による半導体装置の
一例を示す説明図である。FIG. 11 is an explanatory view showing an example of a semiconductor device according to another embodiment of the present invention.
【図１２】本発明の他の実施の形態による半導体装置の
他の例を示す説明図である。FIG. 12 is an explanatory diagram showing another example of a semiconductor device according to another embodiment of the present invention.
１，１ａ，１ｂ 半導体装置 ２ キャリア基板 ３ 接続用電極部 ４ 絶縁樹脂 ５ 半導体チップ ６ チップ電極 ７ バンプ ８ 電極部 ９ はんだバンプ（バンプ） １０，１０ａ キャリア基板 １１，１１ａ 半導体チップ １２ はんだバンプ １３ キャップ １４，１４ａ はんだバンプ １５ 絶縁樹脂 １６ リードピン Ｐ プリント配線基板 ＫＭ 金属マスク ＢＫ バンプ形成用基板 Ｈ 孔 Ｆ フラックス ＦＳ フラックス槽 ＨＰ はんだペースト DESCRIPTION OF SYMBOLS 1, 1a, 1b Semiconductor device 2 Carrier substrate 3 Connecting electrode part 4 Insulating resin 5 Semiconductor chip 6 Chip electrode 7 Bump 8 Electrode part 9 Solder bump (bump) 10, 10a Carrier substrate 11, 11a Semiconductor chip 12 Solder bump 13 Cap 14, 14a Solder bump 15 Insulating resin 16 Lead pin P Printed wiring board KM Metal mask BK Bump forming board H hole F Flux FS Flux tank HP Solder paste
Claims (6)
載され、前記キャリア基板の表面に設けられた接続用電
極と前記半導体チップに設けられたチップ電極とがバン
プを介して接続された半導体装置であって、前記バンプ
を、前記キャリア基板の反り量に見合った高さに形成
し、前記バンプの高さを前記キャリア基板の反りによっ
て生じる勾配に適合させたことを特徴とする半導体装
置。A semiconductor device in which a semiconductor chip is mounted on a surface of a carrier substrate, and a connection electrode provided on the surface of the carrier substrate and a chip electrode provided on the semiconductor chip are connected via bumps. A semiconductor device, wherein the bump is formed at a height corresponding to the amount of warpage of the carrier substrate, and the height of the bump is adapted to a gradient caused by the warpage of the carrier substrate.
載され、前記キャリア基板の裏面に外部接続用電極が設
けられ、前記外部接続用電極にはバンプが形成され、プ
リント配線基板の基板電極領域に形成された基板電極に
前記バンプが接続される半導体装置であって、前記バン
プを、前記プリント配線基板における基板電極領域の反
り量に見合った高さに形成し、前記バンプの高さを前記
基板電極領域の反りによって生じる勾配に適合させたこ
とを特徴とする半導体装置。2. A semiconductor chip is mounted on a front surface of a carrier substrate, an external connection electrode is provided on a rear surface of the carrier substrate, and a bump is formed on the external connection electrode. A semiconductor device in which the bump is connected to the formed substrate electrode, wherein the bump is formed at a height commensurate with the amount of warpage of the substrate electrode region on the printed wiring board, and the height of the bump is set at the substrate. A semiconductor device adapted to a gradient generated by warpage of an electrode region.
られ、前記チップ電極にはバンプが形成され、プリント
配線基板の基板電極領域に形成された基板電極に前記バ
ンプが接続される半導体装置であって、前記バンプを、
前記プリント配線基板における基板電極領域の反り量に
見合った高さに形成し、前記バンプの高さを前記基板電
極領域の反りによって生じる勾配に適合させたことを特
徴とする半導体装置。3. A semiconductor device in which a chip electrode is provided on a main surface of a semiconductor chip, a bump is formed on the chip electrode, and the bump is connected to a substrate electrode formed in a substrate electrode region of a printed wiring board. Then, the bumps
A semiconductor device, wherein the height is adjusted to a height corresponding to the amount of warpage of a substrate electrode region in the printed wiring board, and the height of the bump is adapted to a gradient caused by the warpage of the substrate electrode region.
リント配線基板を準備する工程と、 キャリア基板の表面に半導体チップが搭載され、前記キ
ャリア基板の裏面に外部接続用電極が設けられ、前記外
部接続用電極に前記プリント配線基板における基板電極
領域の反りに応じて高さの異なるバンプが形成された半
導体装置を準備する工程と、 前記バンプまたは前記バンプに対応する前記プリント配
線基板の基板電極にフラックスを塗布する工程と、 前記バンプと前記基板電極とをリフローにより接続する
工程とを有することを特徴とする半導体装置の実装方
法。4. A step of preparing a printed wiring board having a substrate electrode formed in a substrate electrode region, mounting a semiconductor chip on a surface of a carrier substrate, and providing an external connection electrode on a back surface of the carrier substrate. A step of preparing a semiconductor device in which bumps having different heights are formed on the external connection electrodes in accordance with the warpage of the substrate electrode region in the printed wiring board; and a substrate electrode of the printed wiring board corresponding to the bumps or the bumps A step of applying a flux to the substrate, and a step of connecting the bump and the substrate electrode by reflow.
リント配線基板を準備する工程と、 主面にチップ電極が設けられ、前記チップ電極に前記プ
リント配線基板における基板電極領域の反り量に見合っ
た高さにバンプが形成された半導体チップを準備する工
程と、 前記バンプまたは前記バンプに対応する前記基板電極に
フラックスを塗布する工程と、 前記バンプと前記基板電極とをリフローにより接続する
工程とを有することを特徴とする半導体装置の実装方
法。5. A step of preparing a printed wiring board having a board electrode formed in the board electrode area, and providing a chip electrode on a main surface, wherein the chip electrode corresponds to the amount of warpage of the board electrode area in the printed wiring board. Preparing a semiconductor chip having bumps formed at different heights; applying flux to the bumps or the substrate electrode corresponding to the bumps; connecting the bumps and the substrate electrodes by reflow. A method for mounting a semiconductor device, comprising:
載され、前記キャリア基板の表面に設けられた接続用電
極と前記半導体チップに設けられたチップ電極と接続さ
れるバンプが、前記キャリア基板の反り量に見合った高
さに形成された半導体装置を準備する工程と、 バンプに対応した基板電極が形成され、前記半導体装置
を実装するプリント配線基板を準備する工程と、 前記バンプまたは前記バンプに対応する前記プリント配
線基板の基板電極にフラックスを塗布する工程と、 前記バンプと前記基板電極とをリフローにより接続する
工程とを有することを特徴とする半導体装置の実装方
法。6. A semiconductor chip is mounted on a surface of a carrier substrate, and a connection electrode provided on a surface of the carrier substrate and a bump connected to a chip electrode provided on the semiconductor chip are warped on the carrier substrate. A step of preparing a semiconductor device formed at a height commensurate with the amount; a step of forming a substrate electrode corresponding to the bump, and preparing a printed wiring board on which the semiconductor device is mounted; and a step corresponding to the bump or the bump. A method of mounting a semiconductor device, comprising: applying a flux to a substrate electrode of the printed wiring board; and connecting the bump and the substrate electrode by reflow.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25798999A JP2001085558A (en) | 1999-09-10 | 1999-09-10 | Semiconductor device and mountig method therefor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25798999A JP2001085558A (en) | 1999-09-10 | 1999-09-10 | Semiconductor device and mountig method therefor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2001085558A true JP2001085558A (en) | 2001-03-30 |
Family
ID=17314009
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25798999A Pending JP2001085558A (en) | 1999-09-10 | 1999-09-10 | Semiconductor device and mountig method therefor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2001085558A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007201469A (en) * | 2006-01-23 | 2007-08-09 | Samsung Electro Mech Co Ltd | Printed circuit board for semiconductor package and manufacturing method thereof |
| JP2009302539A (en) * | 2008-06-16 | 2009-12-24 | Intel Corp | Processing method for low profile solder grid array, device, and computer system |
| WO2011102101A1 (en) | 2010-02-17 | 2011-08-25 | Canon Kabushiki Kaisha | Stacked semiconductor device |
| CN113053845A (en) * | 2019-12-27 | 2021-06-29 | 意法半导体有限公司 | WLCSP package with different solder volumes |
-
1999
- 1999-09-10 JP JP25798999A patent/JP2001085558A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007201469A (en) * | 2006-01-23 | 2007-08-09 | Samsung Electro Mech Co Ltd | Printed circuit board for semiconductor package and manufacturing method thereof |
| JP2009302539A (en) * | 2008-06-16 | 2009-12-24 | Intel Corp | Processing method for low profile solder grid array, device, and computer system |
| JP2012151487A (en) * | 2008-06-16 | 2012-08-09 | Intel Corp | Processing method and apparatus for flat solder grid array and computer system |
| WO2011102101A1 (en) | 2010-02-17 | 2011-08-25 | Canon Kabushiki Kaisha | Stacked semiconductor device |
| CN113053845A (en) * | 2019-12-27 | 2021-06-29 | 意法半导体有限公司 | WLCSP package with different solder volumes |
| EP3852139A3 (en) * | 2019-12-27 | 2021-09-08 | STMicroelectronics Pte Ltd. | Wafer level chip scale package with co-planar bumps with different solder heights and corresponding manufacturing method |
| US11581280B2 (en) | 2019-12-27 | 2023-02-14 | Stmicroelectronics Pte Ltd | WLCSP package with different solder volumes |
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