JP2001068993A - Information processing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce power consumption by relieving a load of a main processor to reconfigure a programmable logic circuit and to enhance the performance of the system as a whole. SOLUTION: For example, a local memory 22 stores information of a circuit in use and a sequence in advance. Furthermore, a header part of processing data given from a CPU 11 includes information to specify first circuit information used to reconfigure a programmable logic circuit 21. A programmable logic circuit interface 23 interprets the header part to specify the first circuit information, a programmable logic circuit 21 reconfigures the processing circuit to process the processing data. Moreover, the processing circuit is reconfigured from the circuit information in the sequence stored in the local memory 22 to execute the processing in the processing circuit sequentially. Thus, the CPU 11 needs not conduct processing of the reconfiguration.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an information processing system capable of processing a part of processing by an application program by a programmable logic circuit whose circuit configuration can be reconfigured. In particular, the present invention relates to a method for continuously executing circuit reconfiguration and processing.

[0002]

2. Description of the Related Art In the field of digital circuit devices, in particular, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs) and programmable logic devices (PGAs) have been developed in order to shorten the development period of products.
2. Description of the Related Art Programmable logic circuits including LDs) are widely used. These programmable logic circuits can freely configure the internal logic circuits and the connections between the logic circuits by reading circuit information describing the logic circuits. For this reason, using a programmable logic circuit has the advantage that the time required to manufacture an integrated circuit, which conventionally required several weeks to several months after the completion of circuit design, is not required. In particular, an electrically reconfigurable programmable logic device as described in, for example, U.S. Pat. No. 4,700,187 can change a circuit once manufactured as many times as necessary. It is becoming more and more widely used.

[0003] Recently, logic circuits have become more and more complex, and the circuit scale has increased to a level that cannot be realized by a single programmable logic circuit. As one method for solving this problem, it has been proposed to reconfigure a programmable logic circuit during processing in order to realize different logic circuits at different times. By using this method, there is an advantage that various processes can be performed at relatively high speed even when the size of a circuit that can be built in is limited due to the small size of the device such as a portable information terminal.

However, when reconfiguring a programmable logic circuit, it is necessary to read the circuit information of the entire circuit again, so that there is a disadvantage that the reconfiguration takes time. Further, reconfiguring in the middle of the process means that the process is temporarily suspended, the data at that time is saved in a storage device outside the programmable logic circuit, new circuit information is read and reconfigured, and the data before reconfiguration is reconstructed. And extra processing of inputting new data for reconstruction is required.

[0005] To solve this problem, for example, "CONFIGURABLE LOGI" manufactured by Atmel, USA
C "and a programmable logic circuit described in a data book named Xilinx" THE "
There is a programmable logic circuit or the like described in a data book named "PROGRAMMABLELOGIC". These programmable logic circuits have a data storage device for storing data, and can read a part of the circuit information from an external storage device and partially reconfigure the circuit even during operation of the circuit. This keeps the time for reconfiguration to a minimum.

When such a programmable logic circuit is used in an information processing system, for example, a control device such as a CPU must perform processing of an application and the like and reconfiguration of the programmable logic circuit at high speed and efficiently. There is. That is, the control device extracts circuit information for forming a desired logic circuit from a storage destination, combines a plurality of pieces of circuit information as necessary, and reconfigures the desired logic circuit in the programmable logic circuit. In parallel with this, it is necessary to execute the processing of the application, and both processing must be performed quickly and efficiently.

[0007] The information system for performing processing while reconfiguring a programmable logic circuit based on a plurality of circuit information described above can be used by connecting to a network. As an example, there is a “reconfigurable network computer” disclosed in Japanese Patent Application Laid-Open No. 10-78932.

FIG. 17 is a block diagram showing an example of a conventional information processing system. In the figure, 51 is an application server, 52 and 53 are client computers, 5
4 is a communication network, 55 is a main processor, 56
Is an extension hardware, 57 is an application program, 58 is an extension code, 59 is a main processor code, 60 is an OS, and 61 is a code selection function. The information processing system includes a plurality of computers connected by a communication network 54.

The application server 51 is a computer that distributes application programs. In addition, the client computers 52 and 53 transmit the application program 5 from the application server 51.
7 is downloaded and executed. A main processor 55 is mounted on each of the client computers 52 and 53, and can execute an application program 57 under the control of the OS 60. Further, the client computer 52 has extended hardware 56 separately from the main processor 55. The extended hardware 56 is equipped with the above-described programmable logic circuit, and can change its function as needed by a program and can be reconfigured.

[0010] In the application program 57 stored in the application server 51, some of its functions are provided by a program code (extended code 58) of the extended hardware 56 and a code (main processor code) of the main processor 55 of the client computer. 59) is included.

The client computers 52, 5
The third OS 60 has a code selection function 61 for selecting a code suitable for each hardware configuration.
The code selection function 61 determines whether or not the extension hardware 56 is implemented. If the extension hardware 56 is implemented as in the client computer 52, the extension code 58 is read from the application program 57. And executed by the extended hardware 56. When the client computer 53 does not have extended hardware, the main processor code 59 is selected and executed.

In another configuration, the function realized by the extended hardware 56 is realized as an extended function or a dynamic library of the OS 60 which can be dynamically added / deleted later on the client computer. Register the type of extended function or dynamic library used during processing. OS60,
If the extension function or dynamic library exists on the client computer, it is used. If not, the required extension function or dynamic library is transferred from the application server 51 on the communication network 54 and used. .

Further, the main processor code 59 and the extension code 58 are not integrated, but individual codes are provided on the application server 51 for each extension function or dynamic library of the application program 57 or the OS 60. ing.

If the configuration of the programmable logic circuit constituting the extension hardware 56 differs between client computers, the extension code 58 is described by using a Boolean formula or the like to describe the function of the logic circuit having an appropriate number of gates and input / output terminals. It consists of the basic modules and the codes that represent the connections between them. In the case of a function for assigning each basic module as a basic program of a programmable logic circuit, and in the case of a large extension code extending over a plurality of programmable logic chips, the basic module is divided according to the degree of connection, and arranged on each programmable logic chip. Application server 5
1 or on the client computer.

A hardware resource management function for reusing the unnecessary hardware resources for another application program so that a plurality of applications using the extended hardware 56 can be executed simultaneously; It has a code replacement function that replaces extended codes that cannot fit in by time sharing. A priority value appropriately set for each application program executed on the client computer, a processing capability value of the main processor 55, a processing capability value of the extended hardware 56, a hardware resource amount, and a processing capability value required for exchanging codes. Based on the above, it has an extended hardware management function for selecting a plurality of application programs that cannot fit in the hardware resources. When a plurality of applications use the same extension code in the extension hardware 56 at the same time, the function is shared by switching only the internal state in a time division manner.

As described above, when an application program distributed from an application server is executed on a client computer side on a computer connected via a network, the function is changed as needed by the program, and reconfigurable extended hardware is used. Installed on the client computer. Then, the application program stored in the application server includes a main processor code and an extension code. At the time of execution, an OS that determines the presence or absence and type of extended hardware
The code selection function changes the configuration of the extended hardware on the client computer side to make the configuration suitable for processing. This allows the client computer to process the application program at high speed.

Conventionally, when trying to start a new service that requires special hardware on the client computer side on a network, the user on the client computer side needs to introduce new hardware for that purpose. Was. Also, service providers provided new services only to some users with new hardware. However, as described above, in a configuration that has extended hardware with programmable logic circuits, it is possible to start a new service without introducing new hardware by reconfiguring the programmable logic circuits. Becomes

As described above, when the processing is executed while reconfiguring the circuit by using the programmable logic circuit as the extended hardware, control by the CPU is required. For example, a processing method in which a main processor is always operated is used even when a processing flow is determined in an application program and a functional circuit used for the processing can be selected and designated in advance. In particular,
When extended hardware is installed in a client computer as in the above-described system example, control for reconfiguring with extended code is performed by the main processor of the client computer. For this reason, a necessary extension code is associated with the main program of the application program in advance, and each time the extension hardware is reconfigured, the extension is performed using the extension code under the control of the main processor. For this reason, when executing an application program while frequently reconfiguring a wide variety of extended hardware, the main processor always monitors the progress of processing,
It is necessary to perform control for reconfiguration, and there is a disadvantage that the load on the main processor increases. Further, it is necessary to operate the main processor together with the operation of the extended hardware, and there is a disadvantage that the power consumption of the entire client increases.

As described above, there is a problem that the processing load of the main processor is constantly generated by the control for reconfiguring the circuit, so that the power consumption is increased by combining the main processor and the extended hardware. is there. In addition, there is a disadvantage that the performance of the whole system is reduced due to the load of the main processor for reconfiguring the circuit.

Next, a new device technology for a programmable logic circuit will be described. 2. Description of the Related Art Programmable logic circuits have begun to be used in reconfigurable computing, in which processing circuits adapted to the processing of applications are configured on programmable logic circuits, and high-speed processing is realized using the dedicated processing circuits. In reconfigurable computing, circuit information of a plurality of processing circuits required for application processing is stored in a storage device in advance, and the circuit information read from the storage device is written to a programmable logic circuit as needed. , And generate a circuit required at that time. This technology is called cache logic technology or virtual logic technology.

The cache logic technique is a time-division driving technique in which different circuits are formed as needed on the same programmable logic circuit. As a result, by using a programmable logic circuit having a small circuit scale, a circuit larger than the circuit scale can be realized, and the size and cost of the circuit device can be reduced. However, depending on the size of the circuit information to be written in the programmable logic circuit, there is a problem that the reconfiguration time of the circuit becomes longer and the effect of the reconfigurable computing of realizing high-speed processing using a dedicated processing circuit is impaired. .

One solution to this problem is a device technology called a multi-context technology. That is, a memory for storing a plurality of pieces of circuit information is provided in the programmable logic circuit, and the memory is switched as necessary to reconfigure the circuit, so that the reconfiguration time of the circuit can be significantly reduced.

One of the conventional examples of the multi-context technique is “A First Generator” of FPD'95.
ion DPGA Implementation ”. FIG. 18 is an explanatory diagram of an example of a logic cell structure of the DPGA. In the figure, reference numeral 71 denotes a DRAM,
72 and 75 are multiplexers, 73 is a look-up table, and 74 is a flip-flop. As shown in FIG. 18, a DPGA logic cell stores four sets of configurations.
It comprises a × 32-bit DRAM 71, four 8-input multiplexers 72, a 4-input look-up table 73, a flip-flop 74, and a multiplexer 75 for switching the output. Of the outputs of the 32-bit DRAM 71, 12 bits determine the state of the four 8-input multiplexer 72, 16 bits determine the state of the 4-input look-up table 73, 1 bit determines the state of the multiplexer 75, and the remaining 3 bits determine the state of the multiplexer 75. Pending 4 sets of DRAM7
1 stores different data, and different circuits can be configured by switching memory outputs.

The multi-context technique can greatly reduce the circuit reconfiguration time. Further, the load on the input / output bus lines when transferring circuit information for reconfiguring the circuit to the programmable logic circuit can be reduced, which is advantageous for high speed and low power consumption. However, a memory circuit area for storing circuit information needs to be integrally formed with the programmable logic circuit, which has a disadvantage that the circuit scale of the entire programmable logic circuit when integrated is increased.

[0025]

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and can greatly reduce the load on a main processor for reconfiguring a programmable logic circuit, thereby reducing power consumption. It is an object of the present invention to provide an information processing system in which the power consumption is increased and the performance of the entire system is improved by effectively utilizing a main processor.

[0026]

In general, the flow of processing is determined in an application program.
In the case where a processing circuit used for the selection can be selected and designated in advance by a plurality of types of combinations, or in the case of a predetermined repeated processing in the same order as a unit, the circuit information to be used and the order can be determined in advance. The present invention makes use of this, and stores circuit information for configuring a processing circuit in the programmable logic circuit in advance in the circuit information holding unit in order. Then, the control means such as the CPU includes information for specifying circuit information to be used, for example, in a header portion of processing data to be processed by the programmable logic circuit,
Request processing. The interface means specifies the first circuit information to be used for the reconfiguration of the programmable logic circuit from, for example, a header part of the given processing data, and the order in which the circuit information is held in the circuit information holding means from the specified circuit information. Then, the circuit information is extracted, the programmable logic circuit is reconfigured to configure a processing circuit, and the configured processing circuit processes the processing data.

Thus, in the programmable logic circuit, the reconfiguration and execution of the processing circuit are automatically performed in a preset order. Therefore, a control unit such as a CPU only issues an execution instruction first, and does not need to issue a reconfiguration or execution instruction of a programmable logic circuit that is performed in order thereafter. As a result, the number of processing steps for controlling the programmable logic circuit by the control means such as the CPU can be significantly reduced, and the speed can be increased, and the power consumption can be significantly reduced. At the same time, the overall performance of the information processing system including the programmable logic circuit can be improved.

[0028]

FIG. 1 is a block diagram showing an embodiment of an information processing system according to the present invention. In the figure, 1 is an information processing system, 2 is a network, 3 is an external device, 11
Is a CPU, 12 is a host bus, 13 is a chip set, 1
4 is a main memory, 15 is a system bus, 16 is a hard disk interface, 17 is a hard disk drive, 18 is a communication interface, 19 is an extended hardware unit, 21 is a programmable logic circuit, 22 is a local memory, 23 is a programmable logic circuit interface, 24 is an external input / output interface.

In the information processing system 1, the CPU 11
A main memory 14 composed of a DRAM is connected to the host bus 12 via a memory controller (not shown) included in the chipset 13. Host bus 1
2 is connected to the system bus 15 via a bus bridge (not shown) included in the chipset 13. As the system bus 15, for example, a PCI bus, an ISA bus, or various other buses can be used. For example, when a PCI bus is used as the system bus 15, the chipset 13 only needs to include a host-PCI bridge.

In this example, a hard disk drive 17 is connected to the system bus 15 via a hard disk interface 16.
Is connected to the network 2 via the. Further, an extension hardware unit 19 is connected, and the external device 3 is connected via the extension hardware unit 19. Of course, various other devices may be connected to the system bus 15 directly or via an interface, and the connection of the hard disk and the network is arbitrary.

In this example, the hard disk drive 17
Stores application programs. The application program is loaded from the hard disk drive 17 to the main memory 14 via the hard disk interface 16, the system bus 15, and a bus bridge (not shown) included in the chipset 13 and executed by the CPU 11.

The communication interface 18 is a LAN
And data can be transferred to and from various devices via a network 2 such as the Internet. CP
The application program executed by U11 can access information stored in, for example, a storage device connected to the network 2 by performing communication through the communication interface 18.
Various application programs and data can be obtained. In this case, the application program transferred via the communication interface 18 connected to the network 2 is stored in the main memory 14 and executed, or the application program is directly transmitted from the system bus 15 to the programmable logic circuit 21 via the programmable logic circuit interface 23. You can also transfer.

The extended hardware section 19 has a programmable logic circuit 21, a local memory 22, and a programmable logic circuit interface 23. In this example, the external input / output interface 24 is also provided in the extended hardware unit 19. The function of the programmable logic circuit 21 can be changed and reconfigured at any time by changing circuit information. The programmable logic circuit 21 is connected to the system bus 15 via a programmable logic circuit interface 23. In this example, the external device 3 is also connected to the external device 3 via the external input / output interface 24, and the external device 3 can be controlled by processing in the programmable logic circuit 21.

The local memory 22 can hold processing data to be processed by the programmable logic circuit 21, intermediate processing data after processing, and the like. It also functions as circuit information holding means for holding circuit information to be used in advance and the order.

Programmable logic circuit interface 2
Reference numeral 3 is for performing data transfer and control between the CPU 11, the main memory 14, the local memory 22, and the programmable logic circuit 21 via the system bus 15. Also, the programmable logic circuit interface 23
Has a function of specifying the first circuit information used for reconfiguring the programmable logic circuit from the transferred processing data. When the first circuit information is added, for example, as header information of the processing data, it can be realized by interpreting the header information of the processing data. Also,
It also includes circuit information for circuit reconfiguration, processing data, and a marker detection function of EOF added to the end of intermediate processing data. Further, circuit information is sequentially taken out from the local memory 22 based on the specified first circuit information,
The programmable logic circuit 21 is sequentially reconfigured to configure a processing circuit, and the configured processing circuit processes the processing data. Further, transfer of processing data and intermediate processing data between the local memory 22 and the programmable logic circuit 21 is also performed.

The circuit information used in advance may be stored in, for example, the main memory 14 or the hard disk drive 17. In this case, the programmable logic circuit interface 23 only needs to have a function of transferring data to the main memory 14 or the hard disk drive 17 without operating the CPU 11. For example, the main memory 14 and the local memory 22 may be configured to be accessible in the same memory space, and may be configured to be accessible without being aware of which memory is being used.

The extension hardware unit 19 can be integrated to reduce the line load of the input / output unit, and the speed can be reduced and the power consumption can be reduced by using a dedicated bus. it can.

FIG. 2 is a plan view showing an example of the programmable logic circuit, and FIG. 3 is a block diagram showing an example of the internal structure. In the figure, 31 is a logic cell, 32 is a wiring area, 33 is an input / output terminal, 41 is a configuration memory, and 42 is a circuit element. The programmable logic circuit 21 includes a configuration memory 41 for storing circuit information, a circuit element 42 including a logic cell 31 and a wiring area 32, and an input / output terminal 33.

The configuration memory 41 stores E
It is composed of rewritable memory elements such as EPROM and SRAM. The circuit information is composed of address and data pairs. When an address is given to the configuration memory 41 and the data paired with the address is stored in a memory cell corresponding to the address, the circuit configuration in the logic cell 31 and the logic cell 31 and the input / output terminal 33 are stored in accordance with the data. Are reconfigured in the connection state of the wiring region 32 connecting the two. Configuration memory 41
Can be partially reconfigured even when the programmable logic circuit 21 is operating.

Data (processing data and intermediate processing data) to be processed is input to the circuit element 42 reconfigured in the programmable logic circuit 21 via the input / output terminal 33, and the processing result (intermediate processing data) Is output. The logic cell of the data input destination and the logic cell of the data output source are
The application program specifies the control code indicating the cell coordinates corresponding to the position of the logic cell.

With the above system configuration, the method of inputting / outputting processing data by the programmable logic circuit 21 is as follows.
The following processing forms are available. As data,
There are streaming data such as multimedia images and audio. Data input to the information system 1 via the network 2 is processed by the processing circuit reconfigured in the programmable logic circuit 21 via the system bus 15. Data stored in a storage device such as the hard disk drive 17 is processed by the processing circuit reconfigured in the programmable logic circuit 21 via the system bus 15. Data temporarily stored in the main memory 14, such as data transferred from an external storage device or processing results of an application, is processed by the processing circuit reconfigured in the programmable logic circuit 21 via the system bus 15. I do. The data stored in the local memory is processed by the processing circuit reconfigured in the programmable logic circuit 21 via the programmable logic circuit interface 23.

Next, the operation of the information processing system according to the embodiment of the present invention will be described. In the case where the processing flow is determined in the application program and the functional circuit used for that can be selected and designated in advance by a combination of a plurality of types, or when the processing is repeated in the same order as a unit, it is used in advance. Circuit information and order can be determined. Therefore, before the processing of the application is started, circuit information to be used and information such as an order are registered in advance in the local memory 22 or the like as a reference table. If it is not possible to specify what processing is to be performed after an arbitrary processing in a completely uncertain order, the main processor may perform control each time, and therefore, is not included here. .

FIG. 4 is an explanatory diagram of an example of the reference table. In the example shown in FIG. 4, the processing step No. indicating the order of the processing circuits. Corresponding to the pointer indicating the start address in the memory where the circuit information for reconfiguration is stored,
A reference table is formed by a pointer indicating a start address in the memory for storing the intermediate processing data allocated corresponding to the case where the intermediate processing is to be performed, and information on the number of circuits that can be simultaneously reconfigured in the programmable logic circuit 21. ing.

When the result of processing by the i-th processing circuit in the application processing is processed by the next (i + 1) -th processing circuit, data output from the i-th processing circuit is intermediate processing data. The result of processing at the last M-th becomes final output data. The start address pointer of the memory for storing the intermediate processing data is the pointer P in FIG.
di. Since the final data may be used by another application, the final data may be stored in the intermediate processing data memory.

The number of circuits Ni that can be simultaneously reconfigured for the processing circuit to be reconfigured according to the circuit scale of the programmable logic circuit is the maximum number of simultaneously reconfigurable circuits from the i-th circuit. As a mode for reconfiguring the circuit corresponding to Ni, the single configuration mode is automatically set in the case of one, and the single configuration mode or the continuous configuration mode can be selected in the case of a plurality. This can be selected and designated by the CPU at the start of the application.

The reference table as shown in FIG. 4 includes the type and size of the programmable logic circuit 21 used in the information processing system when the application is executed, the memory size of the main memory 14 and the local memory 22, and the like. Is generated by the CPU 11 in consideration of the above. Alternatively, of course, when a predetermined process is performed by the same system, it is not necessary to create this reference table every time the process is executed, and the reference table can be prepared in advance.

FIG. 5 is an explanatory diagram of processing data and circuit information and a memory address space for storing them. The information of the reference table as shown in FIG. 4 can be added, for example, to the header part of the processing data as shown in FIG. In the programmable logic circuit interface 23, when processing data is received, the header part is analyzed, and these pieces of information are taken out, and a reference table can be created. When executing a certain processing step i based on such a reference table, the processing step No. A pointer Pci for circuit information and a pointer Pdi for intermediate processing data associated with i are allocated. Depending on the order of processing, memory allocation efficiency can be improved by allocating by overwriting using the same pointer.

The memory address space shown in FIG.
The memory address space of the local memory 22, or
It may be a memory address space in which the main memory 14 and the local memory 22 are integrated. In the latter case, for example, an area for storing circuit information and intermediate processing data may be secured in the main memory 14.

In the order of the circuit information described above, as shown in FIG. From the first 0 to M
The operation at the time of performing the i-th process in the case of the (M + 1) th step up to the number is described. Let Pci be the start address pointer of the memory that stores the circuit information to be reconfigured. The start address pointer of the memory for storing the intermediate processing data is Pdi. Furthermore, regarding the processing circuit to be reconfigured, according to the circuit scale of the programmable logic circuit,
The number of circuits that can be reconfigured simultaneously is Ni.

The processing data file and the circuit information of the application are read out, and the circuit information is allocated to the memory space before executing the application program. The CPU 11 adds the above four types of information to the header of the processing data file of the application. The processing data file and the circuit information are stored in, for example, a storage device connected to the network 2, a storage device such as a hard disk drive 17 in the information processing system 1, the main memory 14, or the local memory 2.
2, etc., may be stored in any storage device.

When the execution of the application program is a CP
When started by U11, the processing data file is transferred to the programmable logic circuit interface 23, and the information added to the header is interpreted. Reconfiguration of the processing circuit for the programmable logic circuit 21 is performed by the first circuit information, and EOF indicating the end of the circuit information is performed.
The reconstruction is completed by the marker of. The EOF marker is detected by the programmable logic circuit interface 23, the data portion following the header portion is transferred, and the data processing in the reconfigured processing circuit proceeds.

When the processed data is used in a processing circuit for reconstructing the next data, the processed data is temporarily stored as intermediate processing data in the area allocated in the memory space. Then, after reconfiguring the next processing circuit, the intermediate processing data is input to the newly reconfigured processing circuit, and the data processing proceeds. The final data is transferred to the external device 3 via, for example, the external input / output interface 24,
Alternatively, the main memory 14 and the hard disk drive 1
7. The data is transferred to a storage device or the like connected to the network 2. Alternatively, it may be stored similarly to the intermediate processing data.

As described above, the reconfiguration of the circuit and the data processing are sequentially performed by the CPU 11 performing the initial start control, so that the CPU 11 needs to perform the process for reconfiguring the programmable logic circuit 21. There is no. Therefore, the load on the CPU 11 is reduced to greatly reduce the power consumption.
Can be performed in parallel to improve the overall performance of the information processing system.

Next, the reconfiguration area of the processing circuit to the programmable logic circuit 21 and the storage or continuous processing of the intermediate processing data processed by each processing circuit in the memory will be described in three forms. .

FIG. 6 is an explanatory diagram of a first example of reconfiguration of a processing circuit into a programmable logic circuit, and FIG. 7 is a timing chart showing an example of the same operation. The example shown in FIG. 6 shows a method in which the input and output of the intermediate processing data are interposed in the single task mode while the reconfiguration of the processing circuit and the execution of the processing in the processing circuit are sequentially performed. This example is a mode corresponding to a case where an area where continuous processing circuits can be reconfigured at the same time cannot be ensured in the relationship between the maximum configurable circuit size of the programmable logic circuit 21 and the circuit size to be reconfigured.

When the reconfiguration of the first processing circuit is completed and the data processing is performed, the result obtained is temporarily stored in the internal memory or the local memory 22 of the programmable logic circuit 21.
The intermediate processing data is stored as it is using an external memory such as the main memory 14. Then, the next processing circuit is reconfigured by overwriting the first reconfigured area. When the reconfiguration of the next processing circuit is completed, data processing is continuously performed on the intermediate processing data. Thus, the data processing is continued. The processing mode is the case of the single configuration mode in which the number Ni of circuits that can be simultaneously reconfigured is one.

As an example, the example shown in FIG.
This will be described with reference to the timing chart shown in FIG. First, C
For example, a reference table as shown in FIG. 4 is prepared by the PU 11, and a memory address space is allocated as shown in FIG. When the processing data is transferred from the CPU 11, the programmable logic circuit interface 23 interprets the information added to the header part of the processing data and starts the reconfiguration of the circuit A for the programmable logic circuit 21 (FIG. 7). -).

When the reconfiguration of the circuit A is completed, processing data is input to the circuit A, and processing using the circuit A is started (FIG. 7-). The result obtained by the circuit A is stored in the memory as intermediate processing data (FIG. 7-).

When the EOF of the processing data is detected and the processing is completed, the next circuit B is reconfigured (FIG. 7-). The circuit B, which is the next processing circuit, can be reconfigured by overwriting the area of the circuit A reconfigured first. FIG.
This shows a state when the circuit B is reconfigured. When the EOF of the circuit information is detected, the reconfiguration of the circuit B is completed (FIG. 7-). When the reconfiguration of the circuit B is completed, the circuit B
Starts data processing on the intermediate processing data (FIG. 7).
-).

This step is repeated, and ends in processing step M. As described above, only the control by the CPU 11 is performed first, and thereafter, the reconfiguration of the processing circuit and the execution of the processing in the reconfigured processing circuit are continuously performed as specified in advance. by this,
The control load on the CPU 11 is greatly reduced, and the power consumption can be significantly reduced.

FIG. 8 is a flowchart showing an example of the operation in the first reconfiguration example of the processing circuit for the programmable logic circuit. FIG. 8 summarizes the processing operations of the above example. In step S101, a variable i indicating a processing step is initialized to 0. In step S102, processing data is input, and information of a header portion is interpreted to set a pointer and the like.

In S103, the circuit information Pci is accessed to reconfigure the processing circuit for the programmable logic circuit 21. When the EOF indicating the end of the circuit information is detected in S104, the reconfiguration of the processing circuit ends.
Then, in S105, the intermediate processing data Pd (i-
1) and input to the reconfigured processing circuit, or input processing data to the reconfigured processing circuit,
At 106, data processing is started.

In S107, when the EOF indicating the end of the processing data or the intermediate processing data is detected, the processing in the processing circuit ends. In S108, 1 is added to the variable i indicating the processing step, and in S109, it is determined whether or not the value of the variable i is M or less. If the value of the variable i is equal to or smaller than M, in S110, the processing result is set as the intermediate processing data, and the memory area Pd (i−
1). Then, the process returns to S103 to repeat the reconfiguration and processing of the next processing circuit.

The processing up to the processing step M is performed, and if the value of the variable i indicating the processing step exceeds M, the processing in S11
In step 1, the processed data is output as final data, and the processing in the programmable logic circuit 21 ends.

In the above description, the intermediate processing data is generated and processed. However, as shown in FIG. 2, when the result of the circuit A is received by the internal memory and subsequently processed by the circuit B, Instead of the internal memory, it is also possible to use a temporary data holding method using a data latch circuit.

FIG. 9 is an explanatory diagram of a second example of reconfiguration of a processing circuit into a programmable logic circuit, and FIG. 10 is a timing chart showing an example of the same operation. In the example shown in FIG. 9, although the single task mode is set, when a plurality of processes can be simultaneously formed, the processes are continuously executed after reconfiguring a plurality of processing circuits. The processing mode is a selection of a continuous configuration mode in which reconfiguration of a circuit up to a number Ni that can be simultaneously reconfigured is continuously performed.

In the relationship between the maximum configurable circuit scale of the programmable logic circuit 21 and the circuit scale of the processing circuit to be reconfigured, an area where continuous processing circuits can be reconfigured at the same time can be ensured. The obtained result is a case where the intermediate processing data is temporarily stored as it is by using the internal memory of the programmable logic circuit or the external memory of the local memory or the main memory. However, it is possible to include a case in which the processing is performed while being divided through the intermediate processing data. Of course,
As a processing mode, a single configuration mode in which processing circuits are reconfigured one by one can be selected. In this case, it can be handled as the form shown in FIG.

As an example, the example shown in FIG.
This will be described with reference to the timing chart shown in FIG. First,
A reference table as shown in FIG. 4 is prepared by the CPU 11, and a memory address space is allocated as shown in FIG. Programmable logic circuit interface 2
3, when the processing data is transferred from the CPU 11,
The information added to the header of the processing data is interpreted. Then, reconfiguration of a plurality of circuits reconfigurable in the programmable logic circuit 21, here, the circuit A and the circuit B, is started (FIG. 10-).

When the EOF of the two pieces of circuit information is detected, the reconstruction is completed, and the execution of the processing using these processing circuits is started (FIG. 10-). Here, the result processed by the circuit A is input to the circuit B, and the processing result by the circuit B is stored in the memory as intermediate processing data. Here, only the processing result of the last processing circuit is shown (FIG. 10-).

This process is repeated, and the process ends in processing step M. As described above, since the continuous processing can be performed, the processing can be performed without storing all of the intermediate processing data in the memory. Therefore, the number of times of storing the intermediate processing data is reduced, and high-speed processing and power consumption can be reduced. Further, only the control by the CPU 11 is performed first, and thereafter, the reconfiguration of the processing circuit and the execution of the processing in the reconfigured processing circuit are continuously performed as specified in advance. Thereby, the CPU 11
Control load is greatly reduced, and power consumption can be significantly reduced.

FIG. 11 is a flowchart showing an example of the operation in the second example of reconfiguring the processing circuit to the programmable logic circuit. FIG. 11 summarizes the processing operations of the second configuration example described above. In S121, a variable i indicating a processing step is initialized to 0, and in S12
In step 2, the processing data is input, the information in the header part is interpreted, and the setting of the pointer and the like is performed.

In S123, a variable j indicating the number of reconfigured circuits is initialized to 0. In S124, the circuit information Pc (i + j) is accessed to reconfigure the processing circuit for the programmable logic circuit 21. When the EOF indicating the end of the circuit information is detected in S125, the reconfiguration of the processing circuit ends. In S126, 1 is added to the value of the variable j. In S127, it is determined whether or not the value of the new variable j is smaller than the number Ni of simultaneously configurable circuits in the processing step i. If the value of the new variable j is smaller than Ni, the process returns to S124, and the next processing circuit that can be reconfigured at the same time is reconfigured. When the value of the variable j reaches Ni, in S128, the reconfiguration of the processing circuits up to the number of circuits that can be reconfigured at the same time ends.

In step S129, if the variable i is 0, the processing data is accessed. If the variable i is not 0, the intermediate processing data Pd (i + Ni-1) is accessed and input to the reconfigured processing circuit. Data processing is started in S130.

When the EOF indicating the end of the processing data or the intermediate processing data is detected in S131, the processing in the processing circuit ends. In S132, Ni is added to the variable i indicating the processing step, and in S133,
It is determined whether the value of the new variable i is equal to or less than M. If the value of the variable i is equal to or less than M, in step S134, the processing result is used as intermediate processing data, and the memory area Pd for intermediate processing data is used.
(I + Ni-1). Then, returning to S123,
Reconfiguration of the next plurality of processing circuits and continuous processing by the reconfigured processing circuits are repeated.

The processing up to the processing step M is performed, and if the value of the variable i indicating the processing step exceeds M, the processing in S13
In 5, the processed data is output as final data, and the processing in the programmable logic circuit 21 ends.

As in the case of the first reconfiguration example, when performing the single configuration in the single task mode, the intermediate processing data may be stored in the memory for each processing step. Since a continuous circuit can be simultaneously configured, continuous processing can be performed. Naturally, the intermediate processing data is stored in the local memory 22 if necessary.
And so on.

FIG. 12 is an explanatory diagram of a third example of reconfiguration of a processing circuit into a programmable logic circuit, and FIG. 13 is a timing chart showing an example of the same operation. In the example shown in FIG. 12, in the multitask mode, the processing is executed when the reconfiguration of the processing circuit is completed, and the reconfiguration of the next processing circuit is performed in parallel with another of the programmable logic circuit during the execution of the processing. Performed on the region. Then, the processing results obtained by the previous processing circuit are continuously processed, and parallel processing using different data is performed. For example, the configuration of the circuit B is performed during the process by the circuit A, and the processing is continuously performed. Moreover, the processing circuit is reconfigured by the programmable logic circuit 21.
In this case, the continuous configuration mode in which the reconfiguration of the processing circuits up to the number Ni that can be simultaneously reconfigured is continuously performed is selected.

In this example, when the reconfiguration of the previous processing circuit is completed and the data processing is being performed, the reconfiguration of the next processing circuit is performed in parallel. The result of the data processing by the processing circuit described above is temporarily stored as intermediate processing data using an internal memory of the programmable logic circuit 21 or an external memory such as the local memory 22 or the main memory 14, and is stored in the next circuit. When the reconstruction is completed, the data processing is continued. However, if the reconfiguration of the next processing circuit is completed before the output of the processing circuit, the output of the circuit A may be directly input to the circuit B as shown in FIG. Good.

As an example, an example shown in FIG. 12 will be described with reference to a timing chart shown in FIG. First, the CPU 11 prepares a reference table as shown in FIG. 4, and allocates a memory address space as shown in FIG. When the processing data is transferred from the CPU 11, the programmable logic circuit interface 23 interprets the information added to the header of the processing data. The programmable logic circuit interface 23
When the processing data is transferred from the CPU 11, the information added to the header part of the processing data is interpreted, and the reconfiguration of the circuit A for the programmable logic circuit 21 is started (FIG. 13-).

When the EOF of the circuit information regarding the circuit A is detected and the reconfiguration of the circuit A is completed, the processing data is transferred to the circuit A.
And the process using the circuit A is started (FIG. 13-
). The result obtained by the circuit A is stored in the memory as intermediate processing data (FIG. 13-).

In parallel with the processing in the circuit A, the reconfiguration of the next circuit B is started (FIG. 13-). While processing is being performed in such a processing circuit, reconfiguration of the programmable logic circuit up to the number Ni that can be simultaneously reconfigured can be performed continuously.

In the processing in the circuit A, the end of the processing is detected by detecting the EOF of the processing data, and when the end of the reconfiguration of the next circuit B is detected, the execution of the processing using the intermediate processing data in the circuit B is started. It is started (Fig. 13
-,).

As described above, the parallel processing of the reconfiguration of the processing circuit and the execution of the reconfigured processing circuit can shorten the waiting time of the processing by the reconfiguration of the processing circuit, thereby increasing the processing speed. , The speed of the process can be increased. Also, first the CPU
By simply performing the control by step 11, the reconfiguration of the processing circuit and its execution can be continuously performed as specified in advance. As a result, the control load on the CPU 11 is greatly reduced, and the power consumption can be significantly reduced.

FIG. 14 is a flowchart showing an example of the operation in the third example of reconfiguration of the processing circuit to the programmable logic circuit. FIG. 14 summarizes the processing operations of the third configuration example. In S141, a variable i indicating a processing step is initialized to 0, and in S14
In step 2, the processing data is input, the information in the header part is interpreted, and the setting of the pointer and the like is performed.

At S143, the circuit information Pci is accessed to reconfigure the processing circuit for the programmable logic circuit 21. When the EOF indicating the end of the circuit information is detected in S144, the reconfiguration of the processing circuit ends.
Then, after confirming in S145 that the reconfiguration of the processing circuit in the processing step i has been completed, in S146,
The intermediate processing data Pd (i-1) is accessed and input to the reconfigured processing circuit, or the processing data is input to the reconfigured processing circuit, and data processing is started in S147.

In parallel with the execution of the processing in the reconfigured processing circuit, the reconfiguration of the processing circuit in and after S161 is performed. First, in S161, the value of the variable i is saved to the variable k, and in S162, the value of the variable j indicating the processing step of the reconfigured circuit is initialized to k + 1. And
In S163, the circuit information Pc (j) is accessed to reconfigure the processing circuit in the vacant area for the programmable logic circuit 21. When the EOF indicating the end of the circuit information is detected in S164, the reconfiguration of the processing circuit ends. In S165, 1 is added to the value of the variable j,
In S166, it is determined whether the number of simultaneously reconfigured circuits is smaller than the number Nk of simultaneously configurable circuits in the processing step k. For this determination, the value of a new variable j indicating the number of reconfigured circuits + 1 is compared with the value of k + Nk. If the value of the new variable j is smaller than k + Nk, the process returns to S163, and the next processing circuit that can be reconfigured at the same time is reconfigured. When the value of the variable j reaches k + Nk, it is determined that the number of circuits that can be simultaneously configured has been reached, and the reconfiguration of the processing circuit is temporarily stopped.

In S167, if the value of the variable j has reached M, it is determined that the reconfiguration of all the processing circuits has been completed, and the reconfiguration processing is terminated. If the value of the variable j is equal to or smaller than M, the process is continued, and in S168, the process waits until the process is completed in all the processing circuits for which the reconfiguration has been completed, and then returns to S161 to enable the next simultaneous configuration. The reconfiguration processing of the processing circuits corresponding to the number of circuits is performed.

The execution of the processing in the processing circuit, which has been performed in parallel with the reconfiguration processing of the processing circuit, is performed in S14.
In step 8, EOF indicating the end of the processing data or the intermediate processing data is detected, and the processing ends. In S149, 1 is added to the variable i indicating the processing step, and in S150, it is determined whether the value of the new variable i is M or less. If the value of the variable i is equal to or less than M, in S151, the processing result is stored as intermediate processing data in the memory area Pd (i-1) for intermediate processing data. Then, returning to S145, after confirming the end of the reconfiguration of the next processing circuit, the continuous processing by the next processing circuit is repeated.

The processing up to the processing step M is performed. If the value of the variable i indicating the processing step exceeds M, the process proceeds to S15.
In step 2, the processed data is output as final data, and the processing in the programmable logic circuit 21 ends.

In the above description, the reconfiguration of the processing circuit is performed for each number of circuits that can be simultaneously configured. However, the present invention is not limited to this. For example, the configuration is such that the area of the processing circuit for which processing has been completed is sequentially opened, and the next processing circuit is reconfigured immediately when an area in which the next processing circuit can be configured is secured. May be.

The above three examples can be appropriately combined. FIG. 15 is an explanatory diagram of a fourth example of reconfiguration of the processing circuit into the programmable logic circuit, and FIG. 16 is a timing chart showing an example of the same operation. In this example, first, as shown in the above-described second reconfiguration example, the reconfiguration of the processing circuits for the number of circuits that can be simultaneously configured is performed first, and then, in the third reconfiguration example, As described above, it is possible to reconfigure a new processing circuit by opening the area of the processing circuit where the processing is completed.

As an example, an example shown in FIG. 15 will be described with reference to a timing chart shown in FIG. First, as shown in FIG. 15A, reconfiguration of a plurality of circuits reconfigurable in the programmable logic circuit 21, here, the circuit A and the circuit B, is started (FIG. 16-).

When the EOF of the two pieces of circuit information is detected, the reconfiguration is completed, and the processing using these processing circuits is started (FIG. 16-). Here, the result processed by the circuit A is input to the circuit B, and the processing result by the circuit B is stored in the memory as intermediate processing data (FIG. 16-).

When the processing of the circuit A is completed, the area in the programmable logic circuit 21 in which the circuit A is arranged becomes unnecessary. Therefore, in parallel with the execution of the processing of the circuit B, the reconfiguration of the circuit C is started using the area in which the circuit A is configured (FIG. 16-). Such reconfiguration of the processing circuits may be performed as many as the processing circuits can be arranged. In this way, as shown in FIG.
The circuit C is reconfigured using the area where the circuit A is located.

In the processing in the circuit B, the end of the processing is detected by detecting the EOF of the processing data, and when the end of the reconfiguration of the next circuit C is detected, the intermediate processing data output from the circuit B is used. The execution of the process in the circuit C is started (FIG. 16-). Such processing is repeated, and the processing up to the processing step M can be continuously performed.

In the above description, the description has been given based on the configuration shown in FIG. The information processing system of the present invention is not limited to the configuration shown in FIG. 1 and various modifications are possible. Some of them have already been described. As a more extreme example, for example, a configuration of only the extended hardware unit 19 or a configuration in which the external input / output interface 24 is not provided and data is input / output only via the programmable logic circuit interface 23 is provided. Is also good.

[0097]

As is apparent from the above description, according to the present invention, when the circuit to be used and the order can be specified in advance, only the control of the start of the first data processing by the main processor is performed, and Only by interpreting (for example, header information of processing data), data processing by a plurality of functional circuits of the programmable logic circuit can be sequentially executed. For this reason, the processing steps of control by the main processor can be significantly reduced to achieve high speed, and the power consumption can be significantly reduced.

Further, since the load on the main processor for control for circuit reconfiguration is greatly reduced, the processing power can be used for other processing, so that the performance of the entire system can be improved. This has the effect.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing an embodiment of an information processing system of the present invention.

FIG. 2 is a plan view showing an example of a programmable logic circuit.

FIG. 3 is a block diagram illustrating an example of an internal structure of a programmable logic circuit.

FIG. 4 is an explanatory diagram of an example of a reference table.

FIG. 5 is an explanatory diagram of processing data and circuit information, and a memory address space for storing them.

FIG. 6 shows a first processing circuit to a programmable logic circuit;
It is explanatory drawing of the example of reconfiguration | reconstruction.

FIG. 7 shows a first processing circuit to a programmable logic circuit;
6 is a timing chart showing an example of operation in a reconfiguration example of FIG.

FIG. 8 shows a first processing circuit to a programmable logic circuit.
5 is a flowchart showing an example of the operation in the reconfiguration example of FIG.

FIG. 9 shows a second processing circuit to a programmable logic circuit.
It is explanatory drawing of the example of reconfiguration | reconstruction.

FIG. 10 is a timing chart showing an example of an operation in a second reconfiguration example of a processing circuit for a programmable logic circuit;

FIG. 11 is a flowchart illustrating an example of an operation in a second example of reconfiguring a processing circuit to a programmable logic circuit;

FIG. 12 is an explanatory diagram of a third reconfiguration example of a processing circuit for a programmable logic circuit;

FIG. 13 is a timing chart showing an example of an operation in a third example of reconfiguration of the processing circuit to the programmable logic circuit;

FIG. 14 is a flowchart illustrating an example of an operation in a third example of reconfiguring the processing circuit to the programmable logic circuit;

FIG. 15 is an explanatory diagram of a fourth example of reconfiguration of a processing circuit into a programmable logic circuit.

FIG. 16 is a timing chart showing an example of an operation in a fourth reconfiguration example of a processing circuit for a programmable logic circuit;

FIG. 17 is a block diagram illustrating an example of a conventional information processing system.

FIG. 18 is an explanatory diagram of an example of a logic cell structure of a DPGA.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Information processing system, 2 ... Network, 3 ... External equipment, 11 ... CPU, 12 ... Host bus, 13 ... Chipset, 14 ... Main memory, 15 ... System bus, 16
... Hard disk interface, 17 ... Hard disk drive, 18 ... Communication interface, 19 ... Extended hardware part, 21 ... Programmable logic circuit, 22 ...
Local memory, 23: programmable logic circuit interface, 24: external input / output interface, 31: logic cell, 32: wiring area, 33: input / output terminal, 41: configuration memory, 42: circuit element, 51:
Application server, 52, 53 Client computer, 54 Communication network, 55 Main processor, 56 Extended hardware, 57 Application program, 58 Extended code, 59 Main processor code, 60 OS, 61 Code selection function,
71 ... DRAM, 72, 75 ... Multiplexer, 73 ...
Look-up table, 74 ... Flip-flop.

Claims (7)

[Claims] 1. An information processing system comprising a programmable logic circuit capable of changing and reconfiguring functions at any time by changing circuit information, a circuit information holding means for holding circuit information to be used in advance and an order. Specifying the first circuit information to be used for reconfiguring the programmable logic circuit from given processing data, and from the specified circuit information in the order held by the circuit information holding means, the programmable logic An information processing system comprising an interface means for reconfiguring a circuit to form a processing circuit and for causing the processing circuit to process the processing data. 2. The processing data includes, in a header portion, an order of processing steps defined in advance, address information of the circuit information holding unit storing circuit information to be reconfigured corresponding to the order, and an address corresponding to the order. Address information of storage means for storing data processed by the circuit, and information of the number of circuits that can be simultaneously reconfigured continuously in the programmable logic circuit corresponding to the order are added. The information processing system according to claim 1. 3. The method according to claim 1, wherein the interface means is configured to execute a processing step when a region in which continuous processing circuits cannot be reconfigured at the same time cannot be ensured in a relationship between a maximum configurable circuit size of the programmable logic circuit and a reconfigurable circuit size. The processing is performed by the processing circuit configured and configured in accordance with the order of the processing circuits, and the intermediate processing data processed by the processing circuit is sequentially input / output to the storage unit so that the processing is performed continuously. The information processing system according to claim 2, wherein the control is performed. 4. The method according to claim 1, wherein the interface unit reconfigures a plurality of processing circuits based on a relationship between a maximum configurable circuit size of the programmable logic circuit and a circuit size to be reconfigured. The result of the last processing circuit being executed continuously is stored in the storage means as intermediate processing data, and control is performed so that the reconfiguration of the plurality of processing circuits and the processing in the plurality of processing circuits are sequentially executed. The information processing system according to claim 2, wherein: 5. The method according to claim 1, wherein the interface unit continuously reconfigures a plurality of processing circuits by a number that can be simultaneously reconfigured in a relationship between a maximum configurable circuit size of the programmable logic circuit and a reconfigurable circuit size. While performing, the first processing is executed at the time when the reconfiguration of the first processing circuit is completed, and the next circuit is reconfigured in parallel with the execution of the processing, and the processing result is then processed. 3. The information processing system according to claim 2, wherein the control is performed so that the data is transferred to a circuit and the processing is continuously performed. 6. The information processing system according to claim 4, wherein a processing result in the processing circuit can be stored in the storage unit as intermediate processing data. 7. The processing unit according to claim 4, wherein a processing result in the processing circuit can be stored in the storage unit as intermediate processing data every time the processing of a predetermined processing step is completed. Information processing system.