JP2001044443A - Manufacture of semiconductor and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce parasitic capacitance, such as fringe junction capacitance by etching the semiconductor layer in an element isolation region, an insulating layer, and a semiconductor substrate, forming an insulating film on the semiconductor substrate, removing the insulating film from the activation region in the semiconductor layer, and implanting impurities. SOLUTION: An SOI layer in a trench region, a BOX layer 2, and a Si substrate 1 are etched. Thereafter, SiO2 is formed, and after planarization and etching, a SiN film and a pad oxide film are removed. Subsequently, a gate oxide film SiO2 is formed on the surface of an element activation region, and then a NMOS formation region, the Si layer in a PMOS formation region, and a polycrystalline Si film are implanted with ions in high dose. Thereafter, a layer insulating film is deposited. Since isolation is thus provided by a thick trench layer 7, extending to the Si substrate 1 under the buried oxide film 2, parasitic capacitances, such as fringe junction capacitance Cf2, a gate pad capacitance Cg2, and a junction capacitance Cj, are reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS type semiconductor device formed on an SOI substrate, and more particularly to a semiconductor manufacturing method and a semiconductor device for reducing parasitic capacitance.

[0002]

2. Description of the Related Art In recent years, a SOI device capable of improving the performance by reducing the junction capacitance of a conventional semiconductor device has been developed.
Semiconductor devices formed on an I (Silicon On Insulator) substrate are becoming more and more important.

FIG. 3 is a cross-sectional view showing a manufacturing process (part) of a conventional semiconductor device. The illustrated semiconductor device is formed in a so-called mesa type. First, an S in which a BOX layer 2 and an SOI layer 3 are formed on a silicon substrate 1
An OI semiconductor substrate 4 is prepared (FIG. 3A). Next, a pattern is formed by a resist film using a lithography technique, and the SOI layer 3 is etched (FIG. 3B).

Thereafter, a semiconductor element 6 is formed by a well-known method such as formation of a gate electrode 5 or dose ion implantation, an interlayer insulating film (eg, SiO 2) is deposited, and a contact hole is formed by RIE (Reactive Ion Etching). ) Method. Further, metal wiring is formed to complete the semiconductor device.

[0005] By the way, Full-Depletion type SOI
The threshold voltage Vth of the device is controlled by the work function of the front gate, the impurity concentration in the SOI layer, the substrate bias, and the like. Threshold voltage Vth with substrate bias
Is controlled by thinning the buried oxide film to increase the body factor and using a relatively small substrate bias value.

[0006]

However, in the prior art, the thickness of the buried oxide film 2 is reduced by reducing the thickness of the buried oxide film 2 as shown in FIG.
As shown in FIG. 4A and FIG. 4D, the SOI layer 3 has a junction / body capacitance Cj (corresponding to a junction capacitance of a bulk device) with respect to the silicon substrate 1 under the buried oxide film 3, a fringing capacitance Cf1, and a gate electrode. Since the pad capacitance Cg1 increases, there is a problem that the advantage of the junction capacitance of the SOI device is reduced.

Accordingly, the present invention provides a fringing junction capacitance,
It is an object of the present invention to provide a semiconductor manufacturing method and a semiconductor device capable of reducing parasitic capacitance such as gate pad capacitance and junction capacitance.

[0008]

In order to achieve the above object, a semiconductor manufacturing method according to the first aspect of the present invention provides a semiconductor manufacturing method for forming a semiconductor device on a semiconductor substrate having a semiconductor layer electrically separated by an insulating layer. Etching a semiconductor layer, an insulating layer, and a semiconductor substrate in an element isolation region, depositing an insulating film on the semiconductor substrate, and removing the insulating film from an activated region in the semiconductor layer. Implanting at least one or more impurities into the semiconductor substrate.

In a preferred embodiment, the method for manufacturing a semiconductor device according to claim 1 further includes a step of forming a gate electrode such that at least a peripheral portion is located on the element isolation region. May be.

According to another aspect of the present invention, there is provided a semiconductor device formed on a semiconductor substrate having a semiconductor layer electrically separated by an insulating layer. And an element isolation layer formed of an insulating layer and reaching the inside of the semiconductor substrate, and a conductive layer having two kinds of polarities formed in the semiconductor layer.

In a preferred embodiment, for example, in the semiconductor device according to the third aspect,
A gate electrode may be provided on the conductive layer via an insulating layer, and at least a peripheral portion of the gate electrode may be located on the element isolation layer.

In the present invention, the semiconductor layer, the insulating layer, and the semiconductor substrate in the element isolation region are etched and an insulating film is deposited on the semiconductor substrate, so that the element isolation reaches the inside of the semiconductor substrate beyond the insulating layer. Since a layer, a so-called thick trench layer, is formed, parasitic capacitance such as fringing junction capacitance, gate pad capacitance, and junction capacitance can be reduced.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view showing a manufacturing process (part) of a semiconductor device according to an embodiment of the present invention.
The same reference numerals are given to the portions corresponding to FIG.

First, for example, an SOI semiconductor substrate 4 having a 50 nm thick BOX layer 2 and a 30 nm thick SOI layer 3 formed on a silicon (Si) substrate 1 is prepared (FIG. 1).
(A)). Next, for example, a pad oxide film having a thickness of 5 nm, a SiN film having a thickness of 100 nm, and a polycrystalline Si film having a thickness of 100 nm are formed on the Si substrate 1 (not shown). Thereafter, a trench (Trench) pattern is formed by a resist film using a lithography technique (not shown), and the SOI layer 3 in the trench region is formed.
/ BOX layer 2 / Si substrate 1 is dry-etched. For example, the SOI layer 3 / BOX layer 2 / Si substrate 1
Etch about 30/50/100 nm thick.

Thereafter, HDP (High-Density Plasma en)
An SiO ₂ insulating film is formed by a hanced deposition method (not shown). Then, CMP (Chemical / Mechani
After performing planarization and etching by a cal polishing method or the like, the SiN film is removed by hot phosphoric acid or the like, and the pad oxide film is removed by DHF (dilute hydrofluoric acid) or the like (FIG. 1B).

Next, SiO 2 as a gate oxide film is formed on the surface of the element active region. For example, a polycrystalline Si film containing no impurities is processed into a gate electrode pattern on the SiO ₂ (not shown). Then, the NMOS formation region, P
In the Si layer (on the insulating film and the substrate) and the polycrystalline Si film in the MOS formation region, for example, 3 × 10 ¹⁵ / cm 2,
s and BF2 are implanted at a high dose.

Thereafter, after depositing an interlayer insulating film (such as SiO 2), a contact hole is formed by RIE or the like. Further, metal wiring is formed by a conventionally known technique to complete a semiconductor device (not shown).

Here, FIG. 2 is a conceptual diagram showing a state of occurrence of parasitic capacitance in the semiconductor device according to the present embodiment.
In the semiconductor device formed by the above-described steps, FIG.
As shown in FIG. 2A and FIG. 2B, the silicon substrate 1 under the buried oxide film 2 is separated by a thick trench layer (oxide film) 7, so that a fringing junction capacitance Cf2 and a gate pad capacitance Cg2 are formed. , The parasitic capacitance such as the junction capacitance Cj decreases.

In the above-described process, before forming the gate oxide film, ion implantation for adjusting a threshold value or the like may be performed on a semiconductor region such as an element active region. Prior to the high dose ion implantation, a low dose L
A DD (Lightly Doped Drain) film forming step and a subsequent gate side wall forming step may be included. Further, after the high dose ion implantation, the conventionally known S
ALICIDE (Self-Aligned Silicide)
CoSi2, TiSi for gate, source and drain regions
The resistance may be reduced by forming a silicide such as 2.

[0020]

As described above, according to the first aspect of the present invention, the semiconductor layer, the insulating layer, and the semiconductor substrate in the element isolation region are etched to deposit an insulating film on the semiconductor substrate. After forming an element isolation layer that extends into the semiconductor substrate beyond the insulating layer, that is, a so-called trench layer, and removing the insulating film from an active region in the semiconductor layer, at least one trench is formed so as to enter the semiconductor substrate. By implanting more types of impurities, a semiconductor device is formed, so that the fringing junction capacitance,
An advantage is obtained in that parasitic capacitance such as gate pad capacitance and junction capacitance can be reduced.

According to the second aspect of the present invention, at the time of forming the gate electrode, at least the peripheral portion of the gate electrode is located on the element isolation region.
In particular, there is obtained an advantage that the parasitic capacitance due to the fringing junction capacitance can be reduced.

Further, according to the third aspect of the present invention, the element isolation layer which reaches the inside of the semiconductor substrate beyond the insulating layer and is made of the insulating layer has two kinds of polarities formed in the semiconductor layer. Since it is provided around the conductive layer, the fringing junction capacitance, the gate pad capacitance, and the parasitic capacitance can be reduced.

According to the fourth aspect of the present invention, at least the peripheral portion of the gate electrode formed above the conductive layer via the insulating layer is positioned above the element isolation layer. In particular, there is obtained an advantage that the parasitic capacitance due to the fringing junction capacitance can be reduced.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a manufacturing process (part) of a semiconductor device according to an embodiment of the present invention and a state of occurrence of parasitic capacitance in the semiconductor device.

FIG. 2 is a conceptual diagram illustrating a state of occurrence of parasitic capacitance in the semiconductor device according to the present embodiment.

FIG. 3 shows a manufacturing process (part) of a semiconductor device according to a conventional technique.
FIG.

FIG. 4 is a conceptual diagram showing a state of occurrence of a parasitic capacitance in a semiconductor device according to the related art.

[Explanation of symbols]

1 ... Si substrate (semiconductor substrate), 2 ... BOX layer (insulating layer), 3 ... SOI layer (semiconductor layer), 4 ... SOI substrate, 5 ... gate electrode, 6 ... semiconductor element, 7 ... … Trench layer (element isolation layer)

Claims (4)

[Claims] 1. A semiconductor manufacturing method for forming a semiconductor device on a semiconductor substrate having a semiconductor layer electrically separated by an insulating layer, comprising: a step of etching the semiconductor layer, the insulating layer, and the semiconductor substrate in an element isolation region; A step of depositing an insulating film on a semiconductor substrate; a step of removing the insulating film from an active region in the semiconductor layer; and a step of implanting at least one or more impurities into the semiconductor substrate. A semiconductor manufacturing method characterized by the above-mentioned. 2. The method according to claim 1, further comprising the step of forming a gate electrode so that at least a peripheral portion is located on the element isolation region. 3. A semiconductor device formed on a semiconductor substrate having a semiconductor layer electrically separated by an insulating layer, comprising: an element isolation layer that reaches the inside of the semiconductor substrate beyond the insulating layer and is formed of an insulating layer; A conductive layer having two kinds of polarities formed in the semiconductor layer. 4. The semiconductor device according to claim 3, further comprising a gate electrode formed above the conductive layer via an insulating layer, wherein at least a peripheral portion of the gate electrode is located on the element isolation layer. Semiconductor device.