JP2000307971A - Method and device for receiving data - Google Patents

Abstract

PROBLEM TO BE SOLVED: To output audio data by receiving the transmission packet of a content package. SOLUTION: At the time of receiving serial data CPS as the transmission packet of a digital transfer interface packaging the data of respective items including the data of audio items at least, frame sequence data inserted in a header area provided corresponding to an audio data block area, where audio data are inserted, are separated by a serial data transport interface(SDTI) core part 222 and supplied to an interface part 203 as a signal FA. At the interface part 203, these data are compared with a reference sequence. On the basis of the compared result, the address of the output buffer means of the interface part 203 is controlled and audio data DAU are outputted with a correct phase.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a data receiving method and a data receiving apparatus. More specifically, when a transmission packet of the serial digital transfer interface is received, audio data separated from the transmission packet is temporarily stored in, for example, a FIFO unit, read out at a predetermined speed, and output. A reference sequence generated on the receiving side as a reference for output is compared with frame sequence data separated from a received transmission packet, and F is determined based on the comparison result.
The address of the IFO section is controlled.

[0002]

2. Description of the Related Art Conventionally, SMPTE (Society of Motion)
The Picture and Television Engineers (American Motion Picture and Television Engineers) and the European Broadcasting Union (EBU) are studying the exchange of programs between broadcasting stations, and as a result, the EBU / SMPTE Task F
orce for Harmonized Standards for the Exchange ofP
rogramme Material as Bitstreams "has been announced.

In this announcement, essential data of a program, for example, video or audio material is regarded as essence, and information on the content of the essence, for example, the title of the program, the video system (NTSC or PAL), and the audio sampling frequency are meta-data. Data (Metadata).

Next, a content element (Content Element) is formed from the essence and the metadata, and a video or audio content item (Content item) is generated using a plurality of content elements. For example, a video clip useful as an image index collection corresponds to this. Further, a content package (Content Package) is configured from a plurality of content items and content elements. This content package corresponds to one program, and a set of content packages is called a wrapper (Wrappe
r). A proposal has been made to facilitate program exchange by standardizing means for transmitting and storing the wrapper between broadcast stations.

[0005]

In the above-mentioned announcement, only the concept of program exchange is described, but no specific method for transmitting a program is specified. For this reason, the program could not be actually transmitted as a content package as described above.

Accordingly, in the present invention, when a content package is formed and a program is transmitted using a transmission packet of a serial digital transfer interface, data reception for receiving the transmission packet of the content package and outputting audio data. A method and a data receiving device are provided.

[0007]

According to the data receiving method of the present invention, each one-line section of a video frame is divided into an end synchronization code area in which an end synchronization code is inserted, and an auxiliary data area in which auxiliary data is inserted. And a start sync code area in which a start sync code is inserted, and a payload area in which at least data including audio data is inserted, and corresponds to an audio data block area in the payload area in which audio data is inserted. A data receiving method for receiving a transmission packet of a serial digital transfer interface in which frame sequence data for phase management of audio data is inserted into a header area provided as above, wherein audio data separated from the received transmission packet is output. Once stored in the buffer means, read out and output at a predetermined speed, The reference sequence generated on the receiving side, which serves as a reference for the output of the data stored in the buffer means, is compared with the frame sequence data separated from the received transmission packet, and the address of the output buffer means is controlled based on the comparison result. Is what you do.

[0008] Further, a data receiving apparatus according to the present invention comprises:
Each one-line section of the video frame is divided into an end synchronization code area in which an end synchronization code is inserted, an auxiliary data area in which auxiliary data is inserted, a start synchronization code area in which a start synchronization code is inserted, and at least audio data. And a payload area in which data including the data is inserted, and a header sequence provided in the payload area corresponding to the audio data block area in which the audio data is inserted, a frame sequence for managing the phase of the audio data. A data receiving apparatus for receiving a transmission packet of a serial digital transfer interface into which data has been inserted, comprising: data separation means for separating audio data and frame sequence data from the received transmission packet; and storing the audio data separated by the data separation means. Output buffer means, and stored in the output buffer means. A reference sequence generating means for generating a reference sequence serving as a reference for data output; and an output buffer means for comparing the reference sequence generated by the reference sequence generating means with frame sequence data separated from a received transmission packet, based on a comparison result. Address control means for controlling the address of

According to the present invention, a transmission packet of a serial digital transfer interface in which frame sequence data for phase management of audio data is inserted into a header area provided corresponding to an audio data block area into which audio data is inserted is received. In this case, the audio data separated from the received transmission packet
Once stored in the O section, it is read out and output at a predetermined speed. Here, the address control of the FIFO unit is performed based on a comparison result between the reference sequence generated on the receiving side, which is a reference for the output of the data stored in the output buffer means, and the frame sequence data separated from the received transmission packet. Then, the audio data of the data amount based on the reference sequence is written into the FIFO unit, and the write address of the FIFO unit is controlled based on the comparison result to adjust the data amount of the audio data written to the FIFO unit. . When the frame sequence data becomes discontinuous, the read address of the FIFO unit is controlled based on the result of comparison between the write address and the read address, for example, audio data is read twice or thinned out.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. In the present embodiment, data such as video and audio materials are packaged and each content item (for example, a picture item (Picture Item) or an audio item (Audio Item)) is packaged.
m)), as well as packaging information about each content item, metadata about each content, and the like to form one content item (system item (S
ystem Item)), and make each of these content items a content package. Further, a transmission packet is generated from the content package and transmitted using a serial digital transfer interface.

As the serial digital transfer interface, for example, SMPTE-259M "10-bit 4: 2: 2" standardized by SMPTE
Component and 4fsc Composi
te Digital Signals -Seria
l Digital Interface ”(hereinafter“ Serial Digital Interface SDI (Serial Digita
l Interface) format) and the SMPTE-305M “Seri” standard for transmitting packetized digital signals.
al DataTransport Interface
e "(hereinafter referred to as" SDTI format ") to transmit the above-mentioned content package.

First, when the SDI format standardized by SMPTE-259M is arranged in a video frame, the digital video signal of the NTSC 525 system is
1716 (4 + 268 + 4 +) per line in the horizontal direction
1440) The word is composed of 525 lines in the vertical direction. Also, a digital video signal of the PAL625 system is 1728 (4 + 28) per line in the horizontal direction.
(0 + 4 + 1440) words and 625 lines in the vertical direction. However, it is 10 bits / word.

[0013] For each line, four words from the first word to the fourth word are used as a video signal area 144.
Indicates the end of the 0-word active video area, and is used as an area for storing a code EAV (End of Active Video) for separating the active video area and an ancillary data area described later.

Further, for each line, 268 words from the fifth word to the 272th word are used as an ancillary data area, and header information and the like are stored. Four words from the 273rd word to the 276th word indicate the start of the active video area, and a code SA for separating the active video area from the ancillary data area.
It is used as an area for storing V (Start of Active Video), and the 277th word and subsequent words are used as an active video area.

In the SDTI format, the above-mentioned active video area is used as a payload area, and the codes EAV and SAV indicate the end and start of the payload area.

Here, the data of each item is inserted into the payload area of the SDTI format as a content package and the code EAV of the SDI format is inserted.
And SAV are added to form data in a format as shown in FIG. When data in the format shown in FIG. 1 (hereinafter referred to as "SDTI-CP format") is transmitted, P / S conversion and transmission path encoding are performed and transmitted as serial data, as in the SDI format and SDTI format. You. In FIG. 1, the numbers in parentheses indicate the numerical values of the PAL625 video signal, and the numbers without the parentheses indicate the numerical values of the NTSC 525 video signal. Hereinafter, only the NTSC system will be described.

FIG. 2 shows the structure of the code EAV and the header data included in the ancillary data area.

The code EAV is 3FFh, 000h, 000
h, XYZh (h indicates hexadecimal notation, and the same applies to the following description).

In "XYZh", the bit b9 is set to "1" and the bits b0 and b1 are set to "0". Bit b8 is a flag indicating whether the field is the first field or the second field.
Is a flag indicating a vertical blanking period. Bit b6 is a flag indicating whether the 4-word data is EAV or SAV. The flag of the bit b6 is set to "1" for EAV and "0" for SAV. Bits b5 to b2 are data for performing error detection and correction.

Next, at the beginning of the header data, data for header data recognition "ADF (Ancillary data flag)"
Are fixed patterns 000h, 3FFh, 3FFh. Following this fixed pattern, “DID (Data ID)” and “S” indicating the attributes of the ancillary data area
DID (Secondary data ID) ", and fixed patterns 140h and 101h indicating that the attribute is a user application are provided.

"Data Count" is "Line Count".
Number-0 ”to“ Header CRC1 ”
This indicates the number of words up to 46 words, and the number of words is 46 words (22Eh).

"Line Number-0, Line
"Number-1" indicates the line number of the video frame. In the NTSC 525 system, these two words indicate the line numbers from 1 to 525. In the PAL system 625 system, line numbers from 1 to 625 are indicated.

"Line Number-0, Line
Number-1 followed by Line Number
er CRC0, Line Number CRC1 "
Are arranged, and this “Line Number CR”
C0, Line Number CRC1 ”is“ DI
D ”to“ Line Number-1 ”, CRC (cyclic redundancy check) for 5-word data
codes), which are used for checking transmission errors.

"Code & AAI (Authorized addr
ess identifier) indicates information such as what the word length of the payload area from the SAV to the EAV is set and what data format is used for the addresses of the sending side and the receiving side. .

[Destination Addresses]
"s" is the address of the data receiving side (transmission destination), and "S
"source Address" is the address of the data transmission side (transmission source).

The "Block Type" following the "Source Address" indicates the format of the payload area, for example, whether the payload area has a fixed length or a variable length. Compressed data is inserted. Here, SDTI-C
In the P format, for example, when a content item is generated using compressed video data (video data), a variable length block (Variable Block) is used because the data amount differs for each picture. For this reason, SD
"Block Type" in TI-CP format
Is fixed data 1C1h.

"CRC Flag" indicates whether a CRC is placed in the last two words of the payload area.

Further, "Da" following "CRC Flag"
“ta extension flag” indicates whether or not the user data packet is extended.

"Data extension fla
Following "g", a 4-word "Reserved" area is provided. Next "Header CRC 0, Head
erCRC 1 ”is a CRC for data from“ Code & AAI ”to“ Reserved 4 ”.
(Cyclic redundancy check codes), which are used for checking transmission errors. The next "Check Su
“m” is a Check Sum code for all header data, and is used for checking transmission errors.

In the payload area shown in FIG. 1, data of items such as video and audio is packaged as a variable-length block in SDTI format. FIG. 3 shows the format of a variable-length block. "Separator" and "End Cod"
"e" indicates the start and end of the variable-length block,
The value of “Separator” is “309h”, and “End”
The value of “Code” is set to “30 Ah”.

The “Data Type” indicates what item the packaged data is, and the value of the “Data Type” is, for example, “04h” in the system item (System Item). "05h" for picture items, "06h" for audio items, and "07h" for AUX items that are other data.
It is said. Note that one word is 10 bits as described above. For example, when the word is 8 bits as indicated by “04h”, the 8 bits correspond to bits b7 to b0. Further, by adding even parity of bits b7 to b0 as bit b8 and adding logically inverted data of bit b8 as bit b9, data of 10 bits is obtained. The 8-bit data in the following description is similarly converted into 10 bits.

In "Word Count", "Data
The “Dat” indicates the number of words of “Block”.
"a Block" is the data of each item. Here, the data of each item is packaged in picture units, for example, frame units, and in the NTSC system, the program switching position is set to the position of 10 lines. Therefore, in the NTSC system, as shown in FIG. 1 in
From the third line, system items, picture items,
Audio items and AUX items are transmitted in this order.

FIG. 4 shows the structure of a system item. "System ItemType" and "Wor
“d Count” is “Data Ty” of the variable-length block.
pe "and" Word Count ".

One-word "System Item B"
The bit b7 of "itmap" is a flag indicating whether or not an error detection and correction code such as a Reed-Solomon code is added, and when "1" is set, the error detection and correction code is added. Is shown. Bit b6 is a flag indicating whether or not there is SMPTE Label information. Here, when “1” is set, it indicates that the information of the SMPTE Label is included in the system item. Bits b5 and b
4 is Reference Date / Time status
mp, Current Date / Time stamp
This is a flag indicating whether or not p is in the system item. This Reference Date / Times
In the “tamp”, for example, the time or date when the content package was first created is indicated. Also Curren
In t Date / Time stamp, the time or date when data of the content package was last corrected is indicated.

Bit b3 is a picture item, bit b
2 is an audio item, and bit b1 is a flag indicating whether or not the AUX item is after the system item. When "1" is set, it indicates that the item exists after the system item.

The bit b0 is the control element (C
ontrol Element).
When "1" is set, it indicates that the control element exists. In addition, although not shown, the bit b
8, b9 are added as described above and transmitted as 10-bit data.

One-word "Content Packa"
bits b7 to b6 of "ge Rate" are undefined areas (Res
erved), and the bits b5 to b1 indicate the package rate which is the number of packages per second in the 1 × speed operation.
(Package Rate) is displayed. Bit b0 is a 1.001 flag. When the flag is set to "1", it indicates that the package rate is (1 / 1.001) times.

One-word "Content Packa"
Bits b7 to b5 of “ge Type” are “Stream States” flags for identifying the position of the picture unit in the stream. This 3
The following eight types of states are indicated by the bit flags.

0: This picture unit is a pre-roll (pr
e-roll) section, editing section, post-roll
It does not belong to any of the sections. 1: This picture unit is a picture included in the pre-roll section, and is followed by an editing section. 2: This picture unit is the first picture unit of the editing section. 3: This picture unit is a picture unit included in the middle of the editing section. 4: This picture unit is the last picture unit of the editing section. 5: This picture unit is a picture unit included in the post-roll section. 6: This picture unit is the first and last picture unit of the editing section (the state where the editing section has only one picture unit). 7: Not defined

The bit b4 is an undefined area (Reserved), and the bits b3 and b2 of "Transfer Mod"
"e" indicates the transmission mode of the transmission packet. Also, the transmission timing mode when transmitting the transmission packet is indicated by “Timing Mode” of bits b1 and b0. Here, when the value indicated by the bits b3 and b2 is “0”, the synchronous mode (Synchronous mode)
When "1", isochronous mode,
When it is "2", it is set to an asynchronous mode (Asynchronous mode). When the value indicated by the bits b1 and b0 is “0”, the transmission of the content package for one frame is started at a timing of a predetermined line of the first field (Normal timing mode).
Advanced timing mode in which transmission is started at the timing of a predetermined line in the second field when "1"
(Advanced timing mode), when "2", a dual timing mode in which transmission is started at a timing of a predetermined line in each of the first and second fields (Dual timing mode)
mode).

"Content Package Ty"
"Channel" followed by two words "Channel Handl"
"e" is used to determine the content package of each program when the content packages of a plurality of programs are multiplexed and transmitted, and are identified by identifying the values of bits H15 to H0. Content packages can be separated for each program.

The two-word "Continuity Co"
"unt" is a 16-bit modulo counter. This counter is counted up for each picture unit, and is independently counted for each stream. Therefore, when a stream is switched by a stream switcher or the like, the value of this counter becomes discontinuous, and a switching point (editing point) can be detected. Since this counter is a 16-bit modulo counter as described above and has a very large value of 65536, the probability that the value of the counter coincidentally coincides at the switching point between the two switched streams is extremely low. In addition, practically sufficient accuracy can be provided for detecting the switching point.

After “Continuity Count”, the above-mentioned SMPTE Label or Refer
ence Date / Time and Current
"SMPTE Universal" indicating Date / Time
sal Label "," Reference Dat "
e / Time stamp "," Current Da
A "te / Time stamp" area is provided.

After that, "Package Meta"
data Set ”or“ Picture Metada ”
ta Set "," Audio Metadata Se "
t "" Auxiliary Metadata Se
A "t" region is provided. In addition, "Picture Me
tadata Set "," Audio Metadat "
a Set "," Auxiliary Metadata "
Set ”indicates that the corresponding item is“ System I
It is provided when it is indicated that the content is included in the content package by the flag of “tem Bitmap”.

In the above-mentioned “Time stamp”, 17 bytes are allocated, and “Time” is used in the first byte.
e stamp ", and the remaining 16 bytes are used as a data area. here,
The first 8 bytes of the data area are, for example, SMPTE12
A time code (Time code) standardized as M is shown, and the subsequent 8 bytes are invalid data.

As shown in FIG. 5, the time code of 8 bytes is “Frame”, “Seconds”, “Minute”.
s "," Hours "and 4-byte" Binary "
Group Data ”.

Bits b5 and b4 of "Frame" indicate the tens place of the frame number, and bits b3 to b0 indicate the place of the first place. Similarly, “Secons” and “Minute”
s ”,“ Hours ”, each bit b6 to b0 indicates seconds,
Minutes and hours are shown.

The bit b7 of "Frame" is a color frame flag (Color Frame Flag), and indicates whether the frame is the first color frame or the second color frame. Bit b6 is a drop frame flag (Drop Frame flag).
Flag), which is a flag indicating whether or not the video frame inserted in the picture item is a drop frame. Bit b7 of “Seconds” is, for example, NTSC
In the case of the system, a field phase (Field Phase), that is, whether the field is the first field or the second field is indicated. In the case of the PAL method, the field phase is indicated by the bit b6 of “Hours”.

The three bits B0 of the bit b7 of “Minutes” and the bits b7 and b6 of “Hours”
B3 (In the PAL system, “Seconds” and “Mini
tes ”and“ Hours ”, each bit b7) indicates whether or not there is data in each of BG1 to BG8 of“ Binary Group Data ”. In this “Binary Group Data”, for example, the Gregorian calendar (GregorianCalender) and the Julian calendar (Julian calendar)
Calender) can be displayed in two digits.

FIG. 6 shows the structure of the "Metadata Set", in which one word "Metadata Co" is used.
"metadata Bl" in the set
The number of “ocks” is indicated. In addition, "Metadata
When the value of “Set” is 00h, “Metadata
Since there is no "Block", "Me
“tadata Set” is one word.

Here, "Metadata Bloc
“k” indicates “Package Metadata Set” indicating content package information such as a program title.
In the case of, the one-word "Metadata Type
"e", a two-word "Word Count", and an information area "Metadata" is provided.
If the number of words of this “Metadata” is “Word C
"out" is indicated by bits b15 to b0.

"Picture Metadata Set", "A" indicating information on packaged items such as video, audio or AUX data
audio Metadata Set "and" Auxili
The “ary MetadataSet” further includes “Element Type” and “Element” of one word.
“Element Number” is provided, and “Element Data” of items such as video and audio described below is provided.
"Element Type" and "E"
element Number ", and is linked to" Element Data Block ".
Metadata can be set for each time. After these “Metadata Set”, “Cont.
A "rollElement" region can be provided.

Next, a block of each item such as video and audio will be described with reference to FIG. Block of each item such as video and audio "Item Type
"e" indicates the type of item as described above,
It is set to "05h" for a picture item, "06h" for an audio item, and "07h" for an AUX data item. “Item Word Count” indicates the number of words up to the end of this block (corresponding to “Word Count” of a variable-length block). "I
“Item H Count” followed by “Item H
"Element Data Bl"
The number of “ocks” is indicated. Here, "Item Hea
Since “der” is 8 bits, “Element”
The number of “DataBlock” ranges from 1 to 255 (0 is invalid). The “Element Data Block” following the “Item Header” is the data area of the item.

"Element Data Bloc"
k "means" Element Type "and" Element
t Word Count "," Element Num "
ber "and" Element Data ", and" Element Type "and" Element ".
Word Count "by" Element
The type and amount of data of “Data” are shown.
The “Element Number” indicates the number of the “Element Data Block”.

Next, the structure of "Element Data" will be described. MPEG, one of the elements
The -2 picture element is an MPEG-2 video elementary stream (V-ES) of any profile or level. Profiles and levels are defined in the decoder template document. FIG. 8 is an example of the format of MPEG-2 V-ES in the SDTI-CP element frame. This example is a V-ES bitstream that specifies a key, ie, an MPEG-2 start code (according to SMPTE recommended practices). MPEG
The -2 V-ES bitstream is simply formatted into data blocks as shown in FIG.

Next, metadata for a picture item, for example, MPEG-2 picture image editing metadata will be described. This metadata is a combination of edit and error metadata, compression encoded metadata, and source encoded metadata. These metadata can be inserted mainly in the system items described above, as well as in auxiliary data items.

FIG. 9 shows “Picture Editing Bitma” provided in the MPEG-2 picture editing metadata inserted in the “Picture MetadataSet” area of the system item shown in FIG.
A “p” area, a “Picture Coding” area, and an “MPEG User Bitmap” area are shown. Further, the MPEG-2 picture editing metadata includes a “Profile / Level” area indicating the profile and level of MPEG-2, and an SMPTE1
It is also conceivable to provide video index information defined in 86-1995.

One word "Picture Edit"
ng Bitmap ”bits b7 and b6 are“ Ed
It flag ", which is a flag indicating editing point information. The following four types of states are indicated by the 2-bit flag.

00: No editing 01: The editing point is before the picture unit with this flag (Pre-picture edit) 10: The editing point is after the picture unit with this flag (Post-picture edit) -picture edit) 11: Only one picture unit is inserted, and the edit point is before and after the picture unit with this flag (single
le frame picture)

That is, a flag indicating whether the video data (in picture units) inserted into the picture item is before the edit point, after the edit point, or sandwiched between two edit points is set to “Picture”. Metadata
Set ”(see FIG. 4),“ Picture Edit ”
ing Bitmap "region.

Bits b5 and b4 are "Error"
flag ". This "Error flag"
Whether the picture contains an uncorrectable error, the picture contains a concealment error, the picture contains no errors,
Furthermore, it indicates whether it is in an unknown state. Bit b3 is "P
Picture Coding ”is the“ Picture
This is a flag indicating whether or not it is in the “MetadataSet” area. Here, when “1” is set, “P”
icture coding ”is included.

The bit b2 is “Profile / Lev”
"el". here,
When it is set to “1”, the “Metadata
The “Block” includes “Profile / Level”. This “Profile / Level” is M
MP @ ML or HP indicating PEG profile or level
＠ Indicates HL or the like.

Bit b1 is a flag indicating whether or not "HV Size" exists. Here, when “1” is set, “HV Size” is included in the “Metadata Block”. Bit b0 is
This flag indicates whether or not “MPEG User Bitmap” is present. Here, when “1” is set, “MPE” is added to the “Metadata Block”.
G User Bitmap "is included.

One-word "Picture Codin"
“Closed GOP” is provided in bit b7 of “g”. This “Closed GOP” indicates that the GOP (Group Of Picture) when MPEG-compressed is Closed.
d Indicates whether this is a GOP.

The bit b6 contains “Broken Lin”.
k ”is provided. This "Broken Link"
Is a flag used for reproduction control on the decoder side.
That is, each picture of MPEG is arranged like a B picture, a B picture, an I picture, etc., but when there is an editing point and a completely different stream is connected, for example, the B picture of the stream after switching is There is a possibility that decoding is performed with reference to the P picture of the stream before switching. By setting this flag, it is possible to prevent the decoding as described above on the decoder side.

Bits b5 to b3 contain "Picture"
“Coding Type” is provided. This "Pi
"cure Coding Type" is a flag indicating whether the picture is an I picture, a B picture, or a P picture. Bits b2 to b0 are undefined areas (Reserved).

One word "MPEG User Bit"
"History dat" is set in bit b7 of "map".
a "is provided. This "History dat"
“a” indicates that the encoded data such as the quantization step, the macro type, and the motion vector, which are necessary for the encoding of the previous generation, are stored in the user data area existing in “Metadata” of “Metadata Block”, for example. , History data, or not. Bit b6 contains “Anc
data ”is provided. This "Anc dat
"a" is the data inserted in the ancillary area (for example,
This is a flag indicating whether or not data necessary for MPEG compression is inserted as Anc data in the user data area.

In the bit b5, "Video inde
x "is provided. This "Video inde
“x” is a video index in the video index area.
This is a flag indicating whether index information is inserted. The video index information is inserted into a 15-byte video index area. In this case, the insertion position is determined for each of the five classes (1.1, 1.2, 1.3, 1.4, and 1.5). For example, the video index information of the 1.1 class is inserted into the first three bytes.

Bit b4 contains “Picture or
der "is provided. This "Picture o
“rder” is a flag indicating whether or not the order of each picture of the MPEG stream has been changed. In addition, MPE
Changing the order of the pictures in the G stream is required for multiplexing.

Bits b3 and b2 contain "Timecode
e2 "and" Timecode1 ". This "Timecode2", "Timecode1"
Is in the area of Timecode2, 1
ical Interval Time Code), LTC (Longitudinal Ti)
me Code) is inserted. Bits b1 and b0 include “H-Phase” and “V
-Phase "is provided. This "H-Phas
"e" and "V-Phase" are flags indicating which horizontal pixel and vertical line are being encoded at the time of encoding, that is, whether or not the information of the frame actually used is in the user data area.

Next, the audio item will be described. The audio item "Element Dat
“a” is “Element Dat” as shown in FIG.
"a" is "Element Header", "Audio"
“Sample Count”, “Stream Val”
id Flags "and" Data Area ".

The one-word “Element Head”
The bit b7 of “r” is “FVUCPVValid Fla.
g), and FVUCP defined in the AES-3 format standardized by the AES (Audio Engineering Society) is the AES of “Data Area”.
-3 format audio data (audio data)
Indicates whether or not it has been set. Bits b6 to b3
Is an undefined area (Reserved), and bits b2 to b0
Sequence number of 5-frame sequence (5-sequ
ence counter) is indicated.

Here, the five-frame sequence will be described. One frame is composed of 525 scanning lines (30/1.
001) synchronized with the video signal of frame / second,
When an audio signal having a sampling frequency of 48 kHz is divided into blocks of each frame of a video signal,
The number of samples per video frame is 1601.6 samples / frame, which is not an integer value. For this reason,
A sequence in which two frames of 1601 samples are provided and three frames of 1602 samples are provided so that five frames have 8008 samples is called a five-frame sequence.

The 5-frame sequence is synchronized with the reference frame signal shown in FIG. 11A. For example, as shown in FIG. 11B, the frames of sequence numbers 1, 3, and 5 are 1602 samples, and the frames of sequence numbers 2 and 4 are 1601 samples. The sequence number is represented by bit b2
Ｂb0.

A two-word "Audio Sample"
"Count" includes bits c15 to c15 as shown in FIG.
This is a 16-bit counter in the range of 0 to 65535 using 0, and indicates the number of samples of each channel. Note that all channels have the same value in the element.

One-word "Stream Valid"
"Flags" indicates whether or not each stream of eight channels is valid. Here, when significant audio data is included in the channel, the bit corresponding to this channel is set to “1”, and otherwise, the bit is set to “0” and the bit is set to “1”. Only the audio data of the channel set to "" is transmitted.

[S2-s0] of [Data Area]
Is a data area for identifying each stream of eight channels. “F” indicates the start of a subframe.
“A23 to a0” are audio data, and “P,
"C, U, V" are channel status, user bit, V
The parity bits include parity bits, parity bits, and the like.

Next, metadata for an audio item will be described. Audio editing metadata (Aud
io Editing Metadata) is a combination of editing metadata, error metadata, and source coding metadata. As shown in FIG. 12, the audio editing metadata includes one word “Field / Frame fl”.
ags ", 1-word" Audio Editing "
Bitmap ", 1-word" CS Valid Bi
tmap "and" Channel Status "
Data ”.

The number of valid audio channels is determined by the “Stream Val” shown in FIG.
id Flags ". If the flag of “Stream Valid Flags” is set to “1”, “Audio E
"Diting Bitmap" becomes effective.

"Audio Editing Bitm"
“first editing flag” of “ap” is the first field, “Second editing flag”.
“lag” indicates information on the editing status in the second field, and indicates whether the editing point is before or after the field with this flag. "Error
“lag” indicates whether or not an error that cannot be corrected has occurred.

“CS Valid Bitmap” is
"Ch" of n (n = 6, 14, 18, or 22) bytes
"annule Status Data" header, which indicates which of the 24 channel status words is present in the data block. Here, "CS
Valid1 ”is“ Channel Status ”
This is a flag indicating whether or not there is data in 0 to 5 bytes of “Data”. "CS Valid2"-"CS
Valid4 ”is“ Channel Status ”
This is a flag indicating whether or not there is data in 6 to 13 bytes, 14 to 17 bytes, and 18 to 21 bytes of “Data”. In addition, "ChannelStatus
Data ”is set to 24 bytes, and 2
Depending on the data of the 22nd byte, whether or not there is data from 0 to 21 bytes is indicated.
The 3-byte data is used as a CRC from 0 to 22 bytes. In addition, "Fielded / Frame flag
The flag "s" indicates whether the audio data of eight channels is packed in frame units or field units.

A general data format (General Data Format)
Format) is used to carry all freeform data types. However, this free form data type does not include special auxiliary element types such as IT nature (word processing, hypertext, etc.).

Next, the configuration of a data transmission system for transmitting data in such an SDTI-CP format will be described.

As shown in FIG. 13, the video data and audio data of the program and the AUX
When transmitting data to a data recording / reproducing device 10 such as a server or a video tape recorder, a program from a plurality of data output devices 14-1 to 14-n is switched by using a matrix switcher 12 such as a router. To be stored in the data recording / reproducing device 10.

At the time of transmission of this program, for example, a stream of video data DVC-1 or uncompressed audio data DAU-1 compressed by the MPEG2 system is transmitted from the data output device 14-1 to the data transmission device 20T- After packaging in frame units by the above 1, the SDTI-
This data is converted into serial data CPS-1 as data in a CP format and output. Similarly, data from another data output device 14-n is packaged in frame units by the corresponding data transmission device 20T-n, and is converted into serial data CPS data as data in the SDTI-CP format.
Convert to -n and output. The signals SC-1 to SC-n are reference timing signals, for example, reference frame pulse signals. The video data is transmitted by the data transmission devices 20-1 to 20-n based on the reference timing signals SC-1 to SC-n. DV
Input processing such as C is performed.

The data transmission device 20R on the receiving side separates the packaged video data and audio data from the serial data CPS selected by the matrix switcher 12, and separates one frame of compressed video data and uncompressed audio data. The data is supplied to the data recording / reproducing device 10 and accumulated. The signal S
CR is a reference timing signal like the signal SC. Based on the reference timing signal SCR, output processing of the video data DVC or the like from the data transmission device 20R is performed.

Next, an outline of the configuration of the data transmission apparatus is shown in FIG.
4 will be described. The transmission-side data transmission device 20T and the reception-side data transmission device 20R have the same configuration. CPU interface unit 20 of data transmission device 20
1 is connected to a CPU (Central Processing Unit) 240. The CPU interface unit 201 has a plurality of registers. The plurality of registers are sequentially designated by the address signal SAD from the CPU 240, and the data signal SDT is supplied to the designated register to set “System Item Type” or “System Item Type”. System
m Item Bitmap "FEC Active
Flag, SMPTE Label and RefDate
/ Time, Current Date / Time, and a flag indicating the presence or absence of Control;
t Package Rate ”to“ Current
Data up to “Date / Time stamp” are stored. These registers are connected to an SDTI core unit 222 described later.

Further, the CPU interface unit 201 has a memory control unit 211 of the memory management unit 210.
Is provided. This register is a storage location of data to be written to an SDRAM unit 250 described later, and is stored in “Package MetaDa”.
ta Set ”to“ Control Element ”
When the data up to "t" is stored in this predetermined register,
The stored data is sequentially written to the SDRAM unit 250 via the memory control unit 211 and the like.

The compressed video data DVC is supplied to the memory control unit 211 via the interface unit 202. The uncompressed audio data DAU is supplied to the memory control unit 211 via the interface unit 203. When the AUX data DSX is supplied, the memory control unit 21
1 is supplied.

Here, the interface units 202 and 20
In step 3204, the number of words of the input data is counted in frame units, and not only the data but also the respective word count values VC, AC, XC are stored in the memory controller 211.
To supply. Also, the interface units 202, 203, 2
In step 04, a clock transfer process is performed, and data input from the outside at different frequencies is converted to an SDR to be described later.
The data is replaced with the clock frequency data of the AM unit 250.
In this clock transfer process, the data of each item is written to the memory in each interface unit based on the clock signal on the data output device side, and the data written to the memory is read by the clock signal of the SDRAM unit 250. , The clock is changed. For example, 8-bit video data DVC having a transmission rate of 27 MHz, 36 MHz or 54 MHz or 16-bit audio data DAU having a sampling frequency of 48 kHz is written in the memory and read at 81 MHz or 108 MHz which is the frequency of the clock signal of the SDRAM section 250. The clock is changed.

Further, the interface unit 203 performs serial-parallel conversion, converts serial audio data into parallel data having a bit number corresponding to the bus width of the SDRAM unit 250, and supplies the parallel data to the memory control unit 211.
The interface units 202 and 204 also convert the input data into a bit number corresponding to the bus width of the SDRAM unit 250 and supply the converted data to the memory control unit 211. Similarly, the CPU interface unit 201 counts the number of words for one frame of data to be written to the SDRAM unit 250, and outputs the word count value MC to the memory control unit 211.
And performs a clock changeover process and a conversion process to the number of bits according to the bus width.

The memory control unit 211 includes the SDRAM unit 2
50 to store data to be written,
Unit 2 for temporarily storing data read from
12 are connected. Here, when the SDRAM unit 250 can perform data transfer or read with maximum transfer efficiency by performing burst transfer with, for example, 32 bits and 16 words, the memory unit 212 stores a system item, a picture item, and an audio item. 32 bits 16 words for each of the AUX items
It is configured to have the memory capacity of the bank. By configuring the memory unit 212 in this manner, by performing data transmission while performing bank switching, while writing data supplied from the interface unit to one bank, the data of each item of the other bank is written in 32 bits. 1
The data can be supplied to the SDRAM unit 250 by burst transfer in six words.

In the memory control unit 211, the SDRAM unit 2
Memory unit 21 configured for data transfer with
When the number of input ports is one, the arbitration of the writing of the data DSY, the video data DVC, the audio data DAU and the AUX data DSX of the system item supplied via the interface units 201 to 204 is performed, and each data is sequentially transmitted. It is stored in the memory unit 212.
Thereafter, when data for burst transfer is stored in the memory unit 212, a write request signal WQ for writing the data to the SDRAM unit 250 is generated and supplied to the arbiter unit 213. Further, the interface unit 20
The word count values MC, VC, AC, and XC supplied from 1, 202, 203, and 204 are stored in the word count table unit 214 for each frame.

In the arbiter 213, the memory controller 21
Arbitration of a write request based on a write request signal WQ from the CPU 1 or a read request based on a read request signal RQ from the memory control unit 215 described later is performed. Here, the signals AKA and AKB indicating that the request has been accepted are transmitted to the memory control units 211 and 215.
Is supplied from the memory unit 212 to the SDRAM.
The data transfer to the unit 250 and the data transfer from the SDRAM unit 250 to the memory unit 216 are prevented from being performed simultaneously, and the data transfer is performed sequentially. Also, based on the word count value stored in the word count table unit 214, a control signal for writing and reading data to and from the SDRAM unit 250 is generated and supplied to the SDRAM control unit 220, so that each item can be controlled. Data of SDRAM section 250
Can be written correctly, and the written data can be read correctly.

The SDRAM control section 220 writes and reads data to and from the SDRAM section 250 by burst transfer based on a control signal from the arbiter section 213, and performs processing such as a refresh operation of the SDRAM section 250.

The arbiter section 213 has an SDRA
A memory unit 216 for temporarily storing data read from the M unit 250 by burst transfer is connected. This memory unit 216 is, like the memory unit 212, an SDRAM
It is configured to be able to write and read data with the maximum transfer efficiency with the unit 250.

Writing and reading of data in the memory unit 216 are controlled by the memory control unit 215,
Data is written at the clock frequency of the DRAM unit 250, and read is performed so that the written data is converted into serial data and output at the transmission frequency (for example, 270 Mbps) of the serial digital transfer interface. This memory unit 216
Is supplied to the SDTI core unit 222.

[0098] The memory control unit 215 uses an SDT described later.
A read request signal RQ is generated based on the data request signal DQ from the I core unit 222 and supplied to the arbiter unit 213. Data is read based on the read request signal RQ and supplied to the SDTI core unit 222 via the memory unit 216. Further, the amount of data stored in the memory unit 216 is determined, and if the amount of data decreases, the SDRAM unit 250
And a read request signal RQ for reading data from the arbiter unit 213. The SDTI core unit 222
Data based on the data request signal DQ from the memory unit 2
16 is written in the memory unit 216
Is supplied to the SDTI core unit 222.

In the SDTI core unit 222, the memory unit 21
The 8-bit item data read from 6 to 32 bits in 1-word units is converted into 10 bits. Also, CP
A system item is generated using information stored in a register of the U interface unit 201, or a picture item or an audio item is generated by adding header information or the like to video data or audio data. In the generation of each item, a CRC for error detection and an ECC for error detection and correction are added. Furthermore, "S
A fixed value such as "eparator" or "End Code" is generated and added, and codes EAV, SAV and header data are added. SD generated in this way
The data in the TI-CP format is converted into serial data CPS by the signal converter 260 and transmitted as a transmission packet of the serial digital transfer interface.

When this data transmission apparatus is used on the reception side, the processing is performed in a manner opposite to that on the transmission side.
That is, the serial data C
Convert PS to 10-bit parallel data and convert to SDTI
It is supplied to the core part 222. In the SDTI core unit 222,
An error detection process based on CRC and an error detection and correction process based on ECC are performed. Furthermore, "Separator"
The data of each item of the content package is separated using data such as “Item Type” and written into the memory unit 216. Further, the word count value included in the content package is extracted and stored in the word count table unit 214. Further, information on system items is supplied to the CPU interface unit 201,
Retrieve information about each item. Here, for example, information on an audio item, for example, “Elemen
t Header ”,“ 5-sequence cou ”
nt "and" Audio Sample Count "are taken out, and the interface unit 2
03.

The memory unit 216 is controlled by the memory control unit 215 as described above, and the memory control unit 2
At 15, the amount of data written to the memory unit 216 is determined. Here, when the data for the burst transfer to the SDRAM unit 250 is stored in the memory unit 216, a write request signal WQ for writing the data stored in the memory unit 216 to the SDRAM unit 250 is transmitted to the memory control unit 215.
From the arbiter unit 213.

The arbiter unit 213 includes the memory control unit 2
In response to the write request from the memory control unit 211 and the write request from the memory control unit 211, the data stored in the memory unit 216 is written to the SDRAM unit and stored in the word count table unit 214. The video data and audio data for one frame of each item are transferred to the SDRAM unit 2 based on the information on the number of words and the read request.
The data is read from the memory 50 and supplied to the memory unit 212.

The data written in the memory unit 212 is
The data is sequentially read out by the memory control unit 211 and supplied to the corresponding interface units 201 to 204. In each of the interface units 201 to 204, the clock is switched by a process reverse to that at the time of transmission, and the SDRAM unit 250
Is output as data having a clock frequency corresponding to the data recording / reproducing apparatus 10.

The timing generator 225 generates various timing signals based on a reference timing signal supplied from the outside and the received serial data CPS. The timing signal generated by the timing generator 225 is , Each interface section and arbiter section 2
13 and supplied to the SDTI core unit 222 and the like, and the operation of each unit is performed at a predetermined timing.

Here, a case where audio data separated from the received serial data is output from the interface unit 203 will be described. "5-seque" of the audio item "Element Header"
ance count "and" Audio Sample "
From the “Count”, the video frame frequency can be determined as shown in Table 1. For example, the sample count value 1602 is used for the sequence numbers 1, 3, and 5, and the sample count value 160 is used for the sequence numbers 2 and 4.
When 1, the video frequency is (30 / 1.001)
It can be determined that the frame rate is frames / second. When the sample count value is 801 in sequence numbers 1, 2, 4, and 5, and the sample count value is 800 in sequence number 3, it is determined that the video frame frequency is (60 / 1.001) frame / sec. Can be determined. Also, when the sequence number is 0 and the sample count value is 1920, 25 frames / second, when the sample count value is 960, 50 frames / second,
When the sample count value is 1600, 30 frames / second, when the sample count value is 800, 60 frames / second, and when the sample count value is 2002, the frequency (24 / 1.001) frame / second corresponding to the movie is used. When the count value is 2000, it can be determined that the frame rate is 24 frames / sec.

[0106]

[Table 1]

When the video frame frequency is determined in this manner, a reference sequence BFS for outputting audio data is generated using the determined video frame frequency as the reference timing signal on the receiving side.

FIG. 15 shows a reference sequence generation circuit for generating a reference sequence BFS which is a reproduction reference signal for outputting audio data. A clock signal WCK from an external device (for example, a data recording / reproducing device in the case of FIG. 13) using the received audio data is supplied to the counter 301. Also, the reference timing signal SCR
Alternatively, one of the audio start signals AST, which is an audio data output start signal supplied from an external device, is selected by the signal selection unit 302 and supplied to the reset signal generation unit 303.

The reset signal generation unit 303 is supplied with a timing signal FTM indicating a sequence switching from a reference sequence output unit 305 described later.
The counter 301 is based on either the reference timing signal SCR or the audio start signal AST.
At the same time, and the timing signal F
The counter control signal CCT for resetting the count value of the counter 301 by the TM is generated by the counter 30.
Feed to 1.

In the counter 301, the clock signal WCK
And supplies the count value CNT to the reference sequence output unit 305. In the video frame frequency discriminating unit 304, the SDTI core unit 22 serving as a data separating unit is used.
Based on the signal FA supplied from 2, the video frame frequency is determined using Table 1 described above, and the determination result FM is supplied to the reference sequence output unit 305.

The reference sequence output unit 305 generates a timing signal FTM based on the determination result FM of the video frame frequency and a count value CNS from a 5-frame counter 307, which will be described later, and supplies the timing signal FTM to the reset signal generation unit 303. Generate and output BFS.

Either the sequence number SNE supplied from the external device or the internally generated sequence number SNI is selected by the signal selection unit 306 and supplied to the 5-frame counter 307. 5 frame counter 307
Then, at the start of the operation, the sequence number selected by the signal selection unit 306 is fetched, counting is started from this sequence number, and the count value CNS is supplied to the reference sequence output unit 305.

For example, if the video frame frequency is (30 /
1.001) frame / second, the reference sequence output unit 305 outputs the timing signal F at the timing of 1601 count or 1602 count.
When the TM is generated and the count value of the 5-frame counter is “1”, the timing signal FTM is first generated at the timing of 1602 counts and supplied to the reset signal generation unit 303, and then the count value is 1601 , 1602, 1601, 1602, 160
At 2..., The timing signal FTM is generated and supplied to the reset signal generation unit 303. Therefore, the first sequence number is “1” from the reference sequence output unit 305.
Can be output.
Also, the count value of the 5-frame counter 307 is “4”.
, It is assumed that the timing signal FTM is first generated at the timing of 1601 counts and supplied to the reset signal generation unit 303, and thereafter, the count value becomes 1601.
By generating the timing signal FTM at 2, 1602, 1601, 1602, 1601... And supplying it to the reset signal generation unit 303, the reference sequence output unit 305 outputs the reference signal whose first sequence number is “4”. Sequence BFS can be output.

In this manner, a reference sequence of a five-frame sequence as shown in FIG. 11 can be generated. Similarly, when the determination result of the video frame frequency is another frame frequency, the reference sequence based on the video frame frequency can be generated and the first sequence number can be set. The audio data DAU is output from the interface unit 203 based on the reference sequence BFS.

As described above, the audio item “E”
“5-sequenc” by element header
e count "and" Audio Sample Co "
unt ", the video frame frequency can be determined, and the reference sequence B
Since the FS can be generated, for example, when processing only the data of the audio item, the audio data DAU can be correctly encoded based on the reference sequence BFS without including the information of the video frame frequency as the header information of the audio data. Can be output based on the

Here, the output of the audio data DAU will be described using the audio data output circuit shown in FIG. The audio data DAU read from the memory unit 212 is stored in a FIFO (Fir
(st-In First-Out) section 351. Further, the reference sequence BFS generated as described above is supplied to the comparing unit 352. As shown in FIG. 10, the comparison unit 352 stores “5-sequence” in the audio item.
ce counter ”is supplied, and the sequence data DSN is compared with the sequence number of the reference sequence BFS. Here, when the number of samples of the frame of the sequence number indicated by the reference sequence BFS is equal to the number of samples of the frame indicated by the sequence data DSN, the reference sequence BF
A write address counter clock ADCK having the same number of clocks as the number of samples of S is generated and supplied to the write address counter 353. When the number of samples of the sequence data DSN is larger than the number of samples of the reference sequence BFS, the write address counter clock ADCK having the number of clocks increased by one from the number of samples of the reference sequence BFS is generated and written. Address counter 3
53. Further, when the number of samples of the sequence data DSN is smaller than the number of samples of the reference sequence BFS, a write address counter clock ADCK having a clock number reduced by one from the number of samples of the reference sequence BFS is generated and written. Address counter 353
To supply.

In the write address counter 353 as the address control means, based on the write address counter clock ADCK from the comparator 352, the write address signal W
ADR is sequentially generated, and the write address signal W
Assuming that the ADR is supplied to the FIFO unit 351, the audio data DAU read from the memory unit 212 is sequentially written to the FIFO unit 351. Therefore, for example, when the number of samples is 1601 in the sequence number 2 of the reference sequence BFS, when the audio data of the sequence data 1 is read, the data is read one sample more than the number of samples of the reference sequence 2 and the sequence data is read. It is possible to read out all the audio data of 1602 samples of one. As described above, by comparing the sample number of the frame of the reference sequence BFS with the sample number of the frame of the sequence data, and adjusting the number of write clocks based on the comparison result, the audio data of each frame can be correctly read.

The read address signal RAD is read by the read address counter 357 constituting the read address control means.
R is generated, and the read position indicated by the read address signal RADR is updated (e.g., counted up) at a constant cycle. This read address signal RADR is applied to FI
By supplying the audio data to the FO unit 351, the audio data written in the FIFO unit 351 is sequentially read at a fixed cycle based on the read address signal RADR and output. The read address control means includes a read address counter 357, a delay unit 355 described later, and a comparison unit 356.
It consists of.

Further, the sequence data DSN is supplied to the delay unit 355 and to the comparison unit 352. The delay unit 355 delays the sequence data DSN by one frame and supplies it to the comparison unit 356. The comparing unit 356 compares the supplied sequence data DSN with the sequence data DSN ′ one frame before, and determines the continuity of the five-frame sequence, that is, the sequence numbers 1, 2, and
It is determined whether the order is 3, 4, 5, 1, 2, 3,..., And when the frame sequence data becomes discontinuous, the write address and read address of the FIFO unit 351 are compared. The read address setting signal SEAD is supplied to the read address counter 357 based on the comparison result.
The read address counter 357 generates a read address signal RADR based on the read address setting signal SEAD,
Audio data DA written to FIFO section 351
The phase of audio data is adjusted by controlling the read address position of U.

Here, when audio data of a 5-frame sequence is output, as shown in FIG. 17, the output phase of audio data is 5 with respect to the reference sequence BFS, that is, the sequence number of the reference sequence BFS is When “1”, the sequence number of the audio data, that is, the sequence data DSN is “1” to
The case of "5" occurs.

For this reason, as shown in FIG. 18, when the matrix switcher 12 switches the audio data of the program A of the 5-frame sequence to the audio data of the program B, the sequence numbers may become discontinuous. For example, at the end of sequence number 3 of program A,
, The sequence number becomes “1”, and the sequence numbers become discontinuous. As described above, the program is switched, and the sequence numbers become discontinuous.
When the sequence of 602 samples increases, the phase of the audio data is delayed. For example, when the sequence number of the reference sequence is “1”, the program of the output phase 1 is selected, and when the sequence number of the reference sequence is 2, the program of the output phase 2 is selected. Further, when the program with the output phase 3 is selected in the case of the reference sequence 3 and the program with the output phase 4 is selected in the case of the reference sequence 4, a sequence 1
Are successively selected. Here, since the number of samples is 1601 in the frames of sequence numbers 2 and 4 of the reference sequence, the phase of the audio data is delayed with respect to the reference sequence shown in FIG. 19B as shown in FIG. 19C. Further, when a program having a sequence number of 1601 samples is sequentially switched and selected, the phase of audio data is advanced as shown in FIG. 19D. FIG. 19A shows a frame signal.

As described above, when the number of samples decreases, the data at the same address is read twice to increase the number of data. When the number of samples increases, the data is read out by thinning out. As a result, the data amount is adjusted, and the phase of the audio data can be maintained in a correct state.

When the number of samples increases due to the switching of the program, for example, when switching from the program having the output phase 2 with the sequence number 1 of the reference sequence to the program having the output phase 3 with the sequence number 2 of the reference sequence,
The output timing is adjusted by outputting the data of the program of output phase 3 one sample earlier. The output timing may be adjusted by starting data output from the second sample of the program data of output phase 3.

When the number of samples is reduced by switching the program, for example, the sequence number 2 of the reference sequence
When the program of the output phase 1 is switched from the program of the output phase 1 to the program of the output phase 2 with the sequence number 3 of the reference sequence, the concealment process for compensating for the insufficient data is performed and the output timing is adjusted so that the phase of the audio data is correct. Things.

As described above, since the audio data of each frame can be read correctly, the sequence number of the reference sequence BFS is compared with the sequence data DNS of the audio item, and the phase data shown in FIG. By adjusting the output timing of the audio data so as to satisfy the following condition, the phase shift of the audio data can be prevented.

Further, by increasing the number of stages of the FIFO unit 351 shown in FIG. 16, even when the number of data increases or decreases due to the program switching, the data amount from the data write position to the data read position is variable. This eliminates the need to immediately perform processing such as double reading or thinning out of data, thereby simplifying the data amount adjustment processing. In this case, in the data amount adjustment processing, the write address signal WADR and the read address signal RADR are supplied to the comparing section 356 so that the address difference is FIFO.
When the number of stages is larger than the number of stages of the unit 351 or when data is read by a read address before data is written, for example, the address position indicated by the read address signal RADR output from the read address counter 357 is changed. By changing the read address setting signal SEAD, data is read twice, thinned out, and the like, and the data amount is adjusted.

In the above-described embodiment, data is packetized in units of frames. However, data may be packaged in units of pictures, such as an MPEG I-picture, B-picture, or P-picture. Of course it is good.

[0128]

According to the present invention, the audio data separated from the received transmission packet is once stored in the output buffer means, read out and output at a predetermined speed, and stored in the output buffer means. A reference sequence generated on the receiving side as a reference for data output is compared with the frame sequence data separated from the received transmission packet, and the address of the output buffer means is controlled based on the comparison result. Therefore, even when the number of audio samples based on the reference sequence and the number of audio samples based on the frame sequence data are different, audio data can be correctly output.

Further, the output buffer means writes audio data of a data amount based on the reference sequence,
Based on the comparison result, the write address of the output buffer is controlled to adjust the amount of audio data written to the output buffer. For this reason, the audio data can be sequentially stored in the output buffer means without omission.
Further, for example, when the frame sequence data becomes discontinuous, the write address and the read address of the output buffer are compared, and the read address of the output buffer is controlled based on the comparison result. Therefore, even if the number of audio samples increases or decreases due to the switching of the program, the audio phase can be correctly adjusted.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining an SDTI-CP format.

FIG. 2 is a diagram showing formats of a code EAV and header data.

FIG. 3 is a diagram showing a format of a variable-length block.

FIG. 4 is a diagram showing a configuration of a system item.

FIG. 5 is a diagram showing a configuration of a time code.

FIG. 6 is a diagram showing a configuration of a metadata set.

FIG. 7 is a diagram illustrating a configuration of another item except a system item.

FIG. 8 shows M in an SDTI-CP element frame.
It is a figure showing the format of PEG-2 V-ES.

FIG. 9 is a diagram showing a configuration of MPEG-2 picture editing metadata.

FIG. 10 is a diagram showing a configuration of an element data block of an audio item.

FIG. 11 is a diagram illustrating a 5-frame sequence.

FIG. 12 is a diagram showing a configuration of audio editing metadata.

FIG. 13 is a diagram illustrating a configuration of a data transmission system.

FIG. 14 is a diagram illustrating an outline of a configuration of a data transmission device.

FIG. 15 is a diagram illustrating a configuration of a reference sequence generation circuit.

FIG. 16 is a diagram showing a configuration of an audio data output circuit.

FIG. 17 is a diagram for explaining an output phase of a 5-frame sequence.

FIG. 18 is a diagram illustrating an operation when a program is switched.

FIG. 19 is a diagram for explaining a phase shift of audio data.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Data recording / reproducing apparatus, 12 ... Matrix switcher, 14 ... Data output apparatus, 20 ... Data transmission apparatus, 201, 202, 203, 204 ...
Interface unit, 210: memory management unit, 211, 215: memory control unit, 212, 21
6: memory unit, 213: arbiter unit, 214
... Word count table section, 220 ... SDR
AM control section, 222 ... SDTI core section, 2
25 timing generator, 250 SDRAM
Unit, 260 ... signal conversion unit, 301 ... counter,
302, 306: Signal selection unit, 303: Reset signal generation unit, 304: Video frame frequency determination unit, 305: Reference sequence output unit, 307 ...
Frame counter, 351,... FIFO unit, 352,
356: comparison unit, 353: write address counter, 355: delay unit, 357: read address counter

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5C025 AA23 BA14 BA22 BA27 CA19 CB08 DA04 5C026 DA24 DA25 DA27 5K028 EE03 KK03 KK13 MM17 SS26 5K030 GA11 HB01 HB02 HB15 HB28 KX13 LD07 MA13 MB11

Claims (8)

[Claims] 1. A section of one line of a video frame is divided into an end synchronization code area in which an end synchronization code is inserted, an auxiliary data area in which auxiliary data is inserted, and a start synchronization code area in which a start synchronization code is inserted. And a payload area in which data including at least audio data is inserted, and the audio data is provided in a header area of the payload area corresponding to an audio data block area in which the audio data is inserted. A data reception method for receiving a transmission packet of a serial digital transfer interface into which frame sequence data for phase management is inserted, wherein said audio data separated from said received transmission packet is once stored in an output buffer means, and then stored at a predetermined speed. And output the data, and store the data in the output buffer means. The reference sequence generated on the receiving side serving as a reference for the output of the received data is compared with the frame sequence data separated from the received transmission packet, and the address of the output buffer means is controlled based on the comparison result. A data receiving method. 2. The output buffer means according to claim 1, wherein said output buffer means writes said audio data in a data amount based on said reference sequence, and controls a write address of said output buffer means based on said comparison result. 2. The data receiving method according to claim 1, wherein the data amount of the audio data written in the data is adjusted. 3. The data receiving method according to claim 1, wherein a write address and a read address of said output buffer means are compared, and a read address of said output buffer means is controlled based on a result of the comparison. . 4. A continuity of the frame sequence data for each of the video frames is determined, and when the frame sequence data becomes discontinuous, a write address and a read address of the output buffer means are compared. 4. The data receiving method according to claim 3, wherein: 5. A one-line section of a video frame is divided into an end synchronization code area in which an end synchronization code is inserted, an auxiliary data area in which auxiliary data is inserted, and a start synchronization code area in which a start synchronization code is inserted. And a payload area into which data including at least audio data is inserted, and the audio data is provided in a header area of the payload area corresponding to an audio data block area into which the audio data is inserted. A data receiving apparatus for receiving a transmission packet of a serial digital transfer interface into which frame sequence data for phase management has been inserted, a data separating unit for separating the audio data and the frame sequence data from the received transmission packet; Output for storing audio data separated by data separation means Buffer means, a reference sequence generating means for generating a reference sequence serving as a reference for output of data stored in the output buffer means, and a reference sequence generated by the reference sequence generating means and separated from the received transmission packet. A data receiving apparatus comprising: an address control unit that compares the frame sequence data and controls an address of the output buffer unit based on a comparison result. 6. The output buffer means writes the audio data of a data amount based on the reference sequence, and the address control means controls a write address of the output buffer means based on the comparison result. 6. The data receiving apparatus according to claim 5, wherein the data amount of the audio data written to said output buffer means is adjusted. 7. A read address control means for comparing a write address and a read address of the output buffer means, and controlling a read address of the output buffer means based on a result of the comparison. 6. The data receiving device according to 5. 8. The read address control means determines the continuity of sequence data by comparing the frame sequence data for each of the video frames, and determines that the frame sequence data has become discontinuous. 8. The data receiving apparatus according to claim 7, wherein a write address and a read address of said output buffer means are compared when said data is read.