JP2000306384A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the power consumption of a write circuit in a semiconductor memory. SOLUTION: The write operation of this semiconductor memory is performed in such a way that a write circuit 2 gives a potential difference to a memory cell 1 via a pair of data lines DW an DWB, a pair of amplitude limitation transfer transistors Q3 and Q4 and a pair of selection transfer transistors Q1 and Q2. During the write operation, the amplitude limitation transfer transistors lower the potential of a potential riseing side digit line by a Vth level from a VDD level or a VINT level.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a write circuit of a semiconductor memory device, and more particularly to a measure for reducing current consumption of a write circuit.

[0002]

2. Description of the Related Art With the speeding up of LSI, DRAM, SR
It is desired to increase the data rate of a semiconductor memory device such as an AM. In a semiconductor memory device, when the data rate is increased, the power consumption of a data circuit becomes particularly large as compared with an address decoder system. This has been dealt with by increasing the bus width in accordance with the increase in speed in the data circuit, so that the number of address system signals is 10 to 20, while the number of data system signals is 100. This is due to the fact that it has become quite large.

FIG. 11 is a circuit diagram of a first conventional semiconductor memory device (SRAM). The SRAM includes a plurality of memory cells 1 arranged in an array in the column and row directions, a write circuit 2 for writing to a memory cell 1 selected by a word line and a digit line, and a digit line from the plurality of memory cells 1. And a sense circuit (not shown) for reading stored data.

Each memory cell 1 includes a pair of transfer transistors Q1, Q2 and a transfer transistor Q.
1, storage node N connected to digit line via Q2
1, a storage unit 10 having N2. Storage unit 10
Is composed of a pair of inverters whose inputs and outputs are connected to each other.

Writing is performed by setting the word line to VDD, one digit line to VDD, and the other digit line to GND level.

FIG. 12 is a diagram showing potential changes during a write operation of each node of the semiconductor memory device of FIG. In this example, the write operation is performed by digit line D and storage node N1.
Is at L level, digit line DB and storage node N2 are at H level.
Level, the digit line D and the storage node N
1 is at the H level, and the digit line DB and the storage node N2 are inverted to the L level. At the time of writing in which this state is inverted (hereinafter referred to as inverted writing), there is a maximum potential difference of VDD between the digit line D or DB and the storage node N1 or N2. Electric current flows. The power supply voltage fluctuates and the current consumption increases due to the peak current.

FIG. 13 is a circuit diagram of a second prior art SRAM. This semiconductor memory device includes an internal voltage generating circuit 4 for generating an internal voltage VINT lower than the power supply voltage VDD in order to suppress a peak current flowing at the time of inversion writing. By setting the potential of the digit line D to the VINT-Vth level, the peak current in the first conventional example is further reduced.

[0008]

However, in the second conventional example, although the peak current can be reduced as compared with the first conventional example, the current consumption for driving the pair of digit lines D and DB is almost entirely internal. Since the load current is the load current I1 of the voltage generation circuit 4, there is a problem that the area occupied by the internal voltage generation circuit 4 for supplying the load current I1 increases.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art. In a write circuit of a semiconductor memory device, a peak current in a write operation is suppressed and the entire occupied area is reduced. It is an object of the present invention to provide a semiconductor memory device in which the number is reduced.

[0010]

In order to achieve the above object, a semiconductor memory device according to the present invention comprises a pair of transfer gates and a pair of inverters whose inputs and outputs are connected to each other by crossing each other. A latch circuit having a data storage section forming a pair of storage nodes connected to a pair of digit lines via the transfer gate, and a write signal supplied with a write voltage and setting the write voltage to a high level And a write circuit for inputting the write signal to the latch circuit via the digit line, wherein the write signal is output to the write circuit or between the write circuit and the latch circuit. A voltage-limited n-channel transistor, and the voltage-limited n-channel transistor provides a high-level Le a, and limits below threshold by the low potential of the voltage limiting n-channel transistor than the write voltage.

According to the semiconductor memory device of the present invention, the write voltage is limited to n by the voltage-limited n-channel transistor.
By lowering only the threshold value of the channel transistor, the current consumption in the writing operation can be reduced.

In the semiconductor memory device according to the present invention, the gate of the voltage-limited n-channel transistor can be maintained at the write voltage.

In the semiconductor memory device according to the present invention, it is preferable that a threshold value of the voltage-limited n-channel transistor is lower than a threshold value of the transfer gate. In this case, even if there is a parasitic resistance component in series and a parasitic capacitor component in parallel on the pair of digit lines, the potential rises during inversion writing until one of the digit lines reaches a predetermined level of potential. Time can be shortened.

In a preferred embodiment of the present invention, the power supply potential of the latch circuit is lower than the write voltage, and the gate of the n-channel transistor is maintained at the power supply potential of the latch circuit. In this case, the current consumption of the write circuit can be further reduced.

The present invention can be applied to both DRAM and SRAM. When applied to an SRAM, the latch circuit forms an SRAM memory cell,
When applied to a DRAM, a write voltage supply circuit for supplying a write voltage to a DRAM memory cell is configured.

Further, in a preferred embodiment of the present invention, the gate of the voltage-limited n-channel transistor is set to a logic that sets the write voltage to a high level. In this case, the writing circuit can also be used.

The write circuit includes a pair of a write p-channel transistor and a write n-channel transistor whose write command is input to a gate,
The voltage-limited n-channel transistor has a gate maintained at the write voltage, and is inserted between the write p-channel transistor and the write n-channel transistor, and the write signal is It is also a preferred embodiment of the present invention that the voltage is output from a connection node between the voltage-limited n-channel transistor and the writing n-channel transistor. In this case, write n
The driving capability of the channel transistor becomes advantageous.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor memory device according to an embodiment of the present invention will be described below with reference to the drawings. FIG.
FIG. 2 is a circuit diagram of the SRAM according to the first embodiment of the present invention.

The SRAM includes a plurality of memory cells 1 arranged in an array in the column and row directions, a write circuit 2 for writing to a memory cell 1 selected by a word line and a digit line, and a plurality of memory cells 1 And a sense circuit for reading a memory written via a digit line.

Each memory cell 1 is connected to a pair of digit lines D and DB via a pair of select transfer gate N-type transistors (hereinafter, referred to as transfer transistors) Q1 and Q2 and transfer transistors Q1 and Q2. A storage unit 10 having storage nodes N1 and N2. The storage unit 10 includes a pair of inverters M1 and M2 whose inputs and outputs are connected to each other. Each memory cell 1 is connected to the write circuit 2 via the amplitude limiting transfer transistors Q3 and Q4. The gates of the amplitude limiting transfer transistors Q3 and Q4 are
Both are connected to VDD.

The write circuit 2 includes a write control circuit 3 and a pair of drivers 8. Driver 8
Channel MOSFET Q5 and N-channel MOSFET
Q6. The source of the P-channel MOSFET Q5 is connected to the power supply voltage VDD, the drain is connected to the drain of the N-channel MOSFET Q6 and used as an output of the driver 8, and the gate is connected to the gate of the N-channel MOSFET Q6 and used as an input of the driver 8. N channel MOS
The source of the FET Q6 is connected to the ground (GND).

The write control circuit 3 has a pair of write output lines W and WB for outputting complementary signals.
And WB respectively connect to the inputs of the first and second drivers 8 respectively. The outputs of the first and second drivers 8 are respectively
Connect to data lines DW and DWB. Write control circuit 3
Are inverted by the driver 8 and output to the pair of data lines DW and DWB. A pair of complementary signals output to the data lines DW and DWB are H
The level side is the VDD level, and the L level side is the GND level.

The data lines DW and DWB are connected to digit lines D and DB via transfer transistors Q3 and Q4, respectively, comprising NMOSFETs for limiting the amplitude of the digit lines.
4 are connected to the power supply VDD. Storage nodes N1 and N2 of memory cell 1 are connected to digit lines D and D via transfer transistors Q1 and Q2, respectively.
B, and the gates of the transistors Q1 and Q2 are connected to the word line WL.

FIG. 2 is a time chart showing a potential change at each node of the SRAM of FIG. The SRAM performs an inversion write operation from an initial state in which the storage node N1 and the digit line D are at the GND level, and the storage node N2 and the digit line DB are at the VDD level.

First, the word line WL is set to the VDD level,
Transfer transistor Q1 of the selected memory cell
And Q2 are turned on. Next, the write circuit 2 sets the data line DW to the VDD level and sets the data line DWB to the GND level. As a result, the potential of the storage node N1 of the memory cell 1 rises from the GND level to the VDD level,
The storage node N2 of the memory cell 1
The potential drops to the ND level.

Here, the amplitude limiting function of the N-channel MOSFET will be described. When a memory cell 1 is selected during a write operation, a selection transfer transistor Q1 which is an N-channel MOSFET and an N-channel MOS
Amplitude limiting transfer transistor Q3 which is FET
, Both gates are at the VDD level. The storage node N1 goes to the VDD level with respect to the select transfer transistor Q1, which is an N-channel MOSFET, due to the effect of raising the potential of the P-channel MOSFET forming the internal circuit of the inverter M1. However, digit line D has VDD-Vth level because there is no effect of raising the potential of P-channel MOSFET with respect to amplitude limiting transfer transistor Q3.

By this amplitude limiting action, the potential difference between digit line D and storage node N1 which occurs at the time of inversion writing is suppressed to VDD-Vth level at the maximum. Thereby, the peak current flowing from the write circuit 2 is also suppressed.

After the write operation, a potential difference Vth is generated between the drain and source of the selected transfer transistor Q1 and between the gate and source, but since the transfer transistor Q1 is turned off, a through current flows between the drain and source. Absent. Therefore, the current consumption of the write circuit 2 is not affected.

According to the above embodiment, the gate potential is set to V
The current consumption of the write circuit 2 can be reduced by the amplitude limiting function provided with the N-channel MOSFET maintained at the DD level.

FIG. 3 shows an SRA according to the second embodiment of the present invention.
It is a circuit diagram of M. The SRAM of the present embodiment differs from the previous embodiment in that the SRAM of the present embodiment includes an internal voltage generation circuit 4 for generating an internal voltage VINT.

In the SRAM, in order to limit the signal amplitude,
An internal voltage generation circuit 4 is provided. Internal voltage generation circuit 4
Generates an internal voltage VINT lower than the power supply voltage VDD, and supplies the internal voltage VINT to the memory cell 1 and the gates of the amplitude limiting transfer transistors Q3 and Q4. Since the internal voltage generating circuit 4 is configured as a series type power supply circuit in which a transistor for maintaining the output voltage at VINT is connected in series between the input and the output, the operating current I2 is almost the same as the load current I1. Become.

FIG. 4 is a time chart showing potential changes at each node of the SRAM of FIG. In the inversion write operation, the amplitude limiting transfer transistor Q3 suppresses the potential of the digit line D to the level of VINT-Vth.
After the write operation, a potential difference Vth occurs between the drain and the source of the selection transfer transistor Q1, but the current consumption is not affected for the same reason as in the previous embodiment.

According to the above embodiment, the power supply voltage VDD
And an internal voltage generation circuit 4 for generating an internal voltage VINT lower than VINT-Vth.
By setting the level, the current consumption of the writing circuit 2 can be further reduced.

FIG. 5 shows an SRA according to a third embodiment of the present invention.
It is a circuit diagram of M. In the SRAM of the present embodiment, a parasitic resistance component R and a parasitic capacitor component C are provided on the digit lines D and DB, and are illustrated. The difference from the previous embodiment is that the amplitude limiting transfer transistors Q3 and Q4 have Vth lower by ΔV than the selective transfer transistors Q1 and Q2.

FIG. 6 is a time chart showing a change in each potential when the Vth of the amplitude limiting transfer transistors Q3 and Q4 is the same as the Vth of the selection transfer transistors Q1 and Q2 in the SRAM of FIG.

In the inversion write operation, the node between the amplitude limiting transfer transistor Q3 and the digit line D is
Although the potential goes to the VINT-Vth level, the digit line D
Due to the above time constant CR, the node between the digit line D and the select transfer transistor Q1 takes a time t until the potential rise speed is delayed and reaches the VINT-Vth level.
Takes one.

FIG. 7 is a time chart showing changes in each potential of the SRAM of FIG. Since the potential at the node connecting the amplitude limiting transfer transistor Q3 and the digit line D is at the level of VINT−Vth + ΔV, the node connecting the digit line D and the select transfer transistor Q1 is determined by the time constant CR on the digit line D. Even if the rising speed of the potential is delayed, the time t2 until the potential reaches the VINT-Vth level is shorter than the time t1 in FIG.

Further, making the Vth of the amplitude limiting transfer transistors Q3 and Q4 lower by ΔV than the Vth of the selection transfer transistors Q1 and Q2 means that both the amplitude limiting transfer transistors Q3 and Q4 are structurally different from each other at the time of manufacturing. , A difference in the P-substrate potential of the N-channel MOSFET, or a difference in the gate potential of the N-channel MOSFET. The same effect can be obtained by any method. . To make the P substrate potential of the N-channel MOSFET different, the P substrate potential of both the amplitude limiting transfer gates Q3 and Q4 is set to 0V.
In addition, when the P substrate potential of both the select transfer gates Q1 and Q2 is set to -1V, the value of ΔV becomes 0.2V to 0.3V.
About V. To make the gate potential of the N-channel MOSFET different, the gate potentials of both the amplitude limiting transfer gates Q3 and Q4 are set to VINT-Vth +
Set to ΔV level.

According to the above-described embodiment, even when the parasitic resistance R is in series and the parasitic capacitor C is in parallel on a pair of digit lines, one digit line whose potential rises at the time of inversion writing is at a predetermined level. Can be shortened until the potential reaches the potential of

FIG. 8 is a circuit diagram of a semiconductor memory device according to the fourth embodiment. The semiconductor storage device (DR
AM), the memory circuit at the subsequent stage viewed from the storage nodes N1 and N2 is configured by DRAM type memory cells.
That is, the present embodiment is an example in which the present invention is applied to a DRAM.

The DRAM of this embodiment includes a latch type sense amplifier 7 and a current control circuit 9 for driving the DRAM type memory cell array 6. The DRAM type memory cell array 6 includes a pair of DRAM type memory cells 5,
And a pair of memory cell control lines PW1, PW2 and a pair of bit line select transfer transistors QC3, QC4
It consists of. The DRAM type memory cell array 6 of the present DRAM includes 256 or 51 DRAM type memory cells 1.
Although there are two, only the specific memory cell 1 and each component connected thereto are shown.

The DRAM type memory cell 5 includes a transfer transistor QC1 and a memory cell capacitor CC.
1 and has a selection input terminal and a bit input / output terminal. In the DRAM type memory cell 5, the selection input terminal is directly connected to the gate of the transfer transistor QC1, and the bit input / output terminal and the ground GND are connected in this order by the transfer transistor QC1 and the memory cell capacitor CC1.

In each DRAM type memory cell 5, a selection input terminal is connected to a pair of memory cell selection signal lines PW1 and PW2, respectively, and a bit input / output terminal is connected to a pair of bit lines BT and BN, respectively.

The current control circuit 9 is supplied with the internal voltage VINT from the internal voltage generation circuit 4 and generates a pair of current control lines SA.
Output signals to P and SAN. The latch type sense amplifier 7 includes P-channel MOSFETs Q9 and Q11 and N-channel MOSFETs Q10 and Q12. The drains of the P-channel MOSFET Q9 and the N-channel MOSFET Q10 are connected to the storage node N1 by the P-channel MO.
The gates of the SFET Q11 and the N-channel MOSFET Q12 are all connected. The gates of the P-channel MOSFET Q9 and the N-channel MOSFET Q10 are connected to the storage node N2, and the drains of the P-channel MOSFET Q11 and the N-channel MOSFET Q12 are connected. The current control line SAP includes P-channel MOSFETs Q9 and Q11.
And the sources of N-channel MOSFETs Q10 and Q12 are connected to the current control line SAN. A pair of storage nodes N1 or N2 are connected to a pair of bit lines BT or BN via a pair of bit line selection transfer transistors QC3 or QC4, respectively. The sense amplifier selection signal line YD is connected to the gates of the selection transfer transistors Q1 and Q2 instead of the word line WL.

At the time of the write operation, the DRAM is connected to the sense amplifier selection signal line YD and the pair of memory cell selection signal lines PW
1, PW2 and the bit selection signal line TG are set to predetermined levels, and the current control circuit 9 sets the potential of the current control line SAP to the VINT level and sets the potential of the current control line SAN to GND.
To level.

Also in the DRAM, the gate potential is set to VIN
The amplitude limiting function provided with the N-channel MOSFET maintained at the T level has the same effect of suppressing the peak current at the time of inversion writing of the writing circuit 2.

According to the embodiment, even in the case of a DRAM, the current consumption of the write circuit 2 can be reduced.

FIG. 10 is a circuit diagram of a semiconductor memory device according to the fifth embodiment. The semiconductor memory device of the present embodiment is
The position to connect the amplitude limiting transfer transistor is
It differs from the previous embodiment in that the digit line is replaced in the write circuit.

The write circuit 2A of the semiconductor memory device of the present embodiment comprises a write control circuit 3 and a pair of drivers 8
A. The driver 8A is a P-channel MOSF
ETQ5, N-channel MOSFET Q6, and amplitude limiting transfer transistor Q3, and have a driver input and a driver output.

The driver input of the driver 8A includes a MOS
The gates of the FETs Q5 and Q6 are connected. Driver 8
The driver output of A is connected to the source of the N-channel MOSFET Q3 and the drain of the N-channel MOSFET Q6. The P-channel MOSFET Q5 has a source connected directly to VDD and a drain connected to the drain of the amplitude limiting transfer transistor Q3. N-channel MOSFE
TQ6 connects the source directly to GND. A pair of first
Alternatively, the second driver 8A connects the driver input to a pair of output lines W or WB of the write control circuit 3, and connects the driver output to a pair of digit lines D or DB, respectively.

FIG. 9 is a circuit diagram of the peripheral portion of the write circuit 2 in FIG. When the SRAM of FIG. 1 performs the inversion writing, the potential of the digit line D on the potential rising side is set to the VDD-Vth level via the P-channel MOSFET Q5 of the first driver 8 and the amplitude limiting transfer transistor Q3. Further, the potential of the digit line DB on the potential falling side is set to the GND level via the amplitude limiting transfer transistor Q4 and the N-channel MOSFET Q6 of the second driver 8.

Returning to FIG. 10, when performing reverse writing,
Via the P-channel MOSFET Q5 of the first driver 8 and the amplitude limiting transfer transistor Q3,
As in the previous embodiment, the potential of the digit line D on the potential rising side is set to the VDD-Vth level. Further, in the present semiconductor memory device, the digit line DB on the potential falling side is connected to the second
Of the driver 8 via the N-channel MOSFET Q6.

According to the above embodiment, the N of the driver 8
The driving capability of the channel MOSFET Q6 becomes advantageous.

In the semiconductor memory devices of the first, second, third, fourth, and fifth embodiments, the DC bias is applied to the gates of the amplitude limiting transfer transistors Q3 and Q4 as described above. To fix the potential, but DC
Instead of the bias, a signal incorporating logic can be applied to the gate. In this case, the writing circuit can be shared. (Embodiment 6)

As described above, the present invention has been described based on the preferred embodiment. However, the semiconductor memory device of the present invention is not limited to the configuration of the above-described embodiment, but rather the configuration of the above-described embodiment. Various modifications and changes of the present invention are also included in the scope of the present invention.

[0056]

As described above, according to the semiconductor memory device of the present invention, the amplitude limiting effect provided by the N-channel MOSFET having the gate potential maintained at a predetermined level is achieved.
During the write operation, the peak current can be suppressed and the current consumption of the write circuit can be reduced. Also, by reducing the current consumption of the write circuit, the area occupied by the internal voltage generation circuit can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a time chart showing a potential change of each node of the semiconductor memory device of FIG. 1;

FIG. 3 is a circuit diagram showing a semiconductor memory device according to a second embodiment of the present invention.

FIG. 4 is a time chart showing a potential change of each node of the semiconductor memory device of FIG. 3;

FIG. 5 is a circuit diagram showing a semiconductor memory device according to a third embodiment of the present invention.

6 is a time chart showing potential changes in the semiconductor memory device of FIG. 5 under assumed conditions.

FIG. 7 is a time chart showing potential changes at respective nodes of the semiconductor memory device of FIG. 5;

FIG. 8 is a circuit diagram showing a semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 9 is a circuit diagram showing the periphery of a write circuit of FIG. 1;

FIG. 10 is a circuit diagram showing a write circuit according to a fifth embodiment of the present invention.

FIG. 11 is a circuit diagram showing a semiconductor memory device of a first conventional example.

FIG. 12 is a time chart showing a potential change of each node of the semiconductor memory device of FIG. 11;

FIG. 13 is a circuit diagram showing a semiconductor memory device of a second conventional example.

FIG. 14 is a time chart showing a potential change of each node of the semiconductor memory device of FIG. 13;

[Explanation of symbols]

REFERENCE SIGNS LIST 1 memory cell 2 write circuit 3 write control circuit 4 internal voltage generating circuit 5 DRAM type memory cell 6 DRAM type memory cell array 7 latch type sense amplifier 8 driver 9 current control circuit 10 storage section VDD power supply voltage VINT internal voltage Vth gate threshold Value voltage I1 Load current I2 Operating current WL Word line D, DB digit line DW, DWB Data line W, WB Write output line N1, N2 Storage node PW1, PW2 Memory cell selection signal line BT, BN Bit line TG Bit line selection signal Line YD Sense amplifier selection signal line SAP, SAN Sense amplifier control signal line M1, M2 Inverter Q1, Q2 Select transfer transistor Q3, Q4 Amplitude limit transfer transistor Q5 to Q12 MOSFET QC1 Memory cell transistor CC1 Riseru capacitor QC3, QC4 parasitic capacitor of the bit line select transfer transistor parasitic resistance component C digit line R digit line content

Claims (8)

[Claims] 1. A pair of transfer gates and a pair of inverters whose inputs and outputs are connected to each other with a cross, and outputs of the pair of inverters are connected to a pair of digit lines via the transfer gates. A latch circuit having a data storage unit forming a storage node,
A write circuit for supplying a write voltage, outputting a write signal for setting the write voltage to a high level, and inputting the write signal to the latch circuit via the digit line; Or, between the write circuit and the latch circuit, a voltage-limited n-channel transistor is provided, and the voltage-limited n-channel transistor sets the high level of the write signal to be higher than the write voltage. A semiconductor memory device, wherein the potential is limited to a potential lower than the threshold of an n-channel transistor. 2. The semiconductor memory device according to claim 1, wherein a gate of said n-channel transistor is maintained at said write voltage. 3. A threshold value of the n-channel transistor is lower than a threshold value of the transfer gate.
The semiconductor memory device according to claim 1. 4. The latch circuit according to claim 1, wherein a power supply potential of said latch circuit is lower than said write voltage, and a gate of said n-channel transistor is maintained at a power supply potential of said latch circuit. Semiconductor storage device. 5. The semiconductor memory device according to claim 1, wherein said latch circuit forms an SRAM memory cell. 6. The semiconductor memory device according to claim 1, wherein said latch circuit is configured as a write voltage supply circuit for supplying a write voltage to a pair of DRAM memory cells. 7. The semiconductor memory device according to claim 1, wherein a gate of said voltage-limited n-channel transistor is set to a logic that sets said write voltage to a high level. 8. The write circuit includes a pair of a write p-channel transistor and a write n-channel transistor whose write command is input to a gate, wherein the voltage-limited n-channel transistor maintains the write voltage. The write signal is inserted between the write p-channel transistor and the write n-channel transistor, and the write signal is applied to the voltage-limited n-channel transistor and the write n-channel transistor. The output from the connection node of
8. The semiconductor memory device according to any one of claims 1 to 7.