JP2000347619A - Driving method of plasma display panel - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain good image display even when the pulse width of driving pulse is shortened to make hardly generate erroneous discharge and by generating maintenance discharge of an intial time portion on a discharge cell which belongs to a part of display line group, then writing picture element data in discharge cells which belong to remaining display groups, and generating remaining maintenance discharge on all the discharge cells at completing. SOLUTION: In a printing process Pc, within display in PDP of the first - the second (n) line, priming discharge is generated against discharge cells which belong to a display line group (display line group B) of the n+1 - the second (n) line. When a first light emission maintenance process Ic1 and the priming process Pc are completed, a second picture element writing process Wc2 is executed. In the second picture element data writing process Wc2, writing of picture element data is executed against the discharge cells which belong to the display line group B. When this is completed, the second light emission maintenance process Ic2 is executed. In the second light emission maintenance process Ic2, maintenance pulse of positive polarity IPx2, IPy2 are alternately and repeatedly impressed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for driving a plasma display panel.

[0002]

2. Description of the Related Art In recent years, as display devices have become larger in size, thinner ones have been required, and various thin display devices have been put to practical use. An AC discharge type plasma display panel is receiving attention as one of the thin display devices. FIG. 1 is a diagram showing a schematic configuration of a plasma display device including such a plasma display panel and a driving device for driving the plasma display panel.

In FIG. 1, a PDP 10 as a plasma display panel has m column electrodes D _{1 to} D _m as data electrodes, and n row electrodes X each arranged so as to cross each of the column electrodes. and a ₁ to X _n and row electrodes Y ₁ to Y _n. The row electrode is a pair of X and Y PDP.
, A row electrode corresponding to one row is formed. The column electrode D and the row electrodes X and Y are formed on each of two glass substrates disposed so as to face each other with a discharge space therebetween, and are formed in one pixel at the intersection between each row electrode pair and the column electrode. The structure is such that corresponding discharge cells are formed.

At this time, since each discharge cell emits light by utilizing a discharge phenomenon, it has only two states of "light emission" and "non-light emission". That is, the lowest luminance (non-light emitting state)
Thus, only the luminance of two gradations of the maximum luminance (light emission state) can be expressed. Therefore, the driving device 100 performs the gradation driving using the subfield method on the PDP 10 in order to realize the halftone luminance display corresponding to the input video signal.

In the subfield method, an input video signal is converted into, for example, 4-bit pixel data corresponding to each pixel, and one field is shown in FIG. 2 corresponding to each of these 4-bit bit digits. Thus, it is divided into four subfields SF1 to SF4. FIG. 3 is a diagram showing the application timing of various drive pulses applied to the row electrode pairs and the column electrodes of the PDP 10 by the drive device 100 within one subfield.

[0006] As shown in FIG.
00 is a positive reset pulse RP_XTo row electrode X₁~ X
_n, Negative reset pulse RP_YIs the row electrode Y₁~ Y_nMark on
Add. These reset pulses RP_xAnd RP_YTo the application of
Accordingly, all discharge cells of PDP 10 are reset discharged.
And a predetermined amount of wall charge is uniformly formed in each discharge cell.
You. Immediately thereafter, the driving device 100 generates the erase pulse EP.
Row electrode X of PDP10 ₁~ X_nAre applied simultaneously. to this
Therefore, an erasing discharge is generated in all the discharge cells, and
The charge disappears (simultaneous reset process Rc). That is,
According to the simultaneous reset process Rc, the PDP 10
All discharge cells are initialized to "non-light emitting cells".
Because

[0007] Next, the driving device 100 controls the pixel data pulse groups DP ₁ -DP _{1 for} each row corresponding to the input video signal.
The DP _n sequentially, with to the column electrodes D _1-m, the scan pulse SP generated at the application timing of the pixel data pulse group DP, which sequentially applies to the row electrodes Y ₁ to Y _n (Pixel data writing process Wc). At this time, the scanning pulse S
A discharge (selective write discharge) is generated only in a discharge cell at an intersection of a “row” to which P is applied and a “column” to which a high-voltage pixel data pulse is applied, thereby forming wall charges. As a result, the discharge cells that have been initialized to the “non-light emitting cell” state in the simultaneous reset process Rc change to “light emitting cells”. On the other hand, the selective writing discharge does not occur in the discharge cells formed intersecting the "row" and "column" where the scan pulse SP is applied but the low-voltage pixel data pulse is applied, A state initialized in the simultaneous reset process Rc,
That is, the state of the “non-light emitting cell” is maintained.

[0008] Next, the drive apparatus 100, as shown in FIG. 3, and applies to repeated sustain pulse IP _X row electrode X ₁ to X _n, and according sustain pulse IP _X by shifting the timing maintained Repeat the pulse IP _Y for the row electrode Y ₁
Applied to to Y _n (light emission sustain process Ic). Incidentally, one sub-number field in pulses IP _X and IP _Y maintained in is applied, as is shown in FIG. 2, are set in accordance with the weighting of each subfield. Here, discharge cells in which wall charges are present, that is, only the "light emitting cell", to sustain every time these sustain pulses IP _X and IP _Y are applied. That is, in the pixel data writing process Wc,
Only the discharge cells set as "light-emitting cells" repeat the light emission accompanying the sustain discharge by the number of times corresponding to the weight of the subfield, as shown in FIG. 2, and maintain the light-emitting state.

The drive device 100 performs the above operation for each subfield. At this time, the halftone luminance corresponding to the video signal is expressed by the total number (in one field) of the sustain discharges generated in each subfield. Note that the number of luminance gradations that can be expressed by the subfield method increases as the number of divided subfields increases. However, since the display period of one field is predetermined, in order to increase the number of subfields, it is necessary to shorten the pulse widths of various drive pulses as shown in FIG.

However, when the pulse width of the driving pulse is shortened, erroneous discharge occurs, resulting in a problem that good display quality cannot be obtained.

[0011]

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and it is possible to display a good image even if the pulse width of a driving pulse applied to a plasma display panel is shortened. An object of the present invention is to provide a driving method of a plasma display panel that can be performed.

[0012]

A driving method of a plasma display panel according to the present invention is characterized in that a row electrode corresponding to each of a plurality of display lines and a column electrode arranged so as to intersect the row electrode have one point. A method of driving a plasma display panel forming discharge cells corresponding to pixels, wherein a unit display period of an input video signal is divided into a plurality of divided display periods, and in each of the divided display periods, each of the display lines is A first discharge generating a selective discharge to be set to one of a non-light-emitting cell and a light-emitting cell in accordance with pixel data corresponding to the input video signal in each of the discharge cells belonging to some of the display line groups. A pixel data writing process;
A first light emission sustaining step of causing a predetermined number of sustain discharges to cause only the light emitting cells belonging to the partial display line group to emit light, and the discharge cells belonging to other display line groups in each of the display lines A second pixel data writing step for generating a selective discharge to be set to either the non-light emitting cell or the light emitting cell according to the pixel data, and a sustain discharge to cause only the light emitting cell to emit light. A second light emission sustaining process is sequentially performed in which the predetermined number of times is subtracted from the number of times corresponding to the weight of each of the divided display periods.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 4 is a diagram showing a schematic configuration of a plasma display device for driving a plasma display panel based on a driving method according to the present invention. As shown in FIG. 4, such a plasma display device includes:
PDP 10 as a plasma display panel and A
And a drive unit including a / D converter 1, a drive control circuit 2, a memory 4, an address driver 6, a first sustain driver 7 and a second sustain driver 8.

The PDP 10 has m address electrodes.
Column electrode D₁~ D_mAnd crossed with each of these column electrodes
2n row electrodes X₁~ X_2nAnd row electrode Y₁
~ Y _2nIt has. At this time, the row electrodes X and Y
One pair corresponds to one display line in PDP10
Row electrodes are formed. Column electrode D, row electrodes X and Y
Is covered with a dielectric layer for the discharge space,
A discharge cell corresponding to one pixel is formed at the intersection between the pole pair and the column electrode.
The structure is formed.

An A / D converter 1 samples an input analog input video signal in response to a clock signal supplied from a drive control circuit 2 and converts the sampled analog input video signal into, for example, a 4-bit pixel corresponding to each pixel. The data is converted into data D and supplied to the memory 4. The memory 4 sequentially writes the pixel data D according to a write signal supplied from the drive control circuit 2.

When the writing operation for one screen (2n rows, m columns) in the PDP 10 is completed by this writing operation, the memory 4 is supplied with the pixel data D _{11-2 nm} for one screen from the drive control circuit 2. The readout is performed as follows in accordance with the readout signal. That is, the memory 4 first stores the pixel data writing processes Wc1 and Wc2 in the subfield SF4 described later.
In the above, only the fourth bit, which is the most significant bit of each of the pixel data D _{11-2 nm} , is grouped by one row and sequentially read out as drive pixel data bit groups DB _{1 to} DB _2n , and these are read out to the address driver 6. Supply. next,
The memory 4 stores the pixel data D in the pixel data writing processes Wc1 and Wc2 in a subfield SF3 described later.
_{Those obtained by grouping} only the third bit of each _{11-2 nm} for one row are sequentially read as drive pixel data bit groups DB _{1 to} DB _2n and supplied to the address driver 6.
Next, in a pixel data writing process Wc1 and Wc2 in a subfield SF2 described later, the memory 4 groups driving pixel data D _{11-2 nm in} which only the second bit is grouped by one row. Bit group DB _{1 to} DB _2n
And sequentially supplies them to the address driver 6. Next, the memory 4 stores a subfield SF to be described later.
In the pixel data writing step Wc1 and Wc2 at 1, the pixel data D _11-2Nm each of the least significant bit in a first bit only one line at a time grouped drive pixel data bit group DB ₁ to DB those _2n are sequentially read and supplied to the address driver 6.

The drive control circuit 2 generates a clock signal for the A / D converter 1 and a write / read signal for the memory 4 according to the horizontal and vertical synchronizing signals in the input video signal. Further, the drive control circuit 2 operates according to the light emission drive format as shown in FIG.
Various timing signals for driving the DP 10 are supplied to the address driver 6, the first sustain driver 7, and the second sustain driver 8, respectively.

In the light emission drive format shown in FIG. 5, one field period of the input video signal is divided into four subfields SF1 to SF4, and in each subfield, the simultaneous reset process Rc and the first pixel data writing are performed. The incorporation step Wc1, the first light emission sustaining step Ic1, the second pixel data writing step Wc2, and the second light emission sustaining step Ic2 are sequentially executed. Further, the priming process Pc is executed immediately before the second pixel data writing process Wc2.

FIG. 6 shows that the address driver 6, the first sustain driver 7, and the second sustain driver 8 apply to the row electrodes and the column electrodes of the PDP 10 within one subfield according to the light emission drive format shown in FIG. FIG. 4 is a diagram illustrating application timings of various drive pulses. First, in the simultaneous reset process Rc shown in FIG.
The first sustain driver 7 applies a positive reset pulse RP _x to the row electrodes X ₁ to X _2n, simultaneously with the application of the reset pulse RP _x, the second sustain driver 8,
Applying a negative reset pulse RP _Y to the row electrodes Y ₁ to Y _2n. Depending on the application of these reset pulses RP _x and RP _Y, all the discharge cells in the PDP10 is reset discharge, uniform predetermined amount of wall charge in each discharge cell is formed. Immediately after that, the first sustain driver 7
Simultaneously applies an erasure pulse EP as but such shown in the PDP10 in the row electrode X ₁ to X _2n. As a result, an erasure discharge is generated in all the discharge cells, and the wall charges disappear.

That is, by the simultaneous reset process Rc, all the discharge cells in the PDP 10 are initialized to "non-light emitting cells". When the simultaneous reset process Rc is completed, the first pixel data write process Wc1 is performed next.
Execute In the first pixel data writing process Wc1, the address driver 6 sequentially read drive pixel data bit group DB ₁ to DB _n each generates a pixel data pulse group DP ₁ to DP _n corresponding from the memory 4 These are sequentially applied to the column electrodes D _1-m as shown in FIG. At this time, the drive pixel data bit groups DB _{1 to} DB _n include, for example, only the most significant bit of the pixel data D in the subfield SF4, and include only the least significant bit of the pixel data D in the subfield SF1. It consists of
That is, the address driver 6 outputs a high-voltage pixel data pulse when the data bit based on the pixel data D is, for example, the logical level “1”, and a low voltage (0 volt) when the data bit is the logical level “0”. Occurs, and this is called PDP10
Are grouped by the display lines corresponding to the first row to the n-th row, and the pixel data pulse group DP ₁
ＤＰDP _n are sequentially applied to the column electrodes D _{1 -m} . At each application timing of these pixel data pulse groups DP _{1 to} DP _n , the second sustain driver 8 generates a negative scan pulse SP, and supplies this to the row electrodes Y _{1 to} Y _n as shown in FIG. Are sequentially applied. At this time, only the discharge cells at the intersection of the “row” to which the scan pulse SP is applied and the “column” to which the high-voltage pixel data pulse is applied are discharged.
(Selective write discharge) occurs, and wall charges are formed in the discharge cells. That is, the discharge cell changes to a “light emitting cell” state. On the other hand, in the discharge cells to which the scan pulse SP is applied but the low-voltage pixel data pulse is applied, the above-described selective write discharge is not generated, and thus the state of the “non-light emitting cell” is maintained.

That is, in the first pixel data writing step Wc1, of the display lines consisting of the first to second n rows in the PDP 10, the first to nth display line groups (hereinafter referred to as display line group A). Pixel data is written to the discharge cells belonging to the same type. The first
When the pixel data writing process Wc1 ends, next, a first light emission sustaining process Ic1 is performed.

[0022] In the first light emission sustain process Ic1, first, the second sustain driver 8, the sustain pulse IP _Y1 is but such positive polarity shown in FIG. 6 simultaneously applied to the PDP10 in the row electrodes Y ₁ to Y _n. Furthermore, immediately after application of the sustain pulse IP _Y1, the first sustain driver 7, the row electrodes X ₁ of the sustain pulse IP _X1 is but such positive polarity shown in FIG. 6 PDP 10
To X _2n . The application of these sustain pulses, the discharge cells in which the wall charges are formed in the first pixel data writing process Wc1, i.e., only "light-emitting cell" to sustain discharge every time the sustain pulse IP _Y1 and IP _X1 are applied Thus, two times of pulse emission are performed.

That is, in the first light emission sustaining step Ic1, P
Discharge cells belonging to the first to n-th display line groups A among the first to second n-th display lines in DP10
(In the "light emitting cell" state), the first two sustain discharges are generated. On the other hand, in the priming process Pc performed simultaneously with the first light emission sustaining process Ic1, the second sustain driver 8 applies the positive priming pulse PP as shown in FIG. 6 to the row electrodes Y _{n + 1 to} Y Y of the PDP 10. _Apply simultaneously to _2n . A priming discharge is generated in response to the application of the priming pulse PP,
Charged particles in the discharge space of each discharge cell is formed belonging to the row electrode Y _{n + 1} ~Y _2n.

That is, in the priming process Pc, among the display lines of the first row to the 2nth row in the PDP 10, the display line groups of the (n + 1) th row to the 2nth row (hereinafter, referred to as “P1”).
A priming discharge for forming charged particles is generated in the discharge cells belonging to the display line group B). When the first light emission sustaining process Ic1 and the priming process Pc are completed, next, a second pixel data writing process Wc2 is performed.

In the second pixel data writing step Wc2, the address
The driver 6 reads the drive sequentially read from the memory 4.
Video elementary data bit group DB_{n + 1}~ DB_2nCorresponding to each
Pixel data pulse group DP_{n + 1}~ DP_2nCauses these
Are sequentially applied to the column electrodes D as shown in FIG._1-mApplied to
go. At this time, the driving pixel data bit group DB_{n + 1}~ DB
_2nThis means that, for example, in the subfield SF4, the pixel data
Data D only consists of the most significant bit
SF1 consists of only the least significant bit of the pixel data D
Things. That is, the address driver 6
The data bit by the raw data D is, for example, a logical level "1".
Is high voltage, and if the logic level is "0",
Generates a low voltage (0 volt) pixel data pulse, which is
Corresponds to each of the nth to 2nth rows of the display lines of the PDP 10
The data grouped by
Luth group DP_{n + 1}~ DP_2nAs the column electrode D_1-mApplied to
I will go. At this time, the scanning pulse SP is applied.
"Row" and "column" to which high-voltage pixel data pulse was applied
Discharge (selective write discharge) occurs only in the discharge cell at the intersection with
As a result, wall charges are formed in the discharge cells. That is,
This discharge cell transitions to a “light emitting cell” state. on the other hand,
Although the scanning pulse SP is applied, the low-voltage pixel data
In the discharge cell to which the data pulse is applied,
No discharge occurs, so "non-light emitting cell" status is maintained
Is done.

That is, in the second pixel data writing step Wc2, the discharge cells belonging to the display line group B of the (n + 1) th row to the 2nth row among the display lines consisting of the first row to the 2nth row in the PDP 10 are The writing of the pixel data is performed. When the second pixel data writing process Wc2 ends, a second light emission sustaining process Ic2 is next performed. In the second light emission sustain process Ic2, the first sustain driver 7 and second sustain driver 8 each of which is shown in FIG. 6 with respect to the row electrodes X ₁ to X _2n and Y ₁ to Y _2n as a positive polarity alternately repeatedly applying a sustain pulse IP _X2 and IP _Y2 of.
The number of sustain pulses applied in the second light emission sustain step Ic2 in each subfield is a number preset in accordance with the weight of each subfield SF, for example, SF4: 8 SF3: 4 SF2: 2 SF1: 1 is the number obtained by subtracting the number of sustain discharges generated in the first light emission sustain step Ic1 from the number set based on the number ratio SF1: 1.

By applying the sustain pulse, the first
Pixel data writing process Wc1 and second pixel data writing process W
Only the discharge cell in which the wall charges are formed at c2, that is, the "light-emitting cell" sustain discharges each time the sustain pulses _IPX2 and _IPY2 are applied, and repeat the intermittent light emission as many times as described above. As described above, in the present invention, P
Of the display lines of the first row to the second n-th row in DP10,
When the pixel data writing to the discharge cells belonging to the display line group A of the first row to the n-th row is completed, the sustain discharge is generated by the first predetermined number of times for the discharge cells belonging to the display line group A. I have to. This allows
The charged particles formed by the selective writing discharge in the first pixel data writing step Wc1 but reduced with the passage of time are re-formed by the sustaining discharge.

Therefore, at the stage immediately before the second light emission sustaining step Ic2 shown in FIG. 6, the charged particles remain in the discharge cells belonging to the display line group A as described above. It is shorter sustain pulses IP _X2 and IP _Y2 each pulse width is applied at ic2, so sustain discharge is correctly occur. On the other hand, for each discharge cell belonging to the remaining display line group B of the PDP 10,
Before writing pixel data, a priming pulse PP is applied to generate a priming discharge. As a result, the charged particles formed by the reset discharge in the simultaneous reset process Rc but reduced with time are re-formed.

Therefore, the charged particles remain in the discharge cells belonging to the display line group B immediately before the second pixel data writing step Wc2 shown in FIG. Even when the pulse width of the scanning pulse SP applied in the two-pixel data writing process Wc2 is short, the selective writing discharge is correctly generated. Therefore, according to the driving according to the present invention, even if the pulse width of the driving pulse (scanning pulse SP, sustaining pulse IP) to be applied to the PDP is shortened in order to increase the number of divided subfields, various discharges (selection Discharge and sustain discharge) can be properly generated, so that good image display can be obtained.

In the above embodiment, as a method of writing pixel data, a so-called selection method of writing pixel data by selectively forming wall charges in each discharge cell according to the pixel data. The case where the write address method is adopted has been described. However, according to the present invention, as such a method of writing pixel data, a wall charge is formed in all discharge cells in advance, and the wall charge is selectively erased according to the pixel data to write the pixel data. Do
The same applies to the case where a so-called selective erase address method is adopted.

In the above embodiment, as shown in FIG. 5, the simultaneous reset process Rc is performed for each subfield.
Although the operation has been described by taking as an example the drive based on the light emission drive format that implements the above, the present invention can be applied to other light emission drive formats. FIG.
Is a diagram showing another configuration of a plasma display device made in view of the above points.

In FIG. 7, a PDP 10 as a plasma display panel has m column electrodes D _{1 to} D _m as address electrodes, and 2n row electrodes X each arranged so as to cross each of these column electrodes. _{1 to} X _2n and row electrodes Y ₁ to
Y _2n is provided. At this time, a row electrode corresponding to one display line of the PDP 10 is formed by a pair of the row electrode X and the row electrode Y. The column electrodes D and the row electrodes X and Y are covered with a dielectric layer with respect to the discharge space, and have a structure in which a discharge cell corresponding to one pixel is formed at an intersection between each row electrode pair and a column electrode. I have.

The A / D converter 1 samples the input analog input video signal in accordance with the clock signal supplied from the drive control circuit 20 and converts the sampled analog video signal into, for example, a 4-bit pixel corresponding to each pixel. The data is converted to data D and supplied to the image processing circuit 30. The image processing circuit 30 performs luminance correction, inverse γ correction, and
The image processing pixel data HD obtained by performing multi-gradation processing such as error diffusion processing and dither processing is supplied to the memory 4. At this time, in the error diffusion process, the upper bits of the pixel data D are regarded as display data, and the remaining lower bits are regarded as error data, and the error data obtained from the pixel data D of each of the surrounding pixels is weighted and added, respectively. What is reflected on the display data is new pixel data. With this operation, the luminance component corresponding to the lower bit in the original pixel is pseudo-expressed by the peripheral pixels.
The dithering process is to express one intermediate display level by a plurality of pixel data (pixel data subjected to diffusion processing) corresponding to pixels adjacent to each other on a screen. At this time, in the dither processing, for example,
Four pixels vertically adjacent to each other are set as one set, and four dither coefficients a to d each having a different coefficient value are assigned to each pixel data corresponding to each pixel of the set and added. According to such dither processing, combinations of four different intermediate display levels occur in four pixels.

Further, the image processing circuit 30 classifies the pixel data subjected to the error diffusion and the dither processing into five gradations according to the luminance level, and FIG. 8 corresponding to this classification is shown in FIG. The image data is converted into 4-bit image processing pixel data HD having a bit pattern as described above and supplied to the memory 4. That is, the input video signal is converted by the A / D converter 1 and the image processing circuit 30 into five types of image processing pixel data HD having a bit pattern as shown in FIG.
Is converted to any one of

The memory 4 sequentially writes the image processing pixel data HD according to a write signal supplied from the drive control circuit 20. When the writing for one screen (2n rows, m columns) in the PDP 10 is completed by the writing operation, the memory 4 stores the image processing pixel data HD for the one screen.
_{11-2 nm} is read as follows in accordance with the read signal supplied from the drive control circuit 20.

That is, the memory 4 first stores the pixel data writing processes Wc1 and Wc2 in the subfield SF1 described later.
In sequentially reads those one row at a time grouping only the first bit is the least significant bit of the image processing pixel data HD _11-2Nm each as drive pixel data bit group DB ₁ to DB _2n, which address driver 6 Next, the memory 4 stores a subfield SF2 described later.
In the pixel data writing process Wc1 and Wc2, only the second bit of each of the image processing pixel data HD _{11-2 nm is set} to 1
The grouped data for each row is sequentially read out as drive pixel data bit groups DB _{1 to} DB _2n and supplied to the address driver 6. Next, the memory 4 stores pixel data writing processes Wc1 and Wc2 in a subfield SF3 described later.
In the above, a group of only the third bit of each of the image processing pixel data HD _{11-2 nm for} each row is sequentially read as drive pixel data bit groups DB _{1 to} DB _2n .
This is supplied to the address driver 6. Next, memory 4
The image processing pixel data H in the pixel data writing processes Wc1 and Wc2 in the subfield SF4 described below.
D _11-2nm Only the 4th bit, which is the most significant bit, is 1
The grouped data for each row is sequentially read out as drive pixel data bit groups DB _{1 to} DB _2n and supplied to the address driver 6.

The drive control circuit 20 generates a clock signal for the A / D converter 1 and a write / read signal for the memory 4 in accordance with the horizontal and vertical synchronizing signals in the input video signal. Further, the drive control circuit 20
Supplies various timing signals for driving the PDP 10 to each of the address driver 6, the first sustain driver 7, and the second sustain driver 8 according to the light emission drive format as shown in FIG.

In the light emission drive format shown in FIG. 9, one field period of the input video signal is divided into four subfields SF1 to SF4, and the first subfield S1
In F1, the simultaneous resetting process Rc, the first pixel data writing process Wc1, the first light emission sustaining process Ic1, the second pixel data writing process Wc2, and the second light emitting sustaining process Ic2 are sequentially performed. Further, in the subfield SF1, the second field
The priming process Pc immediately before the pixel data writing process Wc2
Execute In each of the subfields SF2 to SF4, the first pixel data writing process Wc1 and the first light emission sustaining process I
c1, a second pixel data writing process Wc2, and a second light emission sustaining process Ic2 are sequentially performed. Further, these subfields S
In each of F2 to SF4, the second pixel data writing process W
Immediately before c2, the third light emission sustaining step Ic3 is executed.

FIG. 10 shows that each of the address driver 6, the first sustain driver 7, and the second sustain driver 8 includes a PD according to the light emission drive format shown in FIG.
It is a figure which shows the application timing of various drive pulses applied to the row electrode and column electrode of P10. Note that FIG. 10 shows only the application timing in the first subfield SF1 and the subsequent subfield SF2.

In FIG. 10, the first subfield S
In the simultaneous resetting step Rc, which is implemented only in the F1, the first sustain driver 7 applies a negative reset pulse RP _x to the row electrodes X ₁ to X _2n, simultaneously with the application of the reset pulse RP _x, the second Sustain driver 8
There applies a positive reset pulse RP _Y to the row electrodes Y ₁ to Y _2n. Depending on the application of these reset pulses RP _x and RP _Y, all the discharge cells in the PDP10 is reset discharge, uniform predetermined amount of wall charge in each discharge cell is formed.

That is, by the simultaneous reset process Rc, all the discharge cells in the PDP 10 are initialized to the "light emitting cell" state. When the simultaneous reset process Rc is completed, the first pixel data writing process Wc1 is next performed.
Execute In the first pixel data writing process Wc1, the address driver 6 sequentially read drive pixel data bit group DB ₁ to DB _n each generates a pixel data pulse group DP ₁ to DP _n corresponding from the memory 4 These are shown in FIG.
As shown in FIG. 7, the voltage is sequentially applied to the column electrodes D _{1 -m} .
At this time, the drive pixel data bit groups DB _{1 to} DB _n include, for example, only the first bit of the image processing pixel data HD as shown in FIG.
The subfield SF4 consists of only the fourth bit of the image processing pixel data HD as shown in FIG.
That is, the address driver 6 outputs a high voltage when the data bit of the image processing pixel data HD is, for example, the logical level “1”, and a low voltage (0 volt) when the data bit is the logical level “0”. Generate a pulse,
Sequentially a grouping with each other corresponds to the first row to the n-th row of each display line of DP10 as the pixel data pulse groups DP ₁ to DP _n, is the to the column electrodes D _1-m . The second sustain driver 8 generates a negative-polarity scan pulse SP at each of the application timings of the pixel data pulse groups DP _{1 to} DP _n , and supplies this to the row electrodes Y _{1 to} Y _n as shown in FIG. Are sequentially applied.
At this time, a discharge (selective erase discharge) is generated only in the discharge cell at the intersection of the “row” to which the scanning pulse SP is applied and the “column” to which the high-voltage pixel data pulse is applied, and the simultaneous reset is performed. The wall charges formed in the process Rc disappear. That is,
This discharge cell changes to a “non-light emitting cell” state. On the other hand, the selective erasing discharge as described above is not generated in the discharge cells to which the scan pulse SP is applied but the low-voltage pixel data pulse is applied, so that the state of the “light emitting cell” is maintained.

That is, according to the first pixel data writing process Wc1, the display line group consisting of the first to n-th rows among the display lines consisting of the first to second n-th rows in the PDP 10
Pixel data is written to the discharge cells belonging to the display line group A (hereinafter, referred to as display line group A) by applying the selective erase address method. The first pixel data writing process W
When c1 ends, next, the first light emission sustaining step Ic1 is performed.

In the first light emission sustaining step Ic1, first, the first sustain driver 7 simultaneously applies a sustain pulse IP _X1 having a positive polarity to the row electrodes X _{1 to} X _2n of the PDP 10 as shown in FIG. Furthermore, immediately after application of the sustain pulse IP _X1, the second sustain driver 8, the sustain pulse IP _Y1 is but such positive polarity shown in FIG. 10 simultaneously applied to the PDP10 in the row electrodes Y ₁ to Y _n. Due to the application of these sustain pulses, only the discharge cells in which the wall charges remain in the first pixel data writing step Wc1, that is, the "light emitting cells" are applied each time the sustain pulses IP _Y1 and IP _X1 are applied. And two pulses of light emission are performed.

That is, in the first light emission sustaining process Ic1, P
It belongs to the display line group A consisting of the first row to the n-th row among the display rows consisting of the first row to the second n-th row in the DP 10.
The first two sustain discharges are generated in the light-emitting cell. On the other hand, in the priming step Pc performed simultaneously with the first light-emission sustain step Ic1, the second sustain driver 8 shown in FIG. The priming pulse PP of the positive polarity is applied to the row electrodes Y _{n + 1 to} Y of the PDP 10 as shown in FIG.
_Apply simultaneously to _2n . A priming discharge is generated in response to the application of the priming pulse PP, and the row electrode Y _{n + 1}
Charged particles are formed in the discharge spaces of the discharge cells belonging to .about.Y _2n .

That is, in the priming process Pc, the display line group consisting of the (n + 1) th row to the (2n) th row among the display lines of the first row to the (2n) th row in the PDP 10
A priming discharge for forming charged particles is generated in the discharge cells belonging to the display line group B (hereinafter, referred to as display line group B). When the first light emission sustaining process Ic1 and the priming process Pc are completed, next, a second pixel data writing process Wc2 is performed.

In the second pixel data writing step Wc2, the address driver 6 operates the pixel data pulse group DP _{n +} corresponding to each of the driving pixel data bit groups DB _{n + 1 to} DB _2n sequentially read from the memory 4. _{1 to} DP _2n are generated and sequentially applied to the column electrodes D _1-m as shown in FIG. At this time, the driving pixel data bit groups DB _{n + 1 to} D
B _2n is, for example, only the first bit of the image processing pixel data HD as shown in FIG. 8 in the subfield SF1, and the image processing pixel data HD as shown in FIG. 8 in the subfield SF4. Only the fourth bit. That is, the address driver 6 outputs a high voltage when the data bit of the image processing pixel data HD is, for example, the logical level “1”, and a low voltage (0 volt) when the data bit is the logical level “0”. Pulses are generated, grouped by those corresponding to the (n + 1) -th to (2n) -th rows of the display lines of the PDP 10, and sequentially grouped as the pixel data pulse groups DP _{n + 1 to} DP _2n .
The voltage is applied to the column electrode D _1-m . At each application timing of these pixel data pulse groups DP _{n + 1 to} DP _2n , the second sustain driver 8 generates a scan pulse SP of a negative polarity, and supplies this to the row electrode Y as shown in FIG.
_{n + 1} is sequentially applied to the ~Y _2n. At this time, a discharge (selective erase discharge) is generated only in the discharge cell at the intersection of the “row” to which the scan pulse SP is applied and the “column” to which the high-voltage pixel data pulse is applied, and the discharge cell The wall charges remaining inside disappear. That is, this discharge cell changes to a “non-light emitting cell” state. On the other hand, the scanning pulse S
In the discharge cells to which the P is applied but the low-voltage pixel data pulse is applied, the selective erasing discharge as described above is not generated, so that the state of the “light emitting cell” is maintained.

That is, in the second pixel data writing process Wc2, the discharge cells belonging to the display line group B consisting of the (n + 1) th row to the 2nth row among the display lines consisting of the first row to the 2nth row in the PDP 10 are Thus, writing of pixel data to which the selective erase address method is applied is performed. When the second pixel data writing process Wc2 ends, the second pixel data
The light emission sustaining step Ic2 is performed.

[0048] In the second light emission sustain process Ic2, as the first sustain driver 7 and second sustain driver 8 each of which is shown a sustain pulse IP _X2 and IP _Y2 positive polarity in FIG. 10, the row electrodes X ₁ to X _2n and Y _{1 to} Y _2n are alternately and repeatedly applied. The number of sustain pulses applied in the second light emission sustain step Ic2 in each subfield is a number preset in accordance with the weight of each subfield SF, for example, SF4: 8 SF3: 4 SF2: 2 SF1: 1 is the number obtained by subtracting the number of sustain discharges generated in the first light emission sustain step Ic1 from the number set based on the number ratio SF1: 1.

By applying the sustain pulse, the first
Pixel data writing process Wc1 and second pixel data writing process W
The discharge cell in which wall charges are formed in c2, ie, "
Only the light-emitting cell "is sustain-discharged every time the sustain pulses _IPX2 and _IPY2 are applied, and repeats intermittent light emission for the number of times as described above. When the second light-emission sustain step Ic2 ends, the subfield The first pixel data writing process Wc1 of SF2 is performed.

At this time, in the subfield SF2, as in the case of the subfield SF1, the first pixel data writing step Wc1, the first light emission sustaining step Ic1, the second pixel data writing step Wc2, and the second light emitting sustaining step are performed. Step Ic2 is performed sequentially. Here, in the first subfield SF1, the priming process Pc was performed immediately before the second pixel data writing process Wc2, but in the subfield SF2,
A third light emission sustaining step Ic3 is performed instead of the priming step Pc.

[0051] In the third emission sustaining process Ic3, the second sustain driver 8, the sustain pulse IP _Y3 in sustain pulse IP _Y1 same timing of applying the first light emission sustain process Ic1 PDP 10 row electrodes Y _{n + 1} To Y _2n . At this time, the application of the sustain pulse IP _X1 and the sustain pulse IP _Y3 causes the second pulse in the subfield SF1 to be applied.
A discharge cell in which wall charges remain at the end of the pixel data writing step Wc2, that is, a “light emitting cell”
Only the sustain pulses IP _X1 and IP _Y3 are applied for sustain discharge, and two pulses of light emission are performed.

That is, the third in the subfield SF2
In the light emission sustaining process Ic3, the “light emitting cells” belonging to the display line group B consisting of the (n + 1) th row to the 2nth row among the display lines consisting of the first row to the 2nth row in the PDP 10 are preset as described above. That is, the last two sustain discharges of the number of times of light emission in the subfield SF1 are generated. That is, in the discharge cells belonging to the display line group B, the number of sustain discharges generated in the second light emission sustaining process Ic2 in the subfield SF1,
The total number of sustain discharges generated in the second third light emission sustaining process Ic3 is the number in the subfield SF1 set as described above.

The driving in the subfield SF2 is as follows.
The same applies to subfields SF3 and SF4. As a result, the PDP 10 is driven to emit light in accordance with the image processing pixel data HD, that is, to emit light by one of the five emission drive patterns as shown in FIG. That is, as shown in FIG. 8, first, the first pixel data writing process W in one of the subfields SF1 to SF4 is performed.
Only in c1 and the second pixel data writing process Wc2, a selective erase discharge is generated (shown by a black circle). This allows
The wall charges formed in all the discharge cells of the PDP 10 by the simultaneous reset process Rc remain until the above-described selective erasing discharge is performed, and the sub-field S existing during that period remains.
In each of the light emission sustaining processes Ic1 and Ic2 (or Ic3) in each of F, light emission accompanying the sustain discharge occurs (shown by white circles). That is, each discharge cell becomes a “light-emitting cell” until the above-described selective erasure discharge is performed within one field period,
Light emission is repeated as many times as described above in the light emission sustaining process in each of the subfields existing during that time.

At this time, as shown in FIG. 8, the number of transitions of each discharge cell from “light emitting cell” to “non-light emitting cell” is as follows.
The number of times is always set to one or less within one field period. That is, the discharge cells once set as “non-light-emitting cells” are again changed to “light-emitting cells” within one field period.
That is, the light emission drive pattern for returning to the normal state is prohibited. Therefore, according to such a light emission drive pattern, there is no light emission pattern in which the light emitting state and the non-light emitting state are inverted from each other in one field period, so that a false contour can be suppressed.

Here, according to the light emission drive pattern as shown in FIG. 8, it is possible to express the halftone in five stages in which the light emission luminance ratio is {0, 1, 3, 7, 15}. However, the pixel data D supplied from the A / D converter 1 expresses 4 bits, that is, 16 levels of halftones.

Therefore, the image processing circuit 30 applies error diffusion and dither processing to the pixel data D so as to perform pseudo 16-step halftone display even by the 5-step gradation driving. is there. As mentioned above,
Also in the embodiment shown in FIGS.
When the pixel data writing to the discharge cells belonging to the first to n-th display line groups A out of the ten first to second n-th display lines is completed, a predetermined The first sustain discharge is generated by the number of times. As a result, the charged particles formed by the selective writing discharge in the first pixel data writing step Wc1 but reduced with the passage of time are re-formed by the sustaining discharge.

Therefore, the charged particles remain in the discharge cells belonging to the display line group A immediately before the second light emission sustaining step Ic2 shown in FIG. Even if the pulse width of each of the sustain pulses IP _X2 and IP _Y2 applied in the process Ic2 is short, the sustain discharge can be correctly generated. On the other hand, PDP1
A priming pulse PP or a sustaining pulse _IPY3 is applied to each of the discharge cells belonging to the remaining display line group B of 0 before writing of pixel data to generate a priming discharge or a sustaining discharge. I have. As a result, the charged particles formed by the reset discharge in the simultaneous reset process Rc but reduced with time are re-formed.

Therefore, at the stage immediately before the second pixel data writing step Wc2 as shown in FIG. 10, the above charged particles remain in the discharge cells belonging to the display line group B. This second pixel data writing process Wc2
In this case, even when the pulse width of the scan pulse SP applied is short, the selective erase discharge is correctly generated.

[0059]

As described in detail above, in the present invention,
When the writing of the pixel data to the discharge cells belonging to a part of the display line group among the display lines of the PDP is completed,
The first sustain discharge is generated in the discharge cells belonging to the partial display line group. Thereafter, pixel data is written to the discharge cells belonging to the remaining display line groups, and when this is completed, the remaining sustain discharge is generated for all the discharge cells.

Therefore, according to such driving, charged particles always remain in each discharge cell.
Even if the pulse width of the driving pulse to be applied to the PDP is shortened, erroneous discharge hardly occurs, and a good image display can be obtained.

[Brief description of the drawings]

FIG. 1 is a diagram showing a schematic configuration of a plasma display device.

FIG. 2 is a diagram illustrating an example of a light emission drive format.

FIG. 3 is a diagram showing application timings of various drive pulses applied to a column electrode and a row electrode of the PDP 10 within one subfield.

FIG. 4 is a diagram showing a schematic configuration of a plasma display device for driving a plasma display panel according to a driving method according to the present invention.

FIG. 5 is a diagram showing an example of a light emission drive format based on a drive method according to the present invention.

6 is a diagram showing application timings of various drive pulses applied to column electrodes and row electrodes of the PDP 10 according to the light emission drive format shown in FIG.

FIG. 7 is a diagram showing a schematic configuration of a plasma display device for driving a plasma display panel according to a driving method according to the present invention.

FIG. 8 is a diagram showing a correspondence between image processing pixel data HD and a light emission drive pattern.

FIG. 9 is a diagram showing another example of a light emission drive format based on a drive method according to the present invention.

10 is a diagram showing application timings of various drive pulses applied to column electrodes and row electrodes of the PDP 10 according to the light emission drive format shown in FIG. FIG. 5 is a diagram showing a state transition in a discharge cell.

[Explanation of Signs of Main Parts]

 2,20 drive control circuit 6 address driver 7 first sustain driver 8 second sustain driver 10 PDP 30 image processing circuit

Claims (5)

[Claims] 1. A plasma display panel having a discharge cell corresponding to one pixel at each intersection of a row electrode corresponding to each of a plurality of display lines and a column electrode arranged to cross the row electrode. A driving method, wherein a unit display period of an input video signal is divided into a plurality of divided display periods, and in each of the divided display periods, the discharge cells belonging to a part of the display lines among the display lines are arranged. A first pixel data writing process for generating a selective discharge to be set in one of the non-light emitting cells and the light emitting cells according to the pixel data corresponding to the input video signal; A first light emission sustaining step of causing a predetermined number of sustain discharges to cause only the light emitting cells belonging to the light emitting cells to emit light, and each of the discharge cells belonging to a display line group in another part of the display lines A second pixel data writing step for generating a selective discharge to be set in one of the non-light emitting cell and the light emitting cell in accordance with the pixel data; and a sustained discharge for causing only the light emitting cell to emit light. A second light emission sustaining step that occurs by the number of times obtained by subtracting the predetermined number from the number corresponding to the weighting of each period;
Are sequentially performed, the method for driving a plasma display panel. 2. A reset process for generating a reset discharge for initializing all of the discharge cells to one of the light emitting cells and the non-light emitting cells prior to the first pixel data writing process. The method of driving a plasma display panel according to claim 1, wherein: 3. A priming discharge is generated in each of the discharge cells belonging to the display line group of the other part immediately before the second pixel data writing process in the leading divided display period in the unit display period. 2. The method according to claim 1, wherein a priming step is performed. 4. Only in the first divided display period in the unit display period and prior to the first pixel data writing step, all the discharge cells are switched to one of the light emitting cells or the non-light emitting cells. Performing a reset process for causing a reset discharge to be initially set in a state, wherein the first pixel data write process and the second pixel data write process in any one of the divided display periods in the unit display period 2. The method according to claim 1, wherein the selective discharge for changing the initial setting state of the discharge cells is caused only by the discharge. 5. In each of the divided display periods other than the first divided display period in the unit display period, the light emission belonging to the display line group of the other portion immediately before the second pixel data writing process. 5. The method of driving a plasma display panel according to claim 1, wherein a third light emission sustaining step of generating the sustained discharge for causing only the cells to emit light by the predetermined number of times is performed.