JP2000236066A - Semiconductor integrated circuit and its wiring method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wiring method which can minimize increase in area and degradation of wiring property caused by shield wiring carried out for crosstalk countermeasures. SOLUTION: A VDD line 12 is subjected to wiring in the vertical directions in a Y direction in a cell line and a GND line 14 is subjected to wiring in an X direction for supplying power source to a cell 10. For a region where a CLK line is to be subjected to wiring in the X direction, a VDD line and a GND line are subjected to wiring so that the VDD line 12 or the GND line 14 faces opposite to each other. A CLK line wiring region 16 is formed between the VDD lines 14, and a CLK line wiring region 18 is formed between the VDD lines 12. CLK lines 20a, 20e are subjected to wiring in the CLK line wiring regions 16, 18.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit in which the influence of crosstalk from a clock signal is reduced, and a wiring method thereof.

[0002]

2. Description of the Related Art A semiconductor integrated circuit includes a signal line, a clock signal (CLK) line, a power supply (VDD) line, and a ground (GN).
D) The line is wired. In this case, crosstalk from the clock signal line to the signal line becomes a problem.

In order to address this problem, conventionally, FIG.
As shown in (1), by shielding both sides of the clock signal line 2 with dedicated shield lines 4, the influence of crosstalk is minimized. The shield line 4 is held at a constant potential, but is normally connected to a GND line or a VDD line and held at a GND potential or a VDD potential. In the figure, reference numeral 6 denotes a cell.

Alternatively, as shown in FIG. 6, a clock signal line 12 is built in the power supply line 8 or the basic gate cell 10, and the clock signal is routed and connected simultaneously with the layout of the power supply line or the arrangement of the basic gate cell. , The effect of crosstalk is suppressed. This technology is
It is disclosed in JP-A-9-8235.

[0005]

In the prior art shown in FIG.
Since dedicated shielded wiring is provided on both sides of the clock signal line as a countermeasure against crosstalk, the degree of wiring congestion increases, which greatly affects the wiring performance of other signal lines, that is, increases the chip area. .

In the prior art shown in FIG. 6, since a basic gate cell including a clock signal line is used, the clock signal line of the cell is automatically connected when the cell is arranged.
After the placement, the CTS (clock) is applied to the clock signal line.
A buffer cannot be inserted due to tree synthesis, and thus skew adjustment cannot be realized. Also, in order to implement multi-phase clock wiring using basic gate cells, it is necessary to arrange adjacent clock signal lines with the same clock signal line built in the cells and connect them. Adjustment is limited.

SUMMARY OF THE INVENTION An object of the present invention is to provide a wiring method capable of minimizing an increase in area and a deterioration in wiring performance due to shield wiring for measures against crosstalk.

It is still another object of the present invention to provide a semiconductor integrated circuit having a wiring realized by the above wiring method.

[0009]

According to a first aspect of the present invention, there is provided:
In a semiconductor integrated circuit in which a power supply line and a ground line for supplying power to cells are wired, a power supply line and / or a ground line are provided.
Alternatively, a semiconductor integrated circuit is characterized in that a ground line is used as a shield line for a clock signal line. The clock signal line is wired in a wiring region in which a power supply line, a ground line, or a power supply line and a ground line are arranged on both sides.

A second aspect of the present invention is a method for wiring a power supply line and a ground line for supplying power to a cell and a clock signal line for supplying a clock signal to a cell in a semiconductor integrated circuit. And a power supply line and / or a ground line to form a clock signal line wiring region, and wiring the clock signal line in the wiring region. The clock signal line wiring area is
It is formed between adjacently arranged power lines, between adjacently arranged ground lines, or between a power line and a ground line.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The embodiments of the present invention will be specifically described below based on examples.

[0012]

Embodiment 1 FIG. 1 shows an example of a wiring layout of a one-phase clock signal in a semiconductor integrated circuit. For convenience of description, the horizontal direction is referred to as an X direction in the drawings, and the vertical direction orthogonal to the horizontal direction is referred to as a Y direction.

In this semiconductor integrated circuit, a plurality of cells 1
0s are arranged in the X direction to form a cell row, and such cell rows are arranged in a plurality of rows in the Y direction.

To supply power to the cells, the Y
A VDD line 12 and a GND line 14 are arranged in the X direction above and below the direction. In this case, in the region where the CLK line is to be wired in the X direction, the VDD lines 12 or GND
The VDD line and the GND line are to be wired so that the lines 14 face each other. In the figure, the CLK line wiring region 16
Is sandwiched between the GND lines 14, and the CLK line wiring region 18 is
It is formed between D lines 12. GND line 14 and VDD line 12 sandwiching these CLK line wiring regions 16 and 18
Is originally for supplying power to the cell, but also functions as a shield line for the CLK line wired in the CLK line wiring area.

In the semiconductor integrated circuit of FIG. 1, cells 10a,
It is assumed that a clock signal is supplied to 10b, 10c, and 10d. CLK line 20a is wired in the X direction in CLK line wiring region 16, and Y line connected to CLK line 20a is connected to CLK line 20a.
Cells 10a, 10c by the CLK lines 20b, 20c in the
b.

Further, CL connected to the CLK line 20a
The K line 20d is wired in the Y direction and connected to the cell 10d. A shield line 22 is provided on both sides of the CLK line 20d.
In the example of FIG. 1, this shield line is connected to GN.
It is connected to the D line 14 and is held at the GND potential.

The CLK line wiring area 18 has a CL
A CLK line 20e connected to the K line 20d is wired in the X direction. The cell 10c is connected by a Y-direction CLK line 20f connected to the CLK line 20e.

In the above-mentioned wiring of the CLK line, X
All directional wirings are two-layer wirings, and all Y-directional wirings are one-layer wirings.

According to this embodiment, the CLK line wiring region 1
As for the X-direction CLK lines wired to 6, 18, the crosstalk from the CLK line to the signal line is reduced because the GND line and the VDD line on both sides function as shield lines.
Further, since the GND line shield line is provided on both sides of the CLK line 20d in the Y direction, crosstalk is reduced.

According to the wiring of the CLK line of this embodiment, the existing GND line and VDD line are used as the shield lines of the CLK lines 20a and 20e in the X direction, and it is not necessary to provide a dedicated shield line. The area can be reduced accordingly.

[0021]

Embodiment 2 FIG. 2 shows an example of a wiring layout of a two-phase clock signal in a semiconductor integrated circuit.

In this embodiment, CLK line wiring regions 30 and 32 sandwiched between GND lines 14 and CLK line wiring regions 34 sandwiched between VDD lines 16 are formed.

In the semiconductor integrated circuit of FIG. 2, cells 10a,
The first CLK signal (CLK1) is supplied to 10e and 10f, and the second CLK signal (CLK2) is supplied to the cells 10c and 10d.

In the CLK line wiring area 30, the CLK1 line 3
The 6a and CLK2 lines 38a are wired in the X direction. It is connected to the input of the cell 10a by a Y-direction CLK1 line 36b connected to the CLK1 line 36a. CLK2
It is connected to the input of cell 10b by a Y-direction CLK2 line 38b connected to line 38a.

From the output of cell 10a, the CLK1 line 36
c is pulled out in the Y direction, wired in the Y direction, and
CLK1 line 36 wired in the X direction in the line wiring area 34
d. Shield lines 40 are provided on both sides of the CLK1 line 36c. In the example of FIG. 2, this shield line is connected to the VDD line 12 and is held at the VDD potential.

The CLK1 line 36d connected to the CLK1 line 36c is wired in the CLK line wiring area 34 in the Y direction. CLK in Y direction connected to CLK1 line 36d
The cells are connected to the cells 10e and 10f by one line 36e and 36f.

From the output of the cell 10b whose input is connected to the CLK2 line 38b, the CLK2 line 38c is drawn out in the Y direction, wired in the Y direction, and
2 is connected to a CLK2 line 38d wired in the X direction. Shield lines 42 are wired on both sides of the CLK2 line 38c. In the example of FIG. 2, this shield line is GND.
Connected to line 14 and held at GND potential. CLK
CLK2 lines 38e, 3 in the Y direction connected to two lines 38d
8f connects the cells 10c and 10d.

In the above wiring of the CLK line, X
All directional wirings are two-layer wirings, and all Y-directional wirings are one-layer wirings.

According to the wiring of the CLK1 line and the CLK2 line of this embodiment, the CLK1 lines 36a and 36a in the X direction are provided.
As the shield lines for the CLK2 lines 38a and 38d in the d and X directions, existing GND lines and VDD lines are used, and there is no need to provide a dedicated shield line, so that the area can be reduced accordingly.

The cell 10a is connected to the CLK1 wiring by CL
Since the cells 10b are inserted into the K2 wiring, a buffer can be provided in these cells to easily perform the skew adjustment which is a problem in the related art.

[0031]

Third Embodiment FIG. 3 shows an example of a layout of a two-phase clock signal wiring in a semiconductor integrated circuit, as in the second embodiment.

In this embodiment, a CLK line wiring region 50 is formed between the VDD line 12 and the GND line 14 wired in the Y direction, and the CLK line is also wired in this wiring region 50. Things.

In this embodiment, the CLK line wiring region 5 sandwiched between the GND lines 14 wired in the X direction is further provided.
A CLK line wiring area 56 is formed between the VDD lines 16, which are arranged in the X direction.

In the semiconductor integrated circuit of FIG. 3, cells 10a,
CLK1 is applied to 10b, 10e, 10g, and cells 10c, 1
It is assumed that the second CLK signal (CLK2) is supplied to 0d and 10f.

In the CLK line wiring area 52, the CLK1 line 5
4a is wired in the X direction. The cells are connected to the cells 10a and 10b by CLK1 lines 54b and 54c in the Y direction connected to the CLK1 line 54a. Further, the CLK1 line 5
The CLK1 line 54d connected to the line 4a is wired in the Y direction, and the C1 line 54d is wired in the X direction in the CLK line wiring region 56.
Connected to LK1 line 54e. Also, the CLK1 line 54d
Is connected to the cell 10e on the way. CLK1 line 5
Shield lines 56 are wired on both sides of 4d. In the example of FIG. 2, this shield line is connected to the VDD line 12 and is held at the VDD potential.

C in the Y direction connected to the CLK1 line 54e
LK1 line 54f connects to cell 10g. Further, the CLK1 line 54g in the Y direction connected to the CLK1 line 54e is wired in the wiring region 50 in the Y direction.

In the CLK line wiring area 50, the CLK2 line 5
8a is wired in the Y direction, and the CLK2 line 58b connected to this CLK2 line 58a is wired in the CLK line wiring area 54 in the X direction.

C in the Y direction connected to the CLK2 line 58b
According to the LK2 lines 58c, 58d, and 58e, the cells 10c,
10d and 10f.

In the wiring of the above CLK line, X
All directional wirings are two-layer wirings, and all Y-directional wirings are one-layer wirings.

According to the wiring of the CLK1 line and the CLK2 line of this embodiment, the CLK1 lines 54a and 54a in the X direction are provided.
e, CLK1 line 54g in Y direction, CLK2 line 5 in X direction
8b, the existing GND line and VDD line are used as shield lines for the CLK2 line 58a in the Y direction, and there is no need to provide a dedicated shield line, so that the area can be reduced accordingly.

[0041]

Fourth Embodiment FIG. 4 shows an example of a wiring layout of a multi-phase (three-phase in this example) clock signal in a semiconductor integrated circuit.

In this embodiment, similarly to the third embodiment, a CLK line wiring region in the Y direction is formed between the VDD line 12 and the GND line 14 wired in the Y direction. Two phases of clock signal lines (CLK2 and CLK3) are wired in this Y-direction CLK line wiring region.
For separation, a shield line 81 is provided in the Y direction between the VDD line 12 and the GND line 14 in the Y direction. This shield line 80 is held at the VDD potential or the GND potential. One of the two divided lines of the CLK line is 70a,
Let the other be 70b.

In this embodiment, the CLK line wiring region 7 sandwiched between the GND lines 14 wired in the X direction is further provided.
2, CLK line wiring regions 76 and 78 are formed between the VDD lines 16 wired in the X direction.

In the semiconductor integrated circuit of FIG. 4, cells 10a,
CLK1 is applied to 10b, 10e, 10g, and cells 10c, 1
It is assumed that CLK2 is supplied to 0f and CLK3 is supplied to the cell 10d.

In the CLK line wiring area 72, the CLK1 line 8
0a is wired in the X direction. The cells are connected to the cells 10a and 10b by Y-direction CLK1 lines 80b and 80c connected to the CLK1 line 80a. Further, the CLK1 line 8
The CLK1 line 80d connected to the line 0a is wired in the Y direction, and the C1 line 80d wired in the X direction in the CLK line wiring region 78.
Connected to LK1 line 80e. Also, the CLK1 line 80d
Is connected to the cell 10e on the way. CLK1 line 8
Shield lines 82 are wired on both sides of 0d. In the example of FIG. 4, this shield line is connected to the VDD line 12 and held at the VDD potential.

C in the Y direction connected to CLK1 line 80e
LK1 line 80f connects to cell 10g. Further, the CLK1 line 80g in the Y direction connected to the CLK1 line 80e is wired in the wiring region 70b in the Y direction.

The CLK line wiring region 70b further includes C
The LK2 line 84a is wired in the Y direction, and the CLK2 line 8a
The CLK2 line 84b connected to 4a is wired in the CLK line wiring area 76 in the X direction.

C in the Y direction connected to CLK2 line 84b
LK2 line 84c connects to cell 10c. Further, the CLK2 line 84b in the Y direction is
Is connected to the cell 10f, and the other end is connected to the CLK2 line 84e wired in the X direction in the CLK line wiring region 72. Shield lines 86 are wired on both sides of the CLK2 line 84d,
In the example of FIG. 4, this shield line is connected to the GND line 14 and is kept at the GND potential.

In CLK line wiring region 70a, CLK3 line 88a is wired in the Y direction, and CLK3 line 88b connected to CLK3 line 88a is wired in CLK line wiring region 74 in the X direction.

C in the Y direction connected to CLK3 line 88b
The LK3 line 88c connects to the cell 10d. Further, the LK3 line 88d connected to the CLK3 line 88b is
It is wired in the Y direction and is connected to the CLK3 line 88e wired in the X direction in the CLK line wiring region 78. A shield line 82 and a shield line 9 are provided on both sides of the CLK3 line 88d.
0 is wired. The shield line 82 is maintained at the VDD potential as described above. The shield line 90 is similarly held at the VDD potential.

The CLK3 line 88e connected to the CLK3 line 88d is wired in the CLK line wiring area 78 in the Y direction.

The wiring of the three-phase CLK lines of this embodiment is shielded for each phase. In this case, the CLK lines 84a and 88a in the Y direction and the CLK lines 80a and 80 in the X direction are provided.
As the shield lines for e, 84b, 88b, and 88e, existing GND lines and VDD lines are used, and there is no need to provide a dedicated shield line, so that the area can be reduced accordingly.

[0053]

According to the present invention, a VDD / GND wiring is not newly provided as a shield for a clock signal line,
Since the existing VDD / GND wiring is used, it is possible to minimize the increase in the area and the deterioration of the wiring property due to the shield wiring for preventing the crosstalk.

According to the present invention, skew adjustment can be easily performed by inserting a buffer into a cell.

[Brief description of the drawings]

FIG. 1 is a diagram showing a first embodiment of a layout of a wiring of a one-phase clock signal in a semiconductor integrated circuit.

FIG. 2 is a diagram showing a second embodiment of the layout of the wiring of the two-phase clock signal in the semiconductor integrated circuit.

FIG. 3 is a diagram showing a third embodiment of the layout of the wiring of the two-phase clock signal in the semiconductor integrated circuit.

FIG. 4 is a diagram showing a fourth embodiment of a wiring layout of a multi-phase clock signal in a semiconductor integrated circuit.

FIG. 5 is a diagram showing an example of a conventional technique.

FIG. 6 is a diagram showing another example of the related art.

[Explanation of symbols]

10 cell 12 VDD line 14 GND line 16, 18, 30, 32, 34 CLK line wiring area 20, 36, 38, 50, 52, 54, 58 CLK line 40, 42, 56, 81, 82, 86, 90 Shield line

Claims (10)

[Claims] 1. A semiconductor integrated circuit in which a power supply line and a ground line for supplying power to a cell are wired, wherein the power supply line and / or the ground line is used as a shield line for a clock signal line. Characteristic semiconductor integrated circuit. 2. The semiconductor integrated circuit according to claim 1, wherein the power supply lines are arranged on both sides to form a clock signal line wiring region, and the clock signal line is wired in the wiring region. 3. The clock signal line wiring region is formed by arranging the ground lines on both sides, and a clock signal line is wired in this wiring region.
A semiconductor integrated circuit as described in the above. 4. The clock signal line according to claim 1, wherein the power supply line and the ground line are arranged on both sides to form a clock signal line wiring region, and the clock signal line is formed in the wiring region. Semiconductor integrated circuit. 5. A first clock signal line wiring area between a power supply line and a ground line, wherein a shield line is wired between the power supply line and the ground line which are wired adjacently. 2. The semiconductor integrated circuit according to claim 1, wherein a second clock signal line wiring region is provided between a ground line and the shield line, and a clock signal line is wired in the first and second wiring regions. 3. circuit. 6. A method for wiring a power supply line and a ground line for supplying power to a cell and a clock signal line for supplying a clock signal to the cell in the semiconductor integrated circuit, the method comprising: Or, using the ground line,
A wiring method, comprising: forming a clock signal line wiring region; and wiring a clock signal line in the wiring region. 7. The wiring method according to claim 6, wherein the clock signal line wiring region is formed between power supply lines that are wired adjacently. 8. The wiring method according to claim 6, wherein said clock signal line wiring area is formed between adjacently wired ground lines. 9. The wiring method according to claim 6, wherein said clock signal line wiring region is formed between a power line and a ground line which are wired adjacently. 10. The clock signal line wiring region, wherein a shield line is wired between the power line and the ground line which are wired adjacently, and a clock signal line wiring region is provided between the power line and the shield line.
7. The wiring method according to claim 6, wherein the wiring is formed between the ground line and the shield line.