JP2000217339A - Semiconductor boosting circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor boosting circuit which can get a sufficient current supplying capacity and, in addition, can efficiently acquire a boosting ability. SOLUTION: A semiconductor boosting circuit is provided with an oscillator circuit 10 which outputs a prescribed oscillate signal, a boosting control section 20 which outputs a control output to a load consuming circuit 30 when the circuit 10 outputs the oscillate signal, and a voltage discriminating circuit 11 which controls the circuit 10 upon discriminating that the voltage of the section 20 is a prescribed value. The control section 20 is provided with a boosting section 12 which outputs a control output to the load consuming circuit 30 from a first output transistor Q1 by means of the circuit 10, a boosting section 13 for converting voltage which outputs a control output from a second output transistor Q2 in accordance with the output of the circuit 10, and a voltage converting circuit 14 which is controlled by the output of the boosting section 13 and connects converted outputs following the output of the circuit 10 to the gates of the first and second output transistors Q1 and Q2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor booster circuit, and more particularly to a semiconductor booster circuit such as a charge pump circuit used for a DRAM or the like.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram showing a configuration of a general boosting circuit. This semiconductor booster circuit includes an oscillator circuit 10 for extracting an oscillation output of a predetermined frequency, a voltage determination circuit 11 for determining whether an output voltage is at a predetermined value, and a booster unit 12 for obtaining a predetermined boost from the output of the oscillator circuit 10. And an output control circuit 15 for controlling the output of the booster 12, and a consumption circuit 30 such as an inverter serving as an output load. The boosting unit 12 includes a boosting logic unit 16 and an output inverter 17 for inputting the output of the oscillator circuit 10 to a plurality of inverters, and an output MO that receives the output of the output inverter 17 via a boosting capacitor Cp1.
And an S transistor Q1.

The voltage at each contact in this circuit configuration is shown in FIG.
FIG. An output Vosc of a predetermined oscillation cycle tosc is output from the output of the oscillator circuit 10, and this output Vosc is output.
Is amplified by the output control circuit 15 to become an output Vgin, and this output is output to the MOS transistor Q via the capacitor Cp3.
A voltage V on which the power supply voltage Vcc1 is superimposed as the gate voltage of 1
gout. As for the output of the boosting logic section 16, the output Vcp1 via the boosting capacitor Cp1 is input to the drain of the output MOS transistor Q1, and the output voltage VP1 is obtained from the source of the MOS transistor Q1. Note that M
Since there is a source-gate potential Vgs2 of the OS transistor Q1, the output voltage VP1 is higher than the double potential 2Vcc1 by the potential Vgs1.
gs2 less.

In this conventional circuit, the power supply voltage Vcc is 5 V
Alternatively, since the voltage was 3.3 V, the gate-source potential difference Vgs2 of the output transistor of the booster circuit could be secured, and the supply capability was obtained. However, with the miniaturization and large capacity of the memory cells, the power supply voltage has been reduced.
5V is becoming common, and the voltage is further reduced.

With the reduction in voltage, the gate signal potential Vgout of the output transistor of the booster circuit cannot secure a potential difference Vgs2 with respect to the output potential Vp1 of the booster circuit. In this case, the voltage drop due to the threshold voltage and the substrate bias effect cause a reduction in capacity, so that the supply current capacity cannot be obtained with respect to the current consumption. As a result, the operation of the consuming circuit causes the output potential Vp1 of the booster circuit to continue to drop, causing the consuming circuit 30 to malfunction.

The operation of the consuming circuit 30 will be briefly described with reference to the waveform diagram of FIG. This consumption circuit 30
The charge and discharge of the consumed charge amount CD are repeated every cycle, and the input signal Vcyi of the consumption circuit 30 has a cycle tcyc. When the input signal Vcyi is at “L” level, the charge amount CD
And charge amount C when input signal Vcyi is at “H” level.
D is to be discharged. The source of the charge amount CD consumed by the consumption circuit 30 is the output Vp1 of the booster circuit. If the cycle tcyc is 70 ns, the oscillation cycle tos
c is 1/2 to 1/4 of the period.

Here, the oscillation cycle tosc of the signal Vosc output from the oscillator circuit 10 is different from the operation cycle tcyc of the consuming circuit 30, and the oscillation cycle tosc is oscillated several times during the normal operation cycle tcyc and supplied to the consuming circuit 30. You.

At this time, the power supply waveform VP1 supplied from the booster circuit
The state of is shown. When the input signal Vcyi is at the “L” level, the charging operation is started for the charge amount CD of the output load.
A potential drop occurs. Note that the potential drop ΔV1 of the power supply source
Is proportional to the charge / discharge amount CD and the capacity CH loaded on the output unit, and as the load capacity CH increases,
The potential drop amount ΔV1 becomes smaller. Further, the potential drop amount ΔV2 of the consuming circuit 30 depends on the speed of the consuming circuit with respect to the charge / discharge amount, and the booster circuit operates until charging is completed. Here, if the current supply capacity of the booster circuit is insufficient, it becomes impossible to supply the electric charge CD within the operation cycle tcyc, so that a potential drop occurs every operation cycle tcyc. As a result, power supply to the consumer circuit cannot be obtained, resulting in an operation failure.

Further, as a method of avoiding the problem of the conventional example, Japanese Patent Laid-Open Publication No. Hei 8-205526 discloses a structure in which a booster voltage Vpp is secured by boosting the gate potential of an output transistor by a voltage converter. ). 8 is a block diagram showing a circuit configuration of the conventional example 2, FIG. 9 is a circuit diagram of an example of the voltage conversion circuit 14 of FIG. 8, and FIG. 10 is a waveform diagram of operating voltages at respective contacts in the circuit configuration of FIG. It is.

This booster circuit has a common internal power supply V
Instead of the output control circuit 15 operated by cc1, a voltage conversion circuit 14 operated by another external power supply Vcc2 is used as shown in FIG. The voltage converter 14 receives the output signal of the oscillator circuit 10 at the gate terminal and the PMOS transistor Q11 connected between the power supply voltage Vcc and the input node N1 as shown in FIG. NMOS transistor Q13 connected between power supply voltage Vcc
A transistor Q12 connected between the output node N2 and the output node N2, and an NMOS transistor Q12 connected between the output node N2 and the ground voltage Vss to supply the gate terminal with a signal from the oscillator circuit 10 inverted by the inverter 40.
14.

The gate terminal of the PMOS transistor Q11 is connected to the output node N2.
Twelve gate terminals are connected to the input node N1.
The output node N2 is connected to the boost capacitor Cp3. As shown in the figure, a PMO with gate terminals cross-connected
S transistor Q11,12 and NMOS transistor Q
A so-called cascode amplifier is constituted by 13, 14.

In this booster circuit, when the output of the oscillator circuit 10 is input at a level that allows the NMOS transistor Q13 to conduct, the input node N1 is discharged and its voltage becomes a logic "L" level, and the gate terminal is connected to the input node N1. Are connected, the PMOS transistor Q12 becomes conductive. Thereby, output node N2 is charged to the level of power supply voltage Vcc. Therefore, the boost node B, that is, the gate voltage of the output transistor Q1 is boosted to the voltage level of 2Vcc. That is, since the boosting node B is boosted to a much higher level than in the prior art, the effect of the voltage drop due to the threshold voltage Vt of the output transistor Q1 can be suppressed, and a large amount of charge can be supplied to the boosted voltage Vpp. . Also in the second conventional example, the voltage conversion circuit 14
Since the power supply potential is not sufficient, a boosted potential cannot be obtained. For example, when the power supply potential Vcc1 is 2.3 V and the output potential VP1 is desired to be 3.5 V, the output transistor Q1
Requires a gate potential about twice the normal threshold potential Vt due to the substrate bias effect. If the normal threshold potential Vt is 0.7 V, a stable potential of about 4.9 V or more is required. Is required. However, in the general boosting circuit of FIG. 5, the gate potential is Vcc1 × 2 = 4.6.
Since only V can be obtained, current supply capability cannot be obtained. Also in the booster circuit of FIG. 8, the power supply voltage Vcc
When 1 is 2.3 V and the power supply voltage Vcc2 is 2.5 V, the gate potential becomes Vcc1 + Vcc2 = 4.8 V, and although the gate potential is slightly secured from the above-described conventional example 1, the current supply capability is still not obtained. I can't.

Further, as a method of securing the gate potential of the output transistor of the booster circuit, there are a block diagram of the circuit configuration of FIG. 11 and an operation waveform diagram of FIG.
In this circuit, the power supply voltage of the voltage conversion circuit 14 is supplied from the output potential VP1 from the booster circuit. This allows
According to the conventional example 1, the gate potential is Vcc1 + VP1 = 2.3.
V + 3.5V = 5.8V can be obtained, and the capability is greatly improved as compared with the above-mentioned conventional examples 1 and 2.

However, when the consuming circuit 30 operates in a short cycle, charging and discharging of the electric charge CD are repeated, so that a potential contact of the output potential VP1 fluctuates by several volts. Therefore, a stable gate potential cannot be obtained.

[0015]

As described above, in the conventional semiconductor booster circuit, in the general booster circuit shown in FIG. 5, only the gate potential Vcc1.times.2 = 4.6 V can be obtained. Can not get. FIG.
In the booster circuit of the above, when the power supply voltage Vcc1 is 2.3 V and the power supply voltage Vcc2 is 2.5 V, the gate potential is Vcc1
+ Vcc2 = 4.8 V, and although the gate potential is slightly secured as compared with the above-mentioned conventional example 1, the current supply capability cannot be obtained yet.

Further, in the case of the circuit configuration shown in FIG. 11, the performance is greatly improved as compared with the conventional examples 1 and 2. However, when the consuming circuit 30 operates in a short cycle, the charge / discharge of the charge amount CD is repeated. Therefore, the potential contact of the output potential VP1 is several volts.
Is generated. Therefore, since a stable gate potential cannot be obtained, there is a problem that the boosting capability cannot be obtained efficiently.

An object of the present invention is to solve these problems and to provide a semiconductor booster circuit capable of sufficiently obtaining a current supply capability and efficiently obtaining a boosting capability.

Another object of the present invention is to provide a semiconductor booster circuit capable of obtaining a stable high potential with respect to a gate potential input to an output transistor of the booster circuit.

[0019]

According to the present invention, there is provided an oscillator circuit for outputting an oscillation signal having a predetermined oscillation frequency, a boost controller for outputting a control output to a load consuming circuit by the output of the oscillator circuit, A voltage booster circuit that determines that the output voltage of the controller is at a predetermined value and controls the output level of the oscillator circuit, wherein the booster controller controls a control output based on the output of the oscillator circuit. A booster for outputting a load from the first output transistor to the load consuming circuit, a booster for voltage conversion for outputting a control output from the second output transistor in accordance with an output from the oscillator circuit, and an output of the booster for voltage conversion. A voltage conversion circuit that supplies a converted output to the gates of the first and second output transistors in accordance with the output to the oscillator circuit. The features.

[0020]

FIG. 1 is a circuit diagram showing a circuit configuration according to an embodiment of the present invention. Conventionally, the power is supplied from the output control circuit 15 of the gate signal generation circuit for controlling the output transistor of the booster circuit or the power supply voltage f of the voltage conversion circuit 14 from the internal power supply Vcc1 or the external power supply Vcc2. In addition, a voltage conversion dedicated booster 13 is provided for the power supply voltage of the voltage conversion circuit 15.

Since the power supply voltage is supplied to the voltage conversion circuit 14 by the voltage conversion dedicated booster 13, the gate signal for controlling the output transistor Q1 of the booster circuit is
An output potential about three times as high can be obtained. Therefore, the potential difference Vgs between the gate and the source of the output transistor Q1 of the booster circuit can be ensured, and the effect of preventing the boosting capability from being reduced due to the substrate bias can be obtained. In particular, it has a great effect on lowering the power supply voltage.

Referring to FIG. 1, this semiconductor booster circuit includes an oscillator circuit 10, a voltage determination circuit 11, a boost controller 20, and a consuming circuit 30 such as an inverter serving as an output load. The unit 20 is the booster 1
2, a voltage conversion dedicated booster 13 and a voltage conversion circuit 14. The oscillator circuit 10 outputs a waveform having an arbitrary cycle, and the output is controlled by a voltage determination circuit 11 that determines the output voltage value VP1 of the booster circuit. Further, the voltage determination circuit 11 detects an output voltage value of the booster circuit set arbitrarily, and when the voltage reaches an arbitrary voltage, stops the operation of the oscillator circuit 10 and sets the output voltage of the booster circuit to an arbitrary value. When the voltage drops below the voltage value, the oscillator circuit 1
0 is provided. The output signal from the oscillator circuit 10 is supplied to a booster 13, a booster 14 dedicated to voltage conversion, and a voltage converter 15.

The boosting section 13 includes a boosting circuit logic section 16 for shaping the output signal Vosc from the oscillator circuit 10, an inverter circuit 17 for driving the same, and an inverter circuit 17 for driving the same.
And an output transistor Q1 for controlling the consuming circuit 30 by inputting the output of the circuit 30 via a pumping capacitor Cp1. The size (dimension) of the pumping capacitor Cp1, the inverter circuit 17 for driving the pumping capacitor Cp1, and the output transistor Q1 for controlling the supply to the consumption circuit 30 depends on the amount of electric charge CD consumed and the operation cycle of the oscillator circuit.
Is set, and the circuit scale is increased as the charge consumption CD is increased and the consumption cycle is shortened. Also, the capacitance CH added to the output of the booster circuit
Is a capacitance for minimizing the amount of potential fluctuation during the operation of the consuming circuit 30, and a large capacitance value is required to reduce the amount of potential fluctuation.

For example, in the case of a DRAM, the electric charge consumption CD
Corresponds to the amount of electric charge consumed, 200 to 400 pF, the capacitance CH is several thousand to several tens of thousands pF, and the pumping capacitance Cp1 is several hundred p.
F, the pumping capacitances Cp2, 3 are several to several tens of pF, and the capacitance Cd is several pF.

The voltage conversion-dedicated boosting section 13 has exactly the same configuration as the above-described boosting section 12, and includes a voltage conversion-dedicated logic section 18 for shaping an output signal from the oscillator circuit 10, and an inverter circuit 19 for driving the same. , This inverter circuit 19
And an output transistor Q2 for controlling the voltage conversion circuit 14 by inputting the output of the circuit through the pumping capacitor Cp2. The output signal of the voltage conversion dedicated boosting unit 13 supplies a potential exclusively for the voltage conversion circuit, and the consumption of the voltage conversion circuit 14 is much smaller than that of the boosting unit 12.
Accordingly, the dimensions of the pumping capacitor Cp2, the inverter circuit 19 for driving the pumping capacitor Cp2, and the output transistor Q2 for controlling the supply to the voltage conversion circuit 15 can be set small. Further, the capacitance Cd added to the output of the voltage conversion dedicated booster 13 is a capacitance that suppresses the amount of potential fluctuation during the operation of the voltage conversion circuit 14.

The voltage conversion circuit 14 uses the output voltage VP2 boosted by the voltage conversion-dedicated booster 13 as a power supply voltage, and converts the output signal having an arbitrary period from the oscillator circuit 10 into a signal whose voltage has been boosted. It is a circuit that converts and outputs. The signal Vgin output by the voltage conversion circuit 14 is
The potential is input to the pumping capacitor Cp3, and the potential is further boosted. The boosted signal Vgout is configured to be a gate signal of the output transistors Q1 and Q2 of the boosting unit 12 and the voltage conversion dedicated boosting unit 13.

In the figure, the inverter circuit of the consuming circuit 30 is a simplified model of a circuit that consumes a boosted potential and is not directly related to the configuration of the present invention, so that it is a simplified circuit configuration diagram.

Next, the operation of this embodiment will be described with reference to FIGS.
This will be described below. The voltage conversion-dedicated booster 13 receives the power supply level Vcc1 and the signal Vosc of the oscillation cycle tosc from the oscillator circuit 10, and the inverter 19 and the pumping capacitor C
With p2, an output waveform Vcp2 is formed. further,
The output potential VP2 is supplied via the output transistor Q2. Since the output of the output potential VP2 is loaded with the capacitor Cd for suppressing the potential fluctuation, a stable potential is always supplied. By setting the capacitance value Cd several times as large as the amount of electric charge consumed in the voltage conversion circuit 14, the amount of potential fluctuation can be suppressed. Since this potential VP2 is supplied as power to the voltage conversion circuit 14, the output signal Vgin is converted into the amplitude of the potential VP2 by the voltage conversion circuit 14 which receives the signal Vosc. Further, since the voltage is boosted by the pumping capacitance Cp3, an amplitude waveform Vgout is obtained. Since this amplitude waveform Vgout is input to the gate of the output transistor Q1 of the booster circuit 12, a potential Vgs1 between the gate and the source can be obtained.

FIG. 3 is a circuit diagram of another embodiment of the present invention. In this circuit, the current supply capability of the booster circuit is further devised. In the figure, the booster 12 shown in FIG.
And a plurality of blocks 20-1 to 20-n in parallel with each other including a block 20 including a voltage conversion circuit booster 13 and a voltage converter 14.
Are arranged, and output signals Vosc1, Vosc2... Voscn having different phases from the oscillator circuit 10 are input.

As described above, in this embodiment, since the phases of the current supply timings are different, a steady current value can be supplied. Further, since the supply capacity can be increased for a circuit having a large amount of electric charge, the effect of increasing the boosting ability can be obtained.

In the configuration of FIG. 3, the output potential VP2 of the voltage conversion-dedicated booster 13 is set to a more steady potential, and therefore, as shown in FIG.
-N using the output potential VP2 of the voltage-conversion dedicated boosting unit 13, and removing the voltage-conversion dedicated boosting units 13 and the voltage conversion circuit 14 of the other boosting control units 20-1 to 20-1. -1 to n-1 may be used in common.

As an example of FIGS. 3 and 4, when the amount of electric charge CD is 400 pF, the sum of the pumping capacitances Cp1 only needs to be equal to or more than the amount of electric charge consumed. , The boost controller 20
Means that the capacitance Cp1 should be 100 pF or more.

Therefore, the dimension of the inverter in the case of one boost control unit 20 is about four times as large as that in the case of four boost control units 20. In this way, the dimension and the number of the boost control units 20 are set in proportion to the electric charge consumption CD. As a specific setting, it is also possible to arrange and increase the number of boost control units 20 (21) to supply a more stable boost potential.

[0034]

As described above, according to the present invention, the gate signal potential of the output transistor of the booster circuit can be sufficiently secured, and a potential difference from the output potential of the booster circuit can be obtained.
It is possible to prevent a decrease in the boosting ability due to the substrate effect in the output transistor of the boosting circuit, and to obtain a high boosting ability. Further, since the output transistor is controlled by a stable gate signal, there is an effect that operation stability can be obtained.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a booster circuit according to the present invention.

FIG. 2 is a timing waveform chart showing an operation example of FIG. 1;

FIG. 3 is a circuit diagram showing a booster circuit according to a second embodiment of the present invention.

FIG. 4 is a circuit diagram illustrating a booster circuit according to a third embodiment of the present invention.

FIG. 5 is a circuit diagram showing a first example of a conventional booster circuit.

FIG. 6 is a timing waveform chart showing an operation example of FIG. 5; <BR>

FIG. 7 is a timing waveform chart showing an operation example of the consumption circuit of FIG. 5;

FIG. 8 is a circuit diagram showing a second example of a conventional booster circuit.

FIG. 9 is a circuit diagram of an example of the voltage conversion circuit of FIG. 7;

FIG. 10 is a timing waveform chart showing an operation example of FIG. 7;

FIG. 11 is a circuit diagram showing a third example of a conventional booster circuit.

FIG. 12 is a timing waveform chart showing an operation example of FIG. 10;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Oscillator circuit 11 Voltage judgment circuit 12 Boost unit 13 Boost unit for voltage conversion 14 Voltage conversion circuit 15 Output control circuit 16 Boost logic unit 17, 19, 40 Inverter 18 Voltage boost logic unit for voltage conversion 20, 20-1 to n, 21 -1 to n step-up control unit 30 consumption circuit (inverter) C1, step-up capacitor Q1, MOS transistor Q11, 12 PMOS transistor Q13, 14 NMOS transistor

[Procedure amendment]

[Submission date] October 28, 1999 (1999.10.
28)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

4. The semiconductor booster circuit according to claim 1 , wherein the pumping capacitance is set to be equal to or more than the amount of electric charge consumed by the load consuming circuit.

5. A method according to claim 1, wherein the amount of charge consumed by said load consuming circuit is:
2. The semiconductor booster circuit according to claim 1 , wherein a dimension and the number of used booster control units are set.

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0019

[Correction method] Change

[Correction contents]

[0019]

According to the present invention, there is provided an oscillator circuit for outputting an oscillation signal having a predetermined oscillation frequency, a boost controller for outputting a control output to a load consuming circuit by the output of the oscillator circuit, A voltage determination circuit for determining that the output voltage of the control unit is at a predetermined value and controlling the output level of the oscillator circuit, wherein the boost control unit outputs the output of the oscillator circuit by a predetermined number. Inn
Amplified by the logic unit consisting of the inverter and the output of this logic unit
A predetermined number and boosting unit, the output to the oscillator circuit to be output to the load supply circuit as a first control voltage is supplied to the first output transistor is boosted through the first pumping capacitor
Amplified by a logic unit composed of inverters
Is boosted through a second pumping capacitor , supplied to a second output transistor and output as a second control voltage, and the voltage conversion booster is boosted.
An output of the oscillator circuit using a second control voltage as a driving power source;
And a voltage conversion circuit for connecting the converted output to the gates of the first and second output transistors, respectively.

[Procedure amendment 3]

[Document name to be amended] Drawing

[Correction target item name] Fig. 1

[Correction method] Change

[Correction contents]

FIG.

Continuation of the front page F term (reference) 5B024 AA15 BA27 CA27 5F038 BG02 BG03 BG05 DF05 DT12 EZ20 5H730 AA14 BB02 BB57 BB82 DD04 FD01

Claims (6)

[Claims] An oscillator circuit for outputting an oscillation signal having a predetermined oscillation frequency, a boost controller for outputting a control output to a load consuming circuit by an output of the oscillator circuit, and an output voltage of the boost controller being a predetermined value. And a voltage determination circuit for controlling the output of the oscillator circuit by determining that the booster control unit outputs a control output from the first output transistor to the load consuming circuit based on the output of the oscillator circuit. A booster for outputting, a booster for voltage conversion for outputting a control output from a second output transistor in accordance with an output to the oscillator circuit, and a converter controlled by an output of the booster for voltage conversion and according to the output of the oscillator circuit. A voltage conversion circuit for connecting an output to the gates of the first and second output transistors, respectively. 2. The semiconductor boosting circuit according to claim 1, wherein the load consuming circuit is driven by a plurality of boosting control units. 3. A boosting unit for voltage conversion and a voltage converting circuit of one boosting control unit among a plurality of boosting control units are commonly used, and a boosting unit for voltage conversion of another boosting control unit and 3. The semiconductor booster circuit according to claim 2, wherein the voltage conversion circuit is omitted. 4. The boosting unit and the voltage converting boosting unit of the boosting control unit include a logic unit including a predetermined number of inverters, and an output transistor for inputting an output of the logic unit via a pumping capacitor. , 2 or 3. 5. The semiconductor booster circuit according to claim 4, wherein the pumping capacitance is set to be equal to or more than the amount of charge consumed by the load consuming circuit. 6. In accordance with the amount of electric charge consumed by the load consuming circuit,
5. The semiconductor booster circuit according to claim 4, wherein the dimension and the number of used booster control units are set.