JP2000206196A - Information processing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to study whether a cause exists in a PLL circuit when an imperfect operation is generated at the time of system estimation in a device having a PLL data reading function. SOLUTION: A PLL counter copy 57 as the copy of a PLL counter 52 is built in an ordinary scan path. Scan reading of the internal state value of the PLL counter copy 57 is performed by using a diagnostic processor 300. The state of the PLL circuit can be monitored from the outside. A the time when a system is started, a trouble caused by clock (e.g. imperfect lock of the PLL or skew increase due to difference of each PLL in an LSI 150) can be early detected. Thereby special measuring instruments are unnecessary and data for reliability improvement can be gathered.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus, and more particularly, to a digital PLL (Digital Phase Lock) used for a synchronization circuit of a computer or the like.
The present invention relates to an information processing apparatus that performs clock phase adjustment using an ed Loop (DPLL) circuit.

[0002]

2. Description of the Related Art As shown in FIG. 1 which describes a conventional information processing apparatus with reference to FIG. 4, a reference clock distributed from a clock supply circuit (not shown) at the time of normal system startup. (REF) 11 and the internal clock (CK)
O) The phase comparison circuit 51 compares the lead / lag of the phase with 14). Then, the count-up /
By inputting the down signal 12 to the PLL counter 52, the PLL counter 52 performs a count up / down operation. As a result, a PLL counter output signal 13 is output, whereby the variable delay circuit 53 operates to delay the timing clock (CLK) 10. By these circuits (PLL circuits), the reference clock (REF) 1
1 and the internal clock (CKO) 14 are adjusted in phase.

In such an apparatus, the diagnostic processor 30
0 to the LSI 50 inside the card (CARD) 100, a shift mode (also called scan mode) signal (S
FT) 30 and a scan-in signal (SIN) 31 are input. Then, a scan-out signal (SOT) 33 is output from the LSI 50.

Although not shown, the LSI 60, the diagnostic processor 300, and a clock supply circuit (not shown)
An interface similar to that of the LSI 50 exists between them. The scan signal 33 is returned to the diagnostic processor 300 as a scan signal 34 via a scan path in the LSI 60.

[0005] In the card 200, a similar interface exists between the card 200 and the diagnostic processor 300.
Through the diagnostic processor 3 as a scan signal 36.
Returned to 00.

[0006]

In the prior art device described above, the PLL counter 52 was not built into the normal scan path of the device. For this reason, there is no effective means for knowing the internal state value of the PLL counter 52, that is, the phase adjustment value. Therefore, when a malfunction occurs during the evaluation of the system, it is difficult to determine whether the cause is a PLL circuit.

Japanese Patent Application Laid-Open No. Sho 59-110227 merely changes the frequency of a clock, and cannot solve the above-mentioned disadvantages of the prior art.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned drawbacks of the prior art. It is an object of the present invention to provide an apparatus having a PLL data reading function, which is used to determine the cause of any malfunction during system evaluation. PLL
An object of the present invention is to provide an information processing apparatus capable of determining whether or not the processing is performed by a circuit, requiring no special measuring instrument, and collecting data for improving reliability.

[0009]

An information processing apparatus according to the present invention includes a DPLL circuit for generating an internal clock synchronized with an externally input clock, and a circuit to be measured operating in synchronization with the internal clock. An information processing apparatus for performing a test, comprising: an operation state deriving unit that outputs operation state data indicating an operation state of the DPLL circuit. The operation state deriving means includes a data extraction circuit for extracting the operation state data, and a scan path for deriving the extracted data.

The operating state data is the DPLL.
A count value of a PLL counter included in the circuit, wherein the data extraction circuit extracts the count value in response to a control signal input from the outside. The semiconductor device further includes a selection circuit for selectively outputting data indicating a state of each logic circuit in the circuit under test and the operation state data to the scan path. Further, the control signal is a shift clock for shifting the scan path, and the data extraction circuit extracts the count value at a transition timing of the shift clock. The DPLL circuit includes a phase comparison circuit for comparing the phase of an externally input input clock with the phase of a reference clock, and increases or decreases the count value of the PLL counter in accordance with the phase comparison. And a variable delay circuit for delaying the input clock in accordance with the internal clock.

In short, in this apparatus, a copy of the PLL counter, which is a copy of the PLL counter, is incorporated in a normal scan path (Scan Path) of the apparatus (system). Then, scan reading of the internal state value of the PLL counter copy is enabled by using the diagnostic processor, so that the state of the PLL circuit can be monitored from outside. As a result, a malfunction caused by a clock at the time of system startup (for example, an increase in skew due to a PLL lock failure or a difference between PLLs in an LSI) can be quickly detected.

[0012]

Next, an embodiment of the present invention will be described with reference to the drawings. In the drawings referred to in the following description, the same parts as those in the other drawings are denoted by the same reference numerals.

FIG. 1 is a block diagram showing an embodiment of an information processing apparatus according to the present invention. 4, the same parts as those in FIG. 4 are indicated by the same reference numerals, and the detailed description of those parts will be omitted.

In FIG. 1, the information processing apparatus according to the present embodiment detects a phase advance / delay of a phase between a reference clock (REF) 11 and an internal clock (CKO) 14 provided from a clock supply circuit (not shown). Comparison circuit 51 and count-up / down signal 12 from phase comparison circuit 51
, A variable delay circuit 53 that delays the timing clock (CLK) 10 by the PLL counter output signal 13 from the PLL counter 52, and a shift mode signal (S
When the FT 30 becomes a valid value (for example, logic “1”), the scan mode is set and the logic circuit 54 that outputs the logic circuit scan output 16 which is the state value of the internal register
When the test mode signal (TST) 32 becomes a valid value (for example, logic “1”), the scan mode is set,
PLL counter copy 5 that scans out internal state values
7, a copy circuit 56 for copying the internal state value 17 of the PLL counter 52 to the PLL counter copy 57, and an input when the test mode signal (TST) 32 becomes a valid value (for example, logic "1"). A selection circuit 55 for selecting the PLL counter copy scan output 15 from the logic circuit scan output 16 and the PLL counter copy scan output 15; an LSI 50 including these circuits;
An LSI 60 that is connected to the I50 in a scan path and includes a similar scan circuit, and a card 100 that includes these LSIs
And a card 200 including a similar scan circuit, and a diagnostic processor 300 connected to these cards by a scan path and editing and correcting the scan data collected by the scan operation so that the data can be monitored from the outside. ing.

In such a configuration, at the time of normal system startup, a reference clock (REF) 11 and an internal clock (CKO) 14 distributed from a clock supply circuit (not shown) are provided.
The lead / lag of the phase is compared and detected by the phase comparison circuit 51. The count-up / down signal 12, which is the comparison (detection) result signal, is input to the PLL counter 52. The count-up / down signal 12 causes the PLL counter 52 to perform a count-up / down operation. As a result, the PLL counter output signal 13 Is output. As a result, the variable delay circuit 53 operates to delay the timing clock (CLK) 10. These circuits (PLL
Circuit), the phase of the reference clock (REF) 11 and the phase of the internal clock (CKO) 14 are adjusted. When the phase adjustment is completed, the PLL counter 52 is held, and the clock phase adjustment value is held in the PLL counter 52. P
The internal state value 17 of the LL counter 52 is
Is copied to the PLL counter copy 57 by the output 18 of the.

Here, as shown in FIG. 2, the PLL counter 52 has a configuration in which the output of the +1 circuit 520 is input to the least significant bit of the counter, and its internal state value, that is, the count output is the PLL counter. Counter copy 57
Is copied to In this case, the output 18 of the copy circuit 56
The count output is input to the PLL counter copy 57 at the transition timing of.

The copy circuit 56 is composed of flip-flops (F / F) 561 and 562 connected in two stages and an AND circuit 563. And F / F
The output of the PLL counter 52, that is, the count output, is extracted at the timing when the output of the F / F 562 and the inverted output of the F / F 562 are input to the AND circuit 563, and the output of the AND product transitions from the L level to the H level. The data is input to the PLL counter copy 57. In this example, TST
In this configuration, the contents of the PLL counter 52 are copied at the signal transition timing (rising timing).
The L counter 52 stops operating after adjusting the difference between the reference clock 11 and the timing clock 10, so that the PLL
The copy circuit may be modified so that the contents of the counter are always copied.

Returning to FIG. 1, a diagnostic processor 300 as a means for monitoring and correcting the internal state of the apparatus from the outside at the time of periodic system diagnosis and failure, and the like, are placed inside the apparatus (system). The scan path will be described.

As shown in FIG. 1, a shift mode signal (SFT) 30 and a scan-in signal (SI) are sent from the diagnostic processor 300 to the LSI 50 inside the card 100.
N) 31 and a test mode signal (TST) 32 are input. Then, a scan-out signal (SOT) 33 is output from the LSI 50.

When performing the scan operation of the PLL counter copy 57, the test mode signal (TST) 32 is set to a valid value (for example, logic "1"). By doing so, the PLL counter copy 57 enters the scan mode (also called shift register mode). By inputting the reference clock (REF) 11 in this state, the PLL counter copy scan output 15, which is the internal state value,
It is output to the selection circuit 55. The selection circuit 55 selects the PLL counter copy scan output 15 based on the test mode signal (TST) 32 and outputs a scan-out signal (SOT) 33 to the LSI 60.

The diagnostic processor 300 sets the test mode signal (TST) 32 to a valid value (eg, logic “1”), and sets a predetermined total F / F (Flip Flo).
p) The output of the reference clock (REF) 11 for about several minutes is instructed to a clock supply circuit (not shown), whereby the internal state value of the PLL counter copy 57 scanned and output is taken into a buffer in the diagnostic processor 300. Thereafter, by editing the contents as necessary, the internal state of the PLL counter copy 57 can be monitored from outside.

Although not shown in FIG. 1, L
An interface similar to the LSI 50 exists between the SI 60 and the diagnostic processor 300 and a clock supply circuit (not shown). The scan signal 33 is returned to the diagnostic processor 300 as a scan signal 34 via a scan path in the LSI 60.

The same applies to the case where the internal state of the logic circuit in each LSI is monitored. When scanning the logic circuit 54 in the LSI 50, the shift mode signal (SF
T) 30 to a valid value (for example, logic “1”), the register in the logic circuit 54 (general term for the F / F group) enters the scan mode, and the timing clock (C
LK) 10, the logic circuit scan output 16, which is the state value of the internal register, is output to the selection circuit 55. The selection circuit 55 outputs a shift mode signal (SF
T) 30, the logic circuit output 16 is selected, and the LSI 6
A scan-out signal (SOT) 33 to 0 is output.
Thereafter, similarly, the scan-out signal (SOT) 3
3 is returned to the diagnostic processor 300 as the scan signal 34, and the internal state value of the logic circuit 54 (inside the LSI) is edited and can be monitored from outside. Note that, as described above, the selection circuit 55 operates to selectively transmit the scan output 15 and the logic circuit output 16.

The diagnostic processor 300 sets the shift mode signal (SFT) 30 to a valid value (for example, logic “1”) and sets a predetermined total F / F (Flip Flop).
The output of the timing clock (CLK) 10 for about several minutes is instructed to a clock supply circuit (not shown), whereby the scan-output internal state value of the logic circuit 54 is fetched into a buffer in the diagnostic processor 300, and then required. By editing the contents according to the above, the internal state of the logic circuit 54 can be monitored from the outside.

In the card 200, a similar interface exists between the card 200 and the diagnostic processor 300.
Through the diagnostic processor 3 as a scan signal 36.
Returned to 00.

FIG. 3 is a flowchart explaining the operation of the information processing apparatus according to the embodiment of the present invention from the side of the diagnostic processor. In the figure, when performing a scan operation on a certain LSI, first, a card on which a scan operation is to be performed is selected (step 301). Next, when the scan operation of the PLL counter copy is performed, the test mode (T
ST) signal is set to a valid value (for example, logic "1") (steps 302 to 303). On the other hand, when the scan operation of the logic circuit is performed, the shift mode signal (SFT)
30 is set to a valid value (for example, logic “1”) (step 302 → 304).

When performing the scan operation of the PLL counter copy, the clock supply circuit is instructed to transmit a clock necessary to complete the scan read operation of the PLL counter copy. The scan data is edited and can be monitored from outside (step 305). Then, the test mode (TST) signal is set to an invalid value (for example, logic “0”) (step 306), and the scanning operation of the PLL counter copy is ended.

When performing a scan operation of a logic circuit, a clock supply circuit is instructed to transmit a clock necessary to complete a scan read operation of the logic circuit, thereby taking in scan data and scanning data of the logic circuit. Is edited to enable external monitoring (step 30).
6). Then, the shift mode signal (SFT) 30 is set to an invalid value (for example, logic “0”) (step 30).
8) Terminate the scan operation of the logic circuit.

As described above, the PLL shown in FIG.
According to the device having the data reading function, when any operation failure occurs during system evaluation, it is possible to determine whether the cause is caused by the PLL circuit. In this case, a special measuring device is required for the clock observation by the clock monitor output as in the conventional case, and it takes time to solve the problem. On the other hand, in this apparatus, no special measuring device is required, and data for improving reliability can be collected.

In FIG. 1, by incorporating the scan path of the PLL counter copy into the normal scan path of the apparatus (system), an increase in the hardware dedicated to the PLL scan data reading function can be suppressed, and the diagnostic processor and the like can be shared.

[0031]

As described above, according to the present invention, the internal state value of the PLL counter copy is read out by the scan path using the diagnostic processor, and the state of the PLL circuit can be monitored from the outside. When any operation failure occurs, it is possible to determine whether the cause is caused by the PLL circuit, and there is an effect that a special measuring instrument is not required and data for improving reliability can be collected. .

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an information processing apparatus according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating an example of an internal configuration of a PLL counter, a copy circuit, and the like in FIG. 1;

FIG. 3 is a flowchart illustrating an operation of the information processing apparatus of FIG. 1;

FIG. 4 is a block diagram illustrating a configuration of a conventional information processing apparatus.

[Explanation of symbols]

 50, 60 LSI 51 Phase comparison circuit 52 PLL counter 53 Variable delay circuit 54 Logic circuit 55 Selection circuit 56 Copy circuit 57 PLL counter copy 100, 200 Card 300 Diagnostic processor

Claims (6)

[Claims] 1. An information processing apparatus, comprising: a DPLL circuit that generates an internal clock synchronized with a clock input from the outside; and performing a test on a circuit under test that operates in synchronization with the internal clock. An information processing apparatus including an operation state deriving unit that outputs operation state data indicating an operation state of a circuit. 2. The information processing apparatus according to claim 1, wherein the operation state deriving unit includes a data extraction circuit for extracting the operation state data, and a scan path for deriving the extracted data. 3. The operation state data is a count value of a PLL counter included in the DPLL circuit, and the data extraction circuit extracts the count value in response to a control signal input from the outside. The information processing device according to claim 2. 4. The scanning circuit according to claim 2, further comprising a selection circuit for selectively outputting data indicating a state of each logic circuit in the circuit under test and the operation state data to the scan path. 3. The information processing apparatus according to 3. 5. The method according to claim 3, wherein the control signal is a shift clock for shifting the scan path, and the data extraction circuit extracts the count value at a transition timing of the shift clock. 4
An information processing apparatus according to claim 1. 6. The DPLL circuit includes a phase comparison circuit that compares a phase of an input clock input from the outside with a reference clock, and increases or decreases the count value of the PLL counter according to the phase comparison. 6. The information processing apparatus according to claim 3, further comprising a variable delay circuit that delays the input clock according to the count value, wherein the delayed output is used as the internal clock.