JP2000285688A - Non-volatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make uniformalizable easily the number of times of erasing among erasing blocks by constituting a non-volatile semiconductor memory device by providing plural erasing blocks having a data storage region and a region for storing the number of times of erasing, an address conversion table, first and second selecting means, and an replacing means. SOLUTION: The non-volatile memory control circuit 17 of a semiconductor memory 10 controls a non-volatile memory 18 at the time of transferring data with a sequencer circuit 13. The non-volatile memory 18 is a block erasing type non-volatile memory such as a flash memory and the like, a memory array is divided into several blocks, erasing pulse applying/erasing verifying are performed for each block. In this case, the memory array is divided into blocks BK(O)-BK(M) of (M+1) pieces, and each divided block is called as an erasing block. One part of the erasing blocks BK(O)-BK(M) is used as an address conversion table.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a nonvolatile semiconductor memory device, and more particularly, to a nonvolatile semiconductor memory device using a block erase type nonvolatile memory.

[0002]

2. Description of the Related Art A nonvolatile semiconductor memory device using a block erase type nonvolatile memory having a finite number of erasures, such as a flash memory, is more resistant to shocks and consumes less power than a magnetic memory device such as a hard disk. It is characterized by high cost and an upper limit of about several hundred thousand data rewrites. For this reason, a nonvolatile semiconductor memory device using a block erase type nonvolatile memory is used as a storage device of a portable computer that can be easily carried around or a film of an electronic camera.

Many of the host systems in the above-mentioned portable computers and electronic cameras have a FAT (File Al) for storing and managing data with high compatibility.
A location table type file system is used. In the FAT type file system, the inside of the storage device is divided into a certain size, for example, a sector, a cluster of several sectors, and the like (hereinafter, each of the divided units is referred to as an “erased block”). Each is numbered and managed. The numbers are put together in a table called FAT and stored in a specific area inside the storage device. The FAT is always referred to when reading / writing data, and if there is any change in the data, the FAT is also changed. Since the FAT is centrally managed in a specific area of the storage device, when viewed from the entire semiconductor storage device, the erase block used for storing the FAT is erased and erased compared to the erase block storing general-purpose data such as an application. Writing frequently occurs. If this is left as it is, only the erasure block for which FAT management is performed will exceed the upper limit of the number of times of erasure, so it is necessary to solve this problem in some way.

[0004] One solution to the problem is to replace the data of an erase block in which rewriting occurs frequently and an erase block in which rewriting does not frequently occur with a certain number of erasures not exceeding the upper limit of the number of erasures. US Patent 5,3
No. 88,083 stores the number of erasures of an erasure block. If a certain erasure block exceeds a predetermined number of erasures, the data of the erasure block is replaced with the data of the erasure block having the minimum number of erasures at that time And repeating this until all erase blocks have the same erase count. By averaging the number of erasures using this method, the number of erasures of all erase blocks can be kept uniform.

[0005]

However, in this leveling method, it is necessary to grasp the erase block having the smallest erase count among all erase blocks, and the difference in erase count between erase blocks is several times. Even at the level, leveling processing is performed until the same number of times of erasure is reached. The processing contents of the semiconductor memory device become complicated, and the life of the semiconductor memory device may be shortened.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a nonvolatile semiconductor memory device capable of easily leveling the number of erases between erase blocks. It is.

[0007]

A nonvolatile semiconductor memory device according to one aspect of the present invention includes a plurality of erase blocks, an address conversion table storage area, a first selecting means, and a second selecting means. And exchange means. Each of the plurality of erase blocks has a data storage area and an erase count storage area. The address conversion table storage area stores an address conversion table that associates a plurality of logical addresses with a plurality of erase blocks. The first selecting means selects a first erase block associated with a logical address given externally at the time of data writing from a plurality of erase blocks with reference to the address conversion table.
When the number of erasures stored in the first erasure block exceeds a predetermined number of erasures, the second selection unit refers to the address conversion table to select the second erasure block from the plurality of erasure blocks. select. The replacement means writes the data stored in the second erase block to the first erase block when the number of erases stored in the second erase block does not exceed the predetermined number of erases, and writes the data from the outside. The data is written to the second erase block, the first erase block is associated with the logical address associated with the second erase block, and the second erase block is associated with the first erase block. Associated logical address.

In the above nonvolatile semiconductor memory device,
It is only necessary to determine the number of erases stored in the second erase block, and it is not necessary to determine the total number of erases of a plurality of erase blocks. Therefore, the number of erasures between erase blocks can be easily leveled without requiring complicated processing.

[0009] Preferably, the address conversion table is divided into a plurality of sub-address conversion tables. The first selecting means further selects a sub address conversion table including a first erase block. When the number of erasures stored in the first erasure block exceeds a predetermined number of erasures, the second selection unit refers to the sub-address conversion table selected by the first selection unit to perform the second erasure. Select a block.

In the above nonvolatile semiconductor memory device,
The second selecting means refers to the sub-address conversion table selected by the first selecting means. Therefore, the number of times of erasure between erase blocks can be equalized more easily than when the entire address conversion table is referred to.

Preferably, an integral multiple of the storage capacity required for each of the sub-address conversion tables is equal to the storage capacity of each of the plurality of erase blocks.

A nonvolatile semiconductor memory device according to another aspect of the present invention includes a plurality of erase blocks, an address conversion table storage area, a first selecting means, a second selecting means, and a replacing means. And Each of the plurality of erase blocks has a data storage area and an erase count storage area. The address conversion table storage area stores an address conversion table that associates a plurality of logical addresses with a plurality of erase blocks. The first selecting means selects a first erase block associated with a logical address given externally at the time of data reading from a plurality of erase blocks with reference to the address conversion table. When the number of erasures stored in the first erasure block exceeds a predetermined number of erasures, the second selection unit refers to the address conversion table to select the second erasure block from the plurality of erasure blocks. select. When the number of erasures stored in the second erasure block does not exceed a predetermined number of erasures, the replacement means replaces the data stored in the first erasure block with the data stored in the second erasure block. The first erase block is replaced with the logical address to which the second erase block was associated, and the second erase block is associated with the first erase block.
Is associated with the logical address to which the corresponding erase block is associated.

In the above nonvolatile semiconductor memory device,
Even at the time of data reading, the number of erasures between erase blocks can be easily leveled.

[0014] Preferably, the address conversion table is divided into a plurality of sub-address conversion tables. The first selecting means further selects a sub address conversion table including a first erase block. When the number of erasures stored in the first erasure block exceeds a predetermined number of erasures, the second selection unit refers to the sub-address conversion table selected by the first selection unit to perform the second erasure. Select a block.

Preferably, an integral multiple of the storage capacity required for each of the sub-address conversion tables is equal to the storage capacity of each of the plurality of erase blocks.

According to still another aspect of the present invention, there is provided a nonvolatile semiconductor memory device comprising: a plurality of erase blocks; an address conversion table storage area; a first selecting means; a second selecting means; Means. Each of the plurality of erase blocks has a data storage area and an erase count storage area. The address conversion table storage area stores an address conversion table that associates a plurality of logical addresses with a plurality of erase blocks. The address conversion table is divided into a plurality of sub address conversion tables. The first selecting means selects a first erase block associated with a logical address given externally at the time of data writing from among a plurality of erase blocks, and a first sub-address conversion table including the first erase block. Select When the number of erasures stored in the first erasure block exceeds a predetermined number of erasures, the second selection means selects the second sub-address conversion table and refers to the second address conversion table to determine the second sub-address conversion table. 2 is selected. The replacement means writes the data stored in the second erase block to the first erase block when the number of erases stored in the second erase block does not exceed the predetermined number of erases, and writes the data from the outside. The data is written to the second erase block, the first erase block is associated with the logical address associated with the second erase block, and the second erase block is associated with the first erase block. Associated logical address.

In the above nonvolatile semiconductor memory device,
Since the second selecting means and the replacing means are provided, the leveling operation can be performed even when all of the erase blocks managed by the first sub-address conversion table approach the upper limit of the number of times of erasing of the nonvolatile memory. it can.

[0018]

Embodiments of the present invention will be described below in detail with reference to the drawings. In the drawings, the same or corresponding portions have the same reference characters allotted, and description thereof will not be repeated.

[First Embodiment] FIG. 1 is a block diagram showing an overall configuration of a semiconductor memory device according to a first embodiment of the present invention. Referring to FIG. 1, this semiconductor storage device 10
Are the host interface circuit 11 and the CPU circuit 1
2, a sequencer circuit 13, an ECC circuit 14, buffers 15a and 15b, a working buffer 16, a nonvolatile memory control circuit 17, and a nonvolatile memory 18.

The host interface circuit 11 exchanges address signals, data signals, and command signals with the host system 1 outside the semiconductor memory device 10. The CPU circuit 12 controls the semiconductor memory device 10. The sequencer circuit 13 manages data transfer. E
CC (Error Checking and Cor)
Recting) circuit 14 is provided to increase the reliability of data retention. The buffers 15a and 15b temporarily hold data during data transfer. The work buffer 16 is provided for reading an address conversion table described later. The nonvolatile memory control circuit 17 operates together with the sequencer circuit 13 when transferring data.
Is controlled. The nonvolatile memory 18 is a block erase type nonvolatile memory such as a flash memory. In a block erase type nonvolatile memory, a memory array is divided into several blocks, and an erase pulse application / erase verify is performed for each block. Here, it is divided into (M + 1) blocks BK (0) -BK (M), and each of the divided blocks is called an erase block. Here, a part of the erase blocks BK (0) -BK (M) is used as an address conversion table. The size of the buffers 15a and 15b is
It has the same size as the erase blocks BK (0) -BK (M).

FIG. 2 shows the erase block BK shown in FIG.
It is a figure which shows the internal structure of (2) -BK (M). Referring to FIG. 2, erase blocks BK (2) -BK (M) include a data storage area 21, an erase count storage area 22, an ECC
And a storage area 23. Data sent from the host system 1 is stored in the data storage area 21. Erased blocks BKi (i = 2)
−M) is stored. The ECC storage area 23 stores data added by the ECC circuit 14.

All data transfer operations in the semiconductor memory device 10 shown in FIG. 1 are performed by the CPU circuit 12 controlling the sequencer circuit 13 and the nonvolatile memory control circuit 17. The sequencer circuit 13 generates various internal waveforms necessary for data transfer, and the nonvolatile memory control circuit 17 generates a control signal for the nonvolatile memory 18 based on the erase block number given from the CPU circuit 12.

Next, an outline of the operation of reading data from the nonvolatile memory 18 will be described. First, information is provided from the host system 1 to the host interface circuit 11. Based on this information, the CPU circuit 12 controls the sequencer circuit 13 and the non-volatile memory control circuit 17 to generate a waveform necessary for reading data. As a result, data is read from the nonvolatile memory 18 to the buffer 15a. Thereafter, based on the waveform generated by the sequencer circuit 13, the data is transferred from the buffer 15a to the host system 1 through the host interface circuit 11. When data is transferred from the nonvolatile memory 18 to the buffer 15a, the read data is simultaneously decoded by the ECC circuit 14. When an error occurs in the data, the error information is sent to the CPU circuit 12 through the sequencer circuit 13, and the data in the buffer 15a is corrected. This error correction may be performed by software using the CPU circuit 12, or may be performed by hardware with error correction dedicated hardware mounted inside the semiconductor memory device.

Next, an outline of an operation of writing data to the nonvolatile memory 18 will be described. In writing data to the non-volatile memory 18, as in the case of reading data, the CPU
The circuit 12 controls the sequencer circuit 13 to generate a waveform required for writing data. As a result, the data is stored in the buffer 15a through the host interface circuit 11. Thereafter, the CPU circuit 12 controls the sequencer circuit 13 to transfer the data in the buffer 15a to the ECC circuit 14, and performs an encoding process. The data in the buffer 15 after the processing is transferred to the ECC circuit 14 to perform an encoding process. The data in the buffer 15a after the processing is
Based on the waveforms generated by the sequencer circuit 13 and the nonvolatile memory control circuit 17, the data is written to the erase block of the nonvolatile memory 18.

At the time of data transfer, a command signal indicating a data transfer request from the host system 1, CHS (Cyl)
inner Head Sector) and LBA (Lo
An address signal such as a physical block address (logical block address) and a data signal to be transferred are provided to the storage device. These pieces of information are both written into a register provided in the host interface circuit 11, and the CPU circuit 12 determines the contents.

In the nonvolatile semiconductor memory device according to the first embodiment, an address conversion table is stored in erase blocks BK (0) and BK (1). The logical address given from the host system 1 at the time of data writing / reading and the like and the erase blocks BK (2) -BK (M) of the nonvolatile memory 18 are associated with each other by the address conversion table.

FIG. 3 is a conceptual diagram of the address conversion table. Referring to FIG. 3, the address conversion table stores the erase block number of the nonvolatile memory corresponding to the logical address given from the host system. Note that the information to be stored may be any information that can calculate the number of the erase block corresponding to the logical address given from the host system 1.

Here, the read unit is 512-byte data, which is one sector. Also, a group of four consecutive sectors is defined as one cluster, and the storage capacity of the erase block is set to 2048 bytes. Further, the read unit for the work buffer 16 is 512 bytes, the data length of the erase block number stored in the address conversion table is 2 bytes, and the unit of the erase block is 2048 bytes. That is, the address conversion table is divided into sub-address conversion tables for every 512 bytes, which is a unit of reading into the working buffer 16. Four sub-address conversion tables are stored in one erase block.

The size of the address conversion table changes depending on the information to be stored. The address conversion table is stored in the nonvolatile memory 18 and refers to a corresponding 512-byte sub-address conversion table at the time of data transfer.

For example, a case where a logical sector address 5002 is given from the host system 1 will be described.

The logical sector address is converted to a logical cluster address (5002/4 = 1250 remainder 2). Here, the quotient 1250 is the logical cluster address, and the remaining 2 is the offset of the sector included in the cluster.

It is calculated in which erase block the corresponding sub-address conversion table is stored (125).
0 ÷ 1024 = 1 remainder 226). Here, the quotient 1 is the erase block number in which the corresponding sub address conversion table is stored, and the remainder 226 is the offset in the erase block of the corresponding sub address conversion table.

The corresponding sub-address conversion table in the erase block calculated above is calculated (226 ÷ 2).
56 = 0 remainder 226). The quotient 0 is 0 in the erase block.
This indicates that 512-byte data of up to 511 bytes is the corresponding sub-address conversion table, and the remaining 226 indicates the offset in the 512-byte table to be read. When the quotient is 1, 512 to 1 in the erase block.
The corresponding sub address conversion table is read out from 512 bytes up to 023 bytes. The same applies when the quotient is a few.

As described above, the sub-address conversion table read out to the work buffer corresponding to the logical address from the host system 1 is specified.

Next, leveling of the number of erasures by the nonvolatile semiconductor memory device according to the first embodiment will be described.

FIG. 4 is a flowchart showing the procedure for leveling the number of erasures during data writing. Referring to FIG. 4, steps S1-S9 are a flow of a normal writing process, and steps S10-S19 are a flow of an erasing frequency equalization.

First, in step S1, a write command and a logical address from the host system 1 are received. The write command and the logical address are written to a register prepared in the host interface circuit 11.

Next, in step S2, write data from the host system 1 is received through the host interface circuit 11.

Next, in step S3, step S
The sub-address conversion table necessary for converting the logical address (here, X) received at 1 into the erase block number (here, X ') of the nonvolatile memory 18 is converted from the nonvolatile memory 18 to the working buffer 16. Read out.

Next, in step S4, step S
The erase block X 'corresponding to the logical address X is obtained by using the sub address conversion table read in step 3. Here, the number of logical addresses stored in the read sub-address conversion table is represented by Y (0 to Y-
1) and the offset x in the subaddress conversion table
It is assumed that the erase block number X 'corresponding to the logical address X is stored in (x is 0 to Y-1).

Next, in step S5, the number of erases of the erase block X 'is stored in the buffer 15 from the nonvolatile memory 18.
Read to a.

Next, in step S6, it is determined whether or not the number of erasures is below a certain value (for example, the upper limit of the number of erasures of the nonvolatile memory 18). If it is below, the process proceeds to step S7; otherwise, the process proceeds to step S10.

If the number of erasures is below a certain value, it is considered that writing is possible, and the erasure block X 'is erased in step S9.

Next, in step S7, step S
The value obtained by adding 1 to the number of erasures obtained in 5 is stored in the buffer 15a.
And the data in the buffer 15a is encoded using the ECC circuit 14.

Next, in step S8, the buffer 1
The data stored inside 5a is written into the erase block X 'of the nonvolatile memory 18, and the process is terminated.

If it is determined in step S6 that the number of erasures is not less than the predetermined value, the number of erasures is leveled.
That is, when it is determined that leveling is necessary based on the number of erasures read in step S5 (for example, the number of erasures / writes exceeds the upper limit of the number of erasures of the erasure block by several erasures).

First, in step S10, an erase block Z 'to which data is to be exchanged is determined by using the offset x of the sub-address conversion table storing the value of the erase block X'. The offset z in the sub-address conversion table in which the value of the replacement destination erase block Z 'is stored is calculated using f (x, Y). For example,
z = f (x, Y) = (x + 1)% Y. % Is the remainder calculation.

Next, in step S11, the number of erases stored in the erase block Z 'is read out to the buffer 15b.

Next, in step S12, it is determined whether or not the number of erasures read out to the buffer 15b is below a certain value. If less than, step S13
If not, return to step S10,
Steps S10 and S11 are repeated.

Next, in step S13, the data stored in the erase block Z 'is read out to the buffer 15b.

Next, in step S14, erase blocks X 'and Z' are erased. Next, in step S15, data in the buffers 15a and 15b is processed. Buffers 15a, 15b
To the buffer 15a, using the ECC circuit 14.
Encode the data in 15b.

Next, in step S16, the number of the erase block Z 'is stored in the offset x of the sub-address conversion table read into the working buffer 16, and the number of the erase block X' is stored in the offset z, thereby deleting the erase block X. 'And Z' are exchanged.

Next, in step S17, the data stored in the buffer 15a is written to the erase block Z '.

Next, in step S18, the data stored in the buffer 15b is written to the erase block X '.

Next, the sub-address conversion table read into the working buffer 16 is written into the nonvolatile memory 18.

As described above, the number of erasures is leveled. By using the sub-address conversion table, the CPU circuit 12 can freely write data in a desired erase block in the nonvolatile memory 18 without being bound by the logical address number given from the host system 1.

Generally, the address conversion table is always read out to the work buffer 16 before the data transfer work.
For example, in the embodiment shown in U.S. Pat. No. 5,388,083, information necessary for address translation is dispersed and stored in all erase blocks, and the address translation data in all erase blocks is read out to the work buffer once. A method of constructing an address conversion table is described. In this case, it takes a considerable amount of time to construct the address conversion table, but once the address conversion table is created, the performance of the address conversion during data transfer is the fastest.

In the first embodiment, the address conversion table is centrally managed and stored in the non-volatile memory, and the sub-address conversion table necessary for the address conversion is read out to the work buffer 16 at the time of data transfer. The read size is the minimum erase size of the erase block in the nonvolatile memory 18. This eliminates the need to search all erased blocks to create an address conversion table, and to reduce the capacity of the work buffer 16.

On the other hand, an overhead of transferring the sub address conversion table from the nonvolatile memory 18 to the work buffer 16 is always added at the time of address conversion. However, this overhead can be performed during data transfer from the host system 1 to the buffers 15a and 15b when writing data. Further, once the address conversion table is read into the work buffer 16 regardless of data read / write, rereading is not performed while the read sub-address conversion table corresponds to the logical address requested by the host system 1. Help me. Therefore, this overhead can be very small. The reason why only the minimum erase size is read out is that it is convenient for leveling the number of erases between erase blocks.

In step S10, the offset z in the sub-address conversion table storing the value of the erase block Z 'is z = f (x, Y) = (x + 1)% Y
Calculated by However, when a large-scale FAT is used, a plurality of nonvolatile memory erase blocks are allocated to the FAT. In this case, since there is a very high possibility that an adjacent erase block is also a FAT, when an erase block Z ′ having a writable erase count is searched using z = (x + 1)% Y, replacement is possible. It can be imagined that it takes a considerable amount of time to find a proper erase block. For this reason, f (x,
Y), for example, z = f (x, Y) = (x + Y / 2−
1) Using% Y or the like reduces the time required for searching,
The bias in the number of times of erasure of the erase block is also eliminated to z = (X + 1)% Y or more.

[Second Embodiment] In the first embodiment, the leveling process at the timing of data writing has been described. However, the leveling process can also be performed at the time of data reading.
FIG. 5 is a flowchart showing a procedure for leveling the number of erasures during data reading. Hereinafter, description will be made with reference to FIG.

First, in step S21, a data read command and a logical address from the host system 1 are received. The read command and the logical address are written to a register prepared in the host interface circuit 11.

Next, in step S22, a sub-address conversion table necessary for converting the logical address X received in step S1 into the erase block number X 'of the nonvolatile memory 18 is read from the nonvolatile memory 18 to the working buffer 16.

Next, in step S23, an erase block X 'corresponding to the logical address X is obtained by using the read sub-address conversion table. Here, as in the first embodiment, the number of logical addresses stored in the sub-address conversion table read at one time is represented by Y (0
To Y-1), and the erase block number X 'corresponding to the logical address X is stored at the offset x (X is 0 to Y-1) in the sub-address conversion table.

Next, in step S24, the number of erases of the erase block X 'is counted from the nonvolatile memory to the buffer 15a.
Read out.

Next, in step S25, if the number of erasures is below a certain value (for example, the upper limit of the number of erasures of the nonvolatile memory 18), there is no problem, and the process proceeds to step S36. 15a is transferred to the host system 1;
The process ends.

If it is determined in step S25 that the number of erasures does not fall below a certain value, steps S26 to S35 are performed.
Leveling process is performed. Step S26-S35
Is the same as the processing in steps S10 to S19 shown in FIG.

As described above, according to the second embodiment, the leveling process can be performed at the time of data reading.

Here, whether or not the leveling is necessary is determined based on the number of erasures of the read erasure block (step S25).
May be used as a trigger when a data error is found. In this case, leveling does not occur as frequently as the former.

[Embodiment 3] Although Embodiments 1 and 2 can be used to equalize the number of erasures, all the erasure blocks managed by the sub-address conversion table that are read out at a time can reduce the number of erasures of the nonvolatile memory. When approaching the upper limit, leveling work cannot be performed.

The third embodiment aims to avoid this problem. The nonvolatile semiconductor memory device according to the third embodiment further includes, in addition to the configuration shown in FIG.
A second working buffer is provided. The second working buffer has the same capacity as the working buffer 16.

FIG. 6 is a flowchart showing a procedure for leveling the number of erasures during data writing according to the third embodiment. Hereinafter, the procedure for leveling the number of erasures will be described with reference to FIG.

In steps S1-S9, the same processing as that shown in FIG. 4 is performed. The main difference from the first embodiment is that when it is determined in step S6 that leveling is necessary, in step S50, the sub-address conversion table B not related to data writing from the host system 1 Read out to the buffer for The selection of the sub-address conversion table B may be calculated by B = (A + 1)% C, as in the method of specifying the erase block. C is a quotient obtained by dividing the total address conversion table by the readout size Y to the working buffer 16.

Then, in step S51, an erase block Z 'to which data is to be replaced is determined in the sub-address conversion table B. The determination method is the same as in step S10 in FIG.
Is the same as

Hereinafter, in steps S51-S59,
The same processing as in steps S11 to S18 shown in FIG. 4 is performed.

Next, in steps S60 and S61,
The work buffer 16 stores the sub-address conversion tables A and B stored in the second work buffer in the nonvolatile memory 18.
Write to.

As described above, according to the third embodiment, the leveling operation can be performed even when all of the erase blocks managed by one sub-address conversion table approach the upper limit of the number of times of erasing of the nonvolatile memory. Can be.

Further, by using the leveling of the first embodiment together, it is possible to level the erasing frequency in a wider range.

Here, in step S50, the selection of the sub-address conversion table B is performed as follows: B = (A +
1) Calculated with% C, but can also be calculated with B = (A + C / 2-1)% C.

The embodiments disclosed this time are to be considered in all respects as illustrative and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[0081]

According to one aspect of the present invention, there is provided a nonvolatile semiconductor memory device including a plurality of erase blocks, an address conversion table storage area, first selection means, second selection means, Since the means is provided, the number of erasures between erase blocks can be easily leveled without requiring complicated processing.

Further, the address conversion table is divided into a plurality of sub address conversion tables, the first selecting means further selects a sub address conversion table including the first erase block, and the second selecting means selects the first sub address conversion table. When the number of erases stored in the erase block exceeds the predetermined number of erases, the second erase block is selected with reference to the sub-address conversion table selected by the first selecting means. , The number of times of erasure between erase blocks can be leveled more easily than in the case of referring to.

A nonvolatile semiconductor memory device according to another aspect of the present invention includes a plurality of erase blocks, an address conversion table storage area, a first selection unit, a second selection unit, and a replacement unit. Is provided, the number of erasures between erase blocks can be easily leveled even during data reading.

According to still another aspect of the present invention, there is provided a nonvolatile semiconductor memory device comprising: a plurality of erase blocks; an address conversion table storage area; a first selecting means; a second selecting means; Since the means is provided, the leveling operation can be performed even when all of the erase blocks managed by the first sub-address conversion table approach the upper limit of the number of times of erasing of the nonvolatile memory.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing an internal configuration of an erase block shown in FIG.

FIG. 3 is a conceptual diagram of an address conversion table.

FIG. 4 is a flowchart showing a procedure for leveling the number of erasures during data writing according to the first embodiment;

FIG. 5 is a flowchart showing a procedure for leveling the number of erasures during data reading according to the second embodiment;

FIG. 6 is a flowchart showing a procedure for leveling the number of erasures during data writing according to the third embodiment.

[Explanation of symbols]

11 Host interface circuit, 12 CPU circuit, 13 Sequencer circuit, 14 ECC circuit, 15
a, 15b buffer, 16 working buffer, 17
Non-volatile memory control circuit, 18 Non-volatile memory, BK
(0) -BK (M) Erase block.

Claims (7)

[Claims] 1. An address conversion table storage area for storing a plurality of erase blocks each having a data storage area and an erase count storage area, and an address conversion table in which a plurality of logical addresses are associated with the plurality of erase blocks. First selecting means for selecting a first erase block associated with a logical address given externally during data writing from the plurality of erase blocks with reference to the address conversion table; A second selection step of selecting a second erase block from the plurality of erase blocks by referring to the address conversion table when the erase count stored in one erase block exceeds a predetermined erase count; Means, when the erase count stored in the second erase block does not exceed the predetermined erase count, the second erase block. The data stored in the memory is written to the first erase block, externally written data is written to the second erase block, and the first erase block is associated with the second erase block. A non-volatile semiconductor storage device, comprising: a replacement unit that associates the second erase block with the logical address that the first erase block is associated with. 2. The address conversion table is divided into a plurality of sub-address conversion tables, the first selection unit further selects a sub-address conversion table including the first erase block, and the second selection unit Selecting the second erase block by referring to a sub-address conversion table selected by the first selecting means when the number of erases stored in the first erase block exceeds a predetermined number of erases Do
The nonvolatile semiconductor memory device according to claim 1. 3. The nonvolatile semiconductor memory device according to claim 2, wherein an integral multiple of a storage capacity required for each of said sub-address conversion tables is equal to a storage capacity of each of said plurality of erase blocks. 4. An address conversion table storage area for storing a plurality of erase blocks each having a data storage area and an erase count storage area, and an address conversion table in which a plurality of logical addresses are associated with the plurality of erase blocks. First selecting means for selecting a first erase block associated with a logical address given externally when reading data from the plurality of erase blocks by referring to the address conversion table; A second selection step of selecting a second erase block from the plurality of erase blocks by referring to the address conversion table when the erase count stored in one erase block exceeds a predetermined erase count; Means, when the number of erases stored in the second erase block does not exceed the predetermined number of erases, the first erase block. Swapping the data stored in the second erase block with the data stored in the second erase block, and associating the first erase block with a logical address to which the second erase block was associated; A non-volatile semiconductor memory device, comprising: a replacement unit for associating the second erase block with a logical address associated with the first erase block. 5. The address conversion table is divided into a plurality of sub-address conversion tables, the first selection unit further selects a sub-address conversion table including the first erase block, and the second selection unit Selecting the second erase block by referring to a sub-address conversion table selected by the first selecting means when the number of erases stored in the first erase block exceeds a predetermined number of erases Do
The nonvolatile semiconductor memory device according to claim 4. 6. The nonvolatile semiconductor memory device according to claim 5, wherein an integral multiple of a storage capacity required for each of said sub-address conversion tables is equal to a storage capacity of each of said plurality of erase blocks. 7. A non-volatile semiconductor memory device, comprising: a plurality of erase blocks each having a data storage area and an erase count storage area; and address conversion in which a plurality of logical addresses are associated with the plurality of erase blocks. An address conversion table storage area for storing a table, wherein the address conversion table is divided into a plurality of sub-address conversion tables, and the nonvolatile semiconductor memory device further externally supplies data from among the plurality of erase blocks when writing data. First selecting means for selecting a first erase block associated with a logical address to be selected and selecting a first sub-address conversion table including the first erase block; and a first selection block stored in the first erase block. When the number of erasures exceeds a predetermined number of erasures, the second sub-address conversion table is selected. And second selecting means for selecting a second erase block by referring to a second address conversion table; and when the number of erases stored in the second erase block does not exceed the predetermined number of erases, Writing data stored in the second erase block to the first erase block, writing externally written data to the second erase block, and writing the first erase block to the second erase block. A non-volatile semiconductor storage device, comprising: a replacement unit that associates the second erase block with the logical address associated with the first erase block.