JP2000244585A - Bus interface circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To transmit data which are transmitted through plural buses by plural IO cards, to a processor in the order of data arrival time. SOLUTION: A setting circuit 16 sets time when data are stored in a reception buffer 14 storing data transmitted by an IO card 5. In this case, when a selector circuit 12 selects the reception buffer 14, according to the time set to the reception buffer 14, the reception buffer 14 having the oldest time is selected and a selector 13 sends data corresponding to the oldest time in the reception buffer 14 selected by the selector circuit 12 to an input/output buffer 11.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a bus interface circuit for controlling transmission and reception of data between an IO device and a processor.

[0002]

2. Description of the Related Art FIG. 9 is a block diagram showing a local area network disclosed in, for example, Japanese Patent Application Laid-Open No. 61-212138. For example, a plurality of cards for transmitting and receiving messages and data are interconnected via a multiplex bus system. It is connected to the.

The local area network comprises a multiplex bus system 100 and an interface module 10
5, subsystem 106, and protocol converter 1
17 The multiplex bus system 100 includes bus lines 102, 103, and 104. The interface module 105 includes three bus adapters 11.
0, 111 and 112, and bus adapters 110 and 11
It comprises bus taps 107, 108 and 109 necessary for connecting 1, 112 to the multiplex bus system 100, a distribution unit 115 operating as a control unit, a host interface unit 116, and a local bus line 114 connecting these. . Further, the protocol converter 117 includes a processor 118, a host memory 119, and an input / output interface 120, all of which are connected to the host bus line 121.

Next, the operation will be described. When the subsystem 106 transmits a message according to the protocol of the multiple bus system 100, the host interface 1
Instructs the distribution unit 115 to transmit a message via 16. The distribution unit 115 includes the subsystem 10
6, the message data is read from within the subsystem 106, and the bus adapter 110,
Transfer to one of 111 and 112. Bus adapter 1
10, 111 and 112 transmit the data transferred from the distribution unit 115 via the bus lines 102, 103 and 104.

If the protocol of the subsystem 106 does not match the protocol of the multiplex bus system 100, the protocol converter 117 converts the protocol of the message data in the subsystem 106. The distribution unit 115 performs similar processing on the converted data. The bus adapters 110, 111, and 112 have a built-in control unit, arbitration device, and storage device.
After autonomously receiving the data from 2, 103 and 104 and acquiring the right to use the local bus line 114, the data is transferred to the subsystem 106 via the host interface 116.

[0006]

As described above,
The conventional interface module has a problem that the received data cannot be controlled to be transferred in accordance with the arrival time and priority of the data.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems. By controlling the transfer of received data, the communication between an IO device and a processor via a plurality of buses is achieved. It is an object of the present invention to obtain a bus interface circuit capable of improving the performance of a system for transmitting and receiving data.

[0008]

According to a first aspect of the present invention, a plurality of input means are connected to a plurality of peripheral devices via a bus, and each of the plurality of input devices receives transmission information transmitted to the processor by the plurality of peripheral devices. Each of the plurality of peripheral devices, wherein the transmission information received by the plurality of input means is stored, and a time at which the transmission information is stored is set corresponding to the stored transmission information. A plurality of reception buffers, a plurality of setting means corresponding to each of the plurality of reception buffers for setting the time in the plurality of reception buffers, and a predetermined selection of transmission information stored in the reception buffers. A selection means for selecting based on a reference, and a selector for transmitting the selected transmission information to the processor.

According to a second aspect, when the transmission information exists in the plurality of reception buffers, the transmission information having the oldest time set is selected based on the time set corresponding to the transmission information. Selection means to perform the selection.

[0010] A third invention comprises a plurality of counters each of which sets the number of the transmission information transmitted by the plurality of peripheral devices, and wherein the plurality of setting means each set the number of the transmission information to the plurality of transmission information. And the selecting means selects the transmission information stored in the reception buffer corresponding to the counter having the largest number of the transmission information.

According to a fourth aspect of the present invention, there is provided a register in which the priorities of the plurality of peripheral devices are written in advance by the processor, and the selecting means is configured to output the plurality of peripheral devices when the transmission information exists in the plurality of reception buffers. The transmission information of the reception buffer in which the transmission information of the peripheral device having the highest priority is stored is selected based on the priority written in the register.

According to a fifth aspect of the present invention, transmission information transmitted to a plurality of peripheral devices by a plurality of processors is stored, and a time at which the transmission information is stored corresponds to the stored transmission information. A plurality of transmission buffers respectively corresponding to the plurality of peripheral devices to be set, and a plurality of processor setting means corresponding to each of the plurality of transmission buffers respectively setting the time in the plurality of transmission buffers, The information that specifies the peripheral device that is the transmission destination of the transmission information is a table in which the plurality of processors write the transmission information before the transmission information is transmitted, and the transmission information stored in the transmission buffer is determined by a predetermined selection criterion. Processor selection means for selecting based on
A processor selector for transmitting the selected transmission information, connected to the plurality of peripheral devices via a bus, receiving the transmission information transmitted by the processor selector, and transmitting the received transmission information to the Output means for transmitting to the specified peripheral device based on the information written in the table.

According to a sixth aspect, when the transmission information exists in the plurality of transmission buffers, the transmission information having the oldest time set is selected based on the time set corresponding to the transmission information. And a processor selecting means.

A seventh invention comprises a plurality of processor counters each of which sets the number of the transmission information transmitted by the plurality of processors, wherein the plurality of processor setting means keeps the number of the transmission information. Each of the plurality of processor counters is set, and the plurality of processor selection means selects transmission information stored in a transmission buffer corresponding to the processor counter having the largest number of transmission information.

According to an eighth aspect of the present invention, there is provided a processor register in which the priorities of the plurality of processors are written in advance by the plurality of processors, wherein the processor selecting means stores the transmission information in the plurality of transmission buffers. When it exists, the transmission information of the transmission buffer storing the transmission information of the processor with the highest priority is selected based on the priority written in the processor register.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a block diagram showing a system configuration of a first embodiment. In the figure, 1 is a CPU card for controlling the system, 5 is a CPU
These are a plurality of IO cards that control an IO device (peripheral device) in accordance with an instruction from the card 1. The CPU card 1 includes a processor 2 for performing calculations, a memory 3 for storing data for calculations, and a bus interface circuit 4 for controlling transmission and reception of data between the CPU card 1 and the IO card 5 via a plurality of buses. Consists of

FIG. 2 is a configuration diagram of the bus interface circuit according to the first embodiment. In the figure, the same reference numerals as those in FIG. 1 indicate the same or corresponding parts. 11 is an input / output buffer for transmitting or receiving data, 12 is for selecting the receiving buffer 14 in accordance with the time information stored in the receiving buffer 14, and further instructing the selector 13 to transmit the data stored in the selected receiving buffer 14. Selection circuit for giving instructions, 13
Is a selector for sending data stored in the reception buffer 14 to the input / output buffer 11 in accordance with an instruction from the selection circuit 12.
Numeral 14 stores the data transmitted by the corresponding IO card 5 and the address of the transmission destination, and the time when the data and the address are stored, that is, a reception buffer in which time information is set, and 15 is a timer for measuring the time. , 16 are timers 15
This is a setting circuit for setting the time measured in the reception buffer 14 as time information.

Reference numeral 17 denotes an input / output buffer for transmitting or receiving data, and reference numeral 18 denotes an IO card 5 by the processor 2.
A transmission buffer for storing the data to be transmitted to the transmission buffer and the address of the transmission destination of the data. Reference numeral 19 denotes an address stored in the transmission buffer 18 and the address written in the table 21 and the correspondence between the IO card 5 and the data. A selection circuit for selecting a transmission destination and further instructing the selector 20 to transmit the data stored in the transmission buffer 18 to the selected transmission destination. The selection circuit 20 stores the data in the transmission buffer 18 according to the instruction from the selection circuit 19. A selector for sending the input data to the input / output buffer 17 corresponding to the destination selected by the selection circuit 19;
This is a table in which the correspondence of the card 5 is written.

Next, the operation will be described. First, C
An operation of transferring data from the PU card 1 to the IO card 5 via a plurality of buses will be described. First, before starting the transfer, the processor 2 writes the correspondence between the destination address and the IO card 5 in the table 21. The processor 2 executes a task (read / write of data) to the IO card 5. Upon receiving the data transmitted by the processor 2 and the address of the transmission destination, the bus interface circuit 4 transmits the data to the transmission buffer 18 via the input / output buffer 11 under the control of the protocol control circuit (not shown). Stores the previous address.

The selection circuit 19 determines the destination IO from the address stored in the transmission buffer 18 and the correspondence between the address written in the table 21 and the IO card 5.
The card 5 is selected, and an instruction for transmitting data to the selector 20 is issued. The selector 20 transmits the data stored in the transmission buffer 18 to the input / output buffer 17 corresponding to the IO card 5 selected by the selection circuit 19 according to the instruction of the selection circuit 19. Transmission of data to the IO card 5 is executed under the control of a protocol control circuit (not shown).

Next, the operation of transferring data from the IO card 5 to the CPU card 1 via a plurality of buses will be described. Upon receiving the data transmitted by the IO card 5 and the address of the transmission destination, the bus interface circuit 4 responds to the IO card 5 via the input / output buffer 17 under the control of a protocol control circuit (not shown). The data and the address of the transmission destination are stored in the reception buffer 14. At the same time, the setting circuit 16 refers to the timer 15 and
The time information is set in the reception buffer 14.

The selection circuit 12 monitors the emptyity of the reception buffer 14, selects a non-empty reception buffer 14, and instructs the selector 13 to transmit the data stored in the selected reception buffer 14. If the plurality of reception buffers 14 are not empty, the reception buffer 14 having the oldest time information is selected with reference to the time information of the reception buffer 14, and the oldest time information in the selected reception buffer 14 is selected. The selector 13 is instructed to transmit data corresponding to. Selector 1
3 sends the data stored in the selected reception buffer 14 to the input / output buffer 11 in accordance with the instruction of the selection circuit 12.

As described above, according to the present embodiment, when the bus interface circuit 4 receives data from the IO card 5, the setting circuit 16 sets time information in the reception buffer 14, and the selection circuit 12 sets the time information in the reception buffer 14. According to the time information set in the reception buffer 14 at the time of selection, the reception buffer 14 having the oldest time information is selected, and the selector 13 selects the reception buffer 14 selected by the selection circuit 12.
Since the data corresponding to the oldest time information is sent to the input / output buffer 11, the data transmitted by the IO card 5 can be transferred to the processor in the order of the arrival time of the data. Thus, the performance of a system for transmitting and receiving data between a plurality of IO cards and the processor 2 can be improved. In the present embodiment, the IO
The case where three cards 5 are used has been described as an example.
The same effect can be exerted even if is increased or decreased. This is the same in the following embodiments.

Second Embodiment FIG. 3 is a configuration diagram of a bus interface circuit according to a second embodiment. In the figure, the figure
The same reference numerals as 1 and 2 indicate the same or corresponding parts. 31 selects the reception buffer 34 according to the value of the counter 33,
A selection circuit for instructing the selector 32 to transmit the data stored in the selected reception buffer 34;
Reference numeral 2 denotes a selector for sending data stored in the reception buffer 34 to the input / output buffer 11 in accordance with an instruction from the selection circuit 31. Reference numeral 33 denotes the number of access requests from the IO card 5 to the reception buffer 34, that is, the number of requests transmitted from the IO card 5. This is a counter corresponding to each of the reception buffers 34 that stores the number of data and addresses stored in the reception buffer 34.

Reference numeral 34 denotes a reception buffer for storing data transmitted by the corresponding IO card 5 and a destination address, and reference numeral 35 denotes a reception buffer from the corresponding IO card 5.
Is a setting circuit that sets the number of access requests to the counter 33 to the counter 33.

Next, the operation will be described. The operation of transferring data from the CPU card 1 to the IO card 5 via a plurality of buses is the same as in the first embodiment. An operation of transferring data from the IO card 5 to the CPU card 1 via a plurality of buses will be described. First, when the bus interface circuit 4 receives the data transmitted by the IO card 5 and the destination address, the protocol control circuit
Under the control of (not shown), via the input / output buffer 17,
The data and the address of the transmission destination are stored in the reception buffer 14 corresponding to the IO card 5. At the same time, setting circuit 3
5 is a receiving buffer 34 in which addresses and data are stored.
Is incremented by one.

The selection circuit 31 monitors the value of the counter 33, selects the reception buffer 34 having the largest value of the counter 33, and instructs the selector 32 to transmit the data stored in the selected reception buffer 34. Give instructions. At the same time, the value of the counter 33 corresponding to the selected reception buffer 34 is decremented by one. The selector 32
According to the instruction of the selection circuit 31, the selected reception buffer 3
4 is sent to the input / output buffer 11.

As described above, according to the present embodiment, when the bus interface circuit 4 receives data from the IO card 5, the setting circuit 35 sets the number of access requests to the reception buffer 34 in the counter 33 when receiving data. Then, the selection circuit 31 selects the reception buffer 34 having the largest value of the counter 33 when the buffer is selected, and the selector 32 sends the data stored in the reception buffer 34 selected by the selection circuit 31 to the input / output buffer 11. So
Data can be transferred according to the load on the IO card 5. That is, the data transfer of the IO card 5 that frequently requests the data transfer can be preferentially performed, and the data transfer can be performed according to the load of the plurality of IO cards 5. This can improve the performance of a system that transmits and receives data between a plurality of IO cards and the processor 2 via a plurality of buses.

Third Embodiment FIG. 4 is a configuration diagram of a bus interface circuit according to a third embodiment. In the figure, FIG.
The same reference numerals as those of to 3 denote the same or corresponding parts. Reference numeral 41 denotes a processing priority of each IO card 5, that is, a register in which the priority of each IO card 5 transmitting data and a destination address to the processor 2 is written, and reference numeral 42 denotes reception in accordance with the priority written in the register 41. Select buffer 34,
Further, a selection circuit for instructing the selector 32 to transmit the data stored in the selected reception buffer 34,
Reference numeral 3 denotes a selector for sending data stored in the reception buffer 34 to the input / output buffer 11 in accordance with an instruction from the selection circuit 42.

Next, the operation will be described. The operation of transferring data from the CPU card 1 to the IO card 5 via a plurality of buses is the same as in the first embodiment. The operation of transferring data from the IO card 5 to the CPU card 1 will be described. First, the processor 2 writes the processing priority of each IO card 5 into the register 41. The writing may be performed immediately after the system is started or during processing. Upon receiving the data transmitted by the IO card 5 and the address of the transmission destination, the bus interface circuit 4 responds to the IO card 5 via the input / output buffer 17 under the control of a protocol control circuit (not shown). The data and the address of the transmission destination are stored in the reception buffer 34.

The selection circuit 42 monitors the emptyity of the reception buffer 34, selects a non-empty reception buffer 34, and instructs the selector 32 to transmit the data stored in the selected reception buffer 34. If the plurality of reception buffers 34 are not empty, the processing priority written in the register 41 is referred to,
The receiving buffer 34 storing the data and the address from the IO card 5 having the highest processing priority is selected, and the selector 43 is instructed to transmit the data stored in the selected receiving buffer 34. The selector 43 includes the selection circuit 4
In accordance with the instruction 2, the data stored in the selected reception buffer 34 is sent to the input / output buffer 11.

As described above, according to the present embodiment, when the bus interface circuit 4 receives data from the IO card 5, the processor 2 writes the processing priority of each IO card 5 into the register 41, and the selection circuit 42 According to the processing priority written to the register 41 when the reception buffer 34 is selected, the reception buffer 34 storing the data and the address from the IO card 5 having the highest processing priority is selected, and the selector 43 selects the selection buffer 42. Since the data stored in the received buffer 34 is sent to the input / output buffer 11, the transmission information with a high transmission request sent by the IO card 5 can be sent to the processor 2 immediately, and Data from the critical IO card 5 can be transmitted with the highest priority, and data is transmitted with guaranteed response time. It can be.

Fourth Embodiment FIG. 5 is a block diagram showing a system configuration of a fourth embodiment. In the figures, FIGS.
The same reference numerals indicate the same or corresponding parts. Reference numeral 50 denotes a bus interface circuit that controls transmission and reception of data between the plurality of processors 2 and the plurality of IO cards 5.

FIG. 6 is a configuration diagram of the bus interface circuit according to the fourth embodiment. In the figures, the same reference numerals as those in FIGS. 1 to 5 indicate the same or corresponding parts. 61 is a setting circuit for setting the time measured by the timer 15 as time information in the transmission buffer 62, and 62 stores the data transmitted by the corresponding processor 2 and the address of the transmission destination, and stores the data and the address. The transmission buffer in which the time of day, that is, the time information is set, 63 selects the transmission buffer 62 according to the time information stored in the transmission buffer 62 and further selects the transmission of the data stored in the selected transmission buffer 62. A selection circuit for giving an instruction to 64, and a selector for sending the data stored in the transmission buffer 62 to the input / output buffer 17 according to the instruction of the selection circuit 63.

A selection circuit 65 selects the reception buffer 14 in accordance with the time information stored in the reception buffer 14, and instructs the selector 67 to transmit the data stored in the selected reception buffer 14, and 66. Is a register in which the processor 2 for transmitting the data stored in the reception buffer 14 is stored, and 67 is a selector for transmitting the data stored in the reception buffer 14 to the input / output buffer 11 in accordance with an instruction from the selection circuit 65.

Next, the operation will be described. First, C
An operation of transferring data from the PU card 1 to the IO card 5 via a plurality of buses will be described. First, before starting transmission, the processor 2 writes the correspondence between the transfer address and the IO card 5 in the table 21.

The processor 2 sends a task to the IO card 5
(Read / Write data). When the bus interface circuit 50 receives the data transmitted by the processor 2 and the address of the transmission destination, the bus interface circuit 50
(Not shown), via the input / output buffer 11,
The data and the address of the transmission destination are stored in the transmission buffer 62. At the same time, the setting circuit 61 sets time information in the transmission buffer 62 with reference to the timer 15.

The selection circuit 63 monitors the emptyity of the transmission buffer 62, selects a transmission buffer 62 that is not empty, and instructs the selector 64 to transmit the data stored in the selected transmission buffer 62. If the plurality of transmission buffers 62 are not empty, the transmission buffer 62 having the oldest time information is selected by referring to the time information of the transmission buffer 62, and the oldest time information in the selected transmission buffer 62 is selected. The selector 64 is instructed to transmit data corresponding to. Selector 2
0 transmits the data stored in the selected transmission buffer 62 to the input / output buffer 17 for the corresponding IO card 5 according to the instruction of the selection circuit 63. Data transmission with the IO card 5 is executed under the control of a protocol control circuit (not shown).

Next, the operation of transferring data from the IO card 5 to the CPU card 1 via a plurality of buses will be described. The bus interface circuit 50 is connected to the IO card 5
When the data and the destination address are received, the data and the destination address are stored in the reception buffer 14 corresponding to the IO card 5 via the input / output buffer 17 under the control of the protocol control circuit (not shown). Store the address. At the same time, the setting circuit 16 refers to the timer 15 and
The time information is set in the reception buffer 14.

The selection circuit 65 monitors the emptyity of the reception buffer 14, selects a non-empty reception buffer 14, and further stores the data stored in the selected reception buffer 14 into an input corresponding to the processor 2 stored in the register 66. Transmission to the output buffer 11 is performed by the selector 67.
Give instructions. Thereafter, the processor 2 stored in the register 66 is changed to indicate another processor 2.

When the plurality of reception buffers 14 are not empty, the reception buffer 14 having the oldest time information is selected by referring to the time information of the reception buffer 14, and the reception buffer 14 having the oldest time information is selected. The selector 67 is instructed to send data corresponding to the old time information to the input / output buffer 11 corresponding to the processor 2 stored in the register 66. Thereafter, the processor 2 stored in the register 66 is changed to indicate another processor 2.

The selector 67 sends the data stored in the selected reception buffer 14 to the input / output buffer 11 corresponding to the processor 2 stored in the register 66 in accordance with the instruction of the selection circuit 65. Note that, in addition to the present embodiment, as shown in the fifth and sixth embodiments, a configuration in which a transmission buffer is selected according to the number of access requests and the priority is also possible.

As described above, according to the present embodiment, when the bus interface circuit 4 receives data from the processor 2, the setting circuit 61 sets time information in the transmission buffer 62, and the selection circuit 63 sets the time information in the transmission buffer 62. According to the time information set in the transmission buffer 62 at the time of selection, the transmission buffer 62 having the oldest time information is selected, and the selector 64 selects the transmission buffer 62 selected by the selection circuit 63.
Since the data corresponding to the oldest time information is sent to the input / output buffer 17, the data transmitted by the processor 2 can be transferred to the IO card 5 in the order of arrival of the data.

The bus interface circuit 4 is connected to the IO
When data is received from the card 5, the setting circuit 16 sets time information in the reception buffer 14, and the selection circuit 65 holds the oldest time information according to the time information set in the reception buffer 14 when the reception buffer 14 is selected. The selected receiving buffer 14 is selected, and the selector 78 converts the data stored in the receiving buffer 34 selected by the selecting circuit 76 into a plurality of processors 2 based on the information stored in the register 66.
Therefore, the data transmitted by the IO card 5 can be evenly and efficiently transferred to the plurality of processors 2 in the order of arrival of the data. This can improve the performance of a system that transmits and receives data between a plurality of IO cards and a plurality of processors 2 via a plurality of buses.

Note that, in the present embodiment, two processors are used.
Although the number of processors has been described, the same effect can be obtained even if the number of processors further increases. This is the same in the following embodiments.

Fifth Embodiment FIG. 7 is a configuration diagram of a bus interface circuit according to a fifth embodiment. In the figure, FIG.
The same reference numerals as-6 indicate the same or corresponding parts. Reference numeral 71 denotes a setting circuit for setting the number of access requests from the corresponding processor 2 to the transmission buffer 73, that is, the number of data and addresses transmitted by the processor 2 to be stored in the transmission buffer 73, to the counter 72. This is a counter corresponding to each of the transmission buffers 73 that stores the number of access requests to the transmission buffer 73.

Reference numeral 73 denotes a transmission buffer for storing data to be transmitted to the IO card 5 by the corresponding processor 2 and an address of a transmission destination. Reference numeral 74 denotes a transmission buffer 73 according to the value of the counter 72, and further selects the selected transmission buffer 73. To transmit the data stored in the selector 75
Is a selector for sending the data stored in the transmission buffer 73 to the input / output buffer 17 in accordance with the instruction from the selection circuit 74.

A selection circuit 76 selects the reception buffer 34 in accordance with the number of access requests stored in the counter 33, and further instructs the selector 78 to transmit the data stored in the selected reception buffer 34. 77 Is a register in which the processor 2 for transmitting the data stored in the reception buffer 34 is stored, and 78 is a selector for transmitting the data stored in the reception buffer 34 to the input / output buffer 11 in accordance with an instruction from the selection circuit 76.

Next, the operation will be described. First, C
An operation of transferring data from the PU card 1 to the IO card 5 via a plurality of buses will be described. First, before starting the transfer, the processor 2 writes the correspondence between the transfer address and the IO card 5 in the table 21. The processor 2 executes a task (read / write of data) to the IO card 5. When receiving the data transmitted by the processor 2 and the address of the transmission destination, the bus interface circuit 50 transmits the data to the transmission buffer 73 via the input / output buffer 11 under the control of the protocol control circuit (not shown). Stores the previous address. At the same time,
The setting circuit 71 includes a counter 72 corresponding to the transmission buffer.
Is incremented by one.

The selection circuit 74 monitors the value of the counter 72, selects the transmission buffer 73 having the largest value of the counter 72, and instructs the selector 75 to transmit the data stored in the selected transmission buffer 73. Give instructions. At the same time, the value of the counter 72 corresponding to the selected transmission buffer 73 is decremented by one. The selector 75
According to the instruction of the selection circuit 74, the selected transmission buffer 7
3 is sent to the input / output buffer 17.

Next, the operation of transferring data from the IO card 5 to the CPU card 1 via a plurality of buses will be described. The bus interface circuit 50 is connected to the IO card 5
When the data and the destination address are received, the data and the destination address are stored in the reception buffer 14 corresponding to the IO card 5 via the input / output buffer 17 under the control of the protocol control circuit (not shown). Store the address. At the same time, the setting circuit 35 increments the value of the counter 33 corresponding to the reception buffer 34 by one.

The selection circuit 76 monitors the value of the counter 33, selects the reception buffer 34 having the largest value of the counter 33, and further stores the data stored in the selected reception buffer 34 in the processor 77 stored in the register 77. The transmission to the input / output buffer 11 corresponding to
Give instructions. At the same time, the selected receive buffer 3
The value of the counter 33 corresponding to 4 is decremented by one.
Further, the processor 2 stored in the register 77 is changed to indicate another processor 2. The selector 78
According to the instruction of the selection circuit 76, the selected reception buffer 3
4 is sent to the input / output buffer 11 corresponding to the processor 2 and stored in the register 77. Note that, in addition to the present embodiment, as shown in Embodiments 4 and 6, a configuration in which a transmission buffer is selected according to time or priority is also possible.

As described above, according to the present embodiment, when the bus interface circuit 4 receives data from the processor 2, the setting circuit 71 counts the number of access requests from the processor 2 when transmitting data from the processor 2 to the counter 72. And the selection circuit 74 selects the transmission buffer 73 in accordance with the value of the counter 72 when the buffer is selected, so that data can be transferred according to the load of the processor 2. That is, the processor 2 that frequently requests data transfer.
Can be preferentially performed, and the load on the processor 2 that frequently requests data transfer can be reduced.

The bus interface circuit 4 is connected to the IO
When data is received from the card 5, the setting circuit 35 sets the number of access requests to the reception buffer 34 in the counter 33 at the time of data reception, and the selection circuit 76 sets
Select the reception buffer 34 having the largest value of the counter 33, and the selector 78 stores the data stored in the reception buffer 34 selected by the selection circuit 76 in the register 7
7 is assigned equally to the plurality of processors 2 based on the information stored in the plurality of processors 2.
, And the data can be transferred according to the load on the IO card 5. That is, the data transfer of the IO card 5 that frequently requests data transfer can be preferentially performed, and the load on the IO card 5 that frequently requests data transfer can be reduced. This can improve the performance of a system that transmits and receives data between a plurality of IO cards and a plurality of processors 2 via a plurality of buses.

Embodiment 6 FIG. 8 is a configuration diagram of a bus interface circuit according to Embodiment 6. In the figure, FIG.
The same reference numerals as those of to 7 denote the same or corresponding parts. A transmission buffer 81 stores data transmitted to the IO card 5 by the corresponding processor 2 and a destination address.
The selector 82 selects the transmission buffer 81 in accordance with the processing priority written in the register 83, and further selects the transmission buffer 81 to transmit the data stored in the selected transmission buffer 81.
4, a register 83 in which the processing priority of each processor 2, that is, a priority in which each processor 2 transmits data and a destination address to the I / O card 5 is written, and 84 a selection circuit of the selection circuit 82. It is a selector that sends the data stored in the transmission buffer 81 to the input / output buffer 17 according to the instruction.

A selection circuit 85 selects the reception buffer 34 in accordance with the processing priority written in the register 41, and further instructs the selector 78 to transmit the data stored in the selected reception buffer 34. Processor 2 for transmitting data stored in reception buffer 34
Is a selector for sending the data stored in the reception buffer 34 to the input / output buffer 11 in accordance with the instruction of the selection circuit 85.

Next, the operation will be described. First CP
An operation of transferring data from the U card 1 to the IO card 5 via a plurality of buses will be described. First, before starting the transfer, the processor 2 writes the correspondence between the transfer address and the IO card 5 in the table 21, and further writes the processing priority of each processor 2 in the register 83. The writing may be performed immediately after the system is started or during processing. The processor 2 performs a task for the IO card 5
(Read / Write data).

When the bus interface circuit 50 receives the data transmitted by the processor 2 and the address of the transmission destination, the bus interface circuit 50 under the control of the protocol control circuit (not shown)
The data and the destination address are stored in the transmission buffer 81 via the input / output buffer 11.

The selection circuit 82 monitors the emptyity of the transmission buffer 81, selects a non-empty transmission buffer 81, and instructs the selector 84 to transmit the data stored in the selected transmission buffer 81. If the plurality of transmission buffers 81 are not empty, the processing priority written in the register 83 is referred to,
The transmission buffer 81 storing the data and the address from the processor 2 having the highest processing priority is selected, and the selector 84 is instructed to transmit the data stored in the selected transmission buffer 81. The selector 84 is connected to the selection circuit 8
In accordance with the instruction 2, the data stored in the selected transmission buffer 81 is sent to the input / output buffer 17.

Next, the operation of transferring data from the IO card 5 to the CPU card 1 via a plurality of buses will be described. The bus interface circuit 50 is connected to the IO card 5
When the data and the destination address are received, the data and the transmission destination are stored in the reception buffer 34 corresponding to the IO card 5 via the input / output buffer 17 under the control of the protocol control circuit (not shown). Store the address.

The selection circuit 85 monitors the emptyity of the reception buffer 34, selects a non-empty reception buffer 34, and instructs the selector 87 to transmit the data stored in the selected reception buffer 34. If the plurality of reception buffers 34 are not empty, the processing priority written in the register 41 is referred to,
The receiving buffer 34 storing the data and the address from the IO card 5 having the highest processing priority is selected, and the selector 87 is instructed to transmit the data stored in the selected receiving buffer 34.

After that, the processor 2 stored in the register 86 is changed to indicate another processor 2. The selector 87 sends the data stored in the selected reception buffer 34 to the input / output buffer 11 corresponding to the processor 2 stored in the register 86 according to the instruction of the selection circuit 85. As shown in Embodiments 4 and 5, a configuration in which a transmission buffer is selected according to time or the number of access requests is also possible.

As described above, according to the present embodiment, when the bus interface circuit 4 receives data from the processor 2, the processor 2 writes the processing priority of each processor 2 in the register 83, and the selection circuit 82 Since the transmission buffer 81 storing the data and the address from the processor 2 having the highest processing priority is selected according to the processing priority written in the register 83 at the time of selecting 81, the transmission buffer 81 transmits the data. Transmission information with a high transmission request can be sent to the IO card 5 immediately, data from the processor 2 that is critical on the system can be transmitted with the highest priority, and data can be transmitted with a guaranteed response time. it can.

The bus interface circuit 4 is connected to the IO
When data is received from the card 5, the processor 2 writes the processing priority of each IO card 5 into the register 41, and the selection circuit 85 operates when the reception buffer 34 is selected.
Of the IO card 5 having the highest processing priority is stored in the receiving buffer 34 stored in the receiving buffer 34 selected by the selection circuit 85. Since the data is evenly allocated to the plurality of processors 2 based on the information stored in the register 86, the data can be equally and efficiently transferred to the plurality of processors 2, and the transmission transmitted by the IO card 5 Highly requested transmission information can be sent to the processor 2 immediately, data from the system-critical IO card 5 can be transmitted with the highest priority, and data can be transmitted with a guaranteed response time. . As a result, a plurality of IOs via a plurality of buses
The performance of a system for transmitting and receiving data between the card and the plurality of processors 2 can be improved.

[0065]

Since the present invention is configured as described above, it has the following effects.

In the first invention, when transmission information is transmitted from a plurality of peripheral devices to a processor via a plurality of buses, the transmitted transmission information is stored in a plurality of reception buffers, and the stored transmission information is transmitted. Since information is selected and transmitted based on predetermined selection criteria, transmission information transmitted by a plurality of peripheral devices can be sent to a processor in various orders, and a plurality of peripheral devices and a processor can be transmitted via a plurality of buses. The performance of a system that transmits and receives data to and from the system can be improved.

In the second invention, when transmission information is transmitted to the processor by a plurality of peripheral devices via a plurality of buses, the transmitted transmission information is stored in a plurality of reception buffers, respectively, and the transmission information is further stored. The transmitted time is set corresponding to the transmission information, and the transmission information with the oldest time set among the times is selected and transmitted. Can be sent to

In the third invention, when transmission information is transmitted to the processor by a plurality of peripheral devices via a plurality of buses, the transmitted transmission information is stored in a plurality of reception buffers, respectively, and further transmitted transmission information is transmitted. Since the number of information is set in the counter and the transmission information stored in the reception buffer having the largest value of this counter is transmitted, the transmission information transmitted by the peripheral device having a large number of transmission requests can be transmitted with priority. This makes it possible to transmit transmission information according to the loads on a plurality of peripheral devices.

In the fourth invention, when the transmission information is transmitted to the processor by the plurality of peripheral devices via the plurality of buses, and the transmitted transmission information is stored in the plurality of reception buffers, the transmission information is written into the register. A reception buffer is selected based on the processing priority, and the transmission information stored in the selected reception buffer is transmitted. Therefore, transmission information from a peripheral device that is critical in the system can be transmitted with the highest priority.

In the fifth invention, when transmission information is transmitted by a plurality of processors, the transmitted transmission information is stored in a plurality of transmission buffers, respectively, and the stored transmission information is determined based on a predetermined selection criterion. Select and send to multiple peripherals over multiple buses, so that transmission information sent by multiple processors can be sent to peripherals in various orders, and multiple peripherals can be sent over multiple buses. Performance of a system for transmitting and receiving data between the processor and a plurality of processors can be improved.

In the sixth aspect, when transmission information is transmitted by a plurality of processors, the transmitted transmission information is stored in a plurality of transmission buffers, and the time at which the transmission information is stored corresponds to the transmission information. The transmission information with the oldest time set is selected from this time and transmitted to multiple peripheral devices via multiple buses, so the transmission information transmitted by multiple processors is arranged in the order of arrival. Can be sent to multiple peripheral devices.

In the seventh invention, when transmission information is transmitted by a plurality of processors, the transmitted transmission information is stored in a plurality of transmission buffers, respectively, and the number of transmitted transmission information is set in a counter. Since the transmission information stored in the transmission buffer having the largest value of this counter is transmitted to a plurality of peripheral devices via a plurality of buses, the transmission information transmitted by a processor with a large number of transmission requests is transmitted with priority. As a result, transmission information can be transmitted according to the loads of the plurality of processors.

In the eighth aspect, when transmission information is transmitted by a plurality of processors and the transmitted transmission information is stored in the plurality of transmission buffers, the transmission buffer is transmitted based on the processing priority written in the register. Is selected,
Since the transmission information stored in the selected transmission buffer is transmitted to a plurality of peripheral devices via a plurality of buses, transmission information from a processor critical in the system can be transmitted with the highest priority.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a system configuration according to a first embodiment.

FIG. 2 is a configuration diagram of a bus interface circuit according to the first embodiment.

FIG. 3 is a configuration diagram of a bus interface circuit according to a second embodiment.

FIG. 4 is a configuration diagram of a bus interface circuit according to a third embodiment.

FIG. 5 is a block diagram showing a system configuration according to a fourth embodiment.

FIG. 6 is a configuration diagram of a bus interface circuit according to a fourth embodiment.

FIG. 7 is a configuration diagram of a bus interface circuit according to a fifth embodiment.

FIG. 8 is a configuration diagram of a bus interface circuit according to a sixth embodiment.

FIG. 9 is a block diagram showing a conventional local area network.

[Explanation of symbols]

1 CPU card, 2 processors, 3 memories, 4
Bus interface circuit, 5 IO card, 11 input / output buffer, 12 selection circuit, 13 selector, 14
Receive buffer, 15 timer, 16 setting circuit, 17
Input / output buffer, 18 transmission buffer, 19 selection circuit, 20 selector, 21 table.

 ──────────────────────────────────────────────────続 き Continuing on the front page F term (reference)

Claims (8)

[Claims] A plurality of peripheral devices connected via a bus;
A plurality of input means for receiving transmission information transmitted to the processor by the plurality of peripheral devices, respectively; the transmission information received by the plurality of input means is stored, and the transmission information is stored. A plurality of reception buffers respectively corresponding to the plurality of peripheral devices whose times are set corresponding to the stored transmission information; and a plurality of reception buffers respectively setting the times in the plurality of reception buffers. A plurality of setting means respectively corresponding thereto; selecting means for selecting transmission information stored in the reception buffer based on a predetermined selection criterion; and a selector for transmitting the selected transmission information to the processor. A bus interface circuit. 2. When the transmission information is present in the plurality of reception buffers, the selection means selects the transmission information with the oldest time set based on the time set in correspondence with the transmission information. 2. The bus interface circuit according to claim 1, wherein said bus interface circuit is selected. A plurality of counters each of which sets the number of the transmission information transmitted by the plurality of peripheral devices, wherein the plurality of setting means sets the number of the transmission information to each of the plurality of counters. 2. The bus interface circuit according to claim 1, wherein said selection means selects transmission information stored in a reception buffer corresponding to a counter having the largest number of said transmission information. 4. The apparatus according to claim 1, further comprising a register in which the priority of the plurality of peripheral devices is written in advance by the processor, wherein the selection means writes the transmission information to the register when the transmission information exists in the plurality of reception buffers. 2. The bus interface circuit according to claim 1, wherein transmission information of a reception buffer storing transmission information of a peripheral device having the highest priority is selected based on the priority. 5. A transmission information transmitted by a plurality of processors to a plurality of peripheral devices is stored, and a time at which the transmission information is stored is set corresponding to the stored transmission information. A plurality of transmission buffers respectively corresponding to the plurality of peripheral devices; a plurality of processor setting means respectively corresponding to the plurality of transmission buffers for respectively setting the time in the plurality of transmission buffers; A table in which information for identifying a peripheral device as a transmission destination is written by the plurality of processors before the transmission information is transmitted, and transmission information stored in the transmission buffer are selected based on a predetermined selection criterion. A processor selector for transmitting the selected transmission information; and a processor selector for transmitting the selected transmission information. An output unit that is connected to the peripheral device, receives the transmission information transmitted by the processor selector, and transmits the received transmission information to the specified peripheral device based on the information written in the table. A bus interface circuit, comprising: 6. When the transmission information is present in the plurality of transmission buffers, the processor selecting means transmits the transmission time with the oldest time set based on the time set corresponding to the transmission information. 6. The bus interface circuit according to claim 5, wherein information is selected. 7. A plurality of processor counters, each of which sets the number of the transmission information transmitted by the plurality of processors, wherein the plurality of processor setting means respectively set the number of the transmission information to the plurality of transmission information. 6. A processor counter, wherein the plurality of processor selectors select transmission information stored in a transmission buffer corresponding to the processor counter having the largest number of transmission information. The bus interface circuit as described. 8. A processor register in which the priorities of the plurality of processors are written in advance by the plurality of processors, wherein the processor selecting means is configured to, when the transmission information exists in the plurality of transmission buffers, 6. The bus interface circuit according to claim 5, wherein transmission information of a transmission buffer storing transmission information of a processor having the highest priority is selected based on the priority written in the processor register.