JP2000100968A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the manufacture cost of a semiconductor integrated circuit device by performing ion implantation all over the surface including an element formation area where a gate electrode in the second layer is to be made, at the time of channel ion implantation into the element formation area where a gate electrode in the first layer is to be made. SOLUTION: The concentration of the impurity in the p-type well region 3B and that of the n-type well region 28 of a MOSFET's Qn2 and Qp2 for logic are made the same in case that the MOSFETs Qn1 and Qp1 for high breakdown voltage do not require voltage drop of power. Then, the channel ion implantation into the element formation area where a gate electrode 10 in the first layer is to be made is performed all over the surface without using a mask. Though the distribution of the concentration of acceptor type of impurities long in length of diffusion is made in the p-type MOSFET Qp2 of logic, too, the deterioration of resistance to punch through is reduced since the concentration of the n-type well region 2B is made high. Hereby, the hot process and the resist removal process can be curtailed, and the manufacture coat of a semiconductor integrated circuit device can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to relates to a manufacturing technology of a semiconductor integrated circuit device, in particular, MOSFET (M etal O x
applied to ide S emiconductor F ield E ffect T ransistor) manufacturing technology of a semiconductor integrated circuit device having a technique effectively.

[0002]

2. Description of the Related Art FIG. 10 is a sectional view showing a schematic structure of a MOSFET mounted on a conventional semiconductor integrated circuit device.
The n-channel conductivity type MOSFE shown in FIG.
T-Qn4 and p-channel conductivity type MOSFET-Qp
4 is a logic MOSFET that constitutes a logic circuit
And the n-channel conductivity type MO shown in FIG.
SFET-Qn3 and p-channel conductivity type MOSFET
-Qp3 is the gate insulating film 1 of the logic MOSFET
High-voltage MOSF having a gate insulating film 7 thicker than 3
ET. These MOSFETs are formed by a two-layer gate process, and the MOSFETs for high breakdown voltage (Qn3, Qp
The gate electrode 10 of 3) is formed of a first-layer gate material (for example, a polysilicon film), and has a logic MOSFET (Q
The gate electrode 14 of (n4, Qp4) is formed of a second-layer gate material (for example, a polysilicon film and a tungsten silicide film).

The well region differs between logic and high breakdown voltage, and the impurity concentration is higher than that of the high breakdown voltage well region (n-type well region 2A, p-type well region 3A). The well region 3B) is higher. This is because the punch-through resistance of the logic MOSFET is improved, and since the operating voltage is low, the logic MOSFET operates even when the withstand voltage is low. In addition, as described below, introduction of channel impurities (introduction of impurities for controlling a threshold voltage) is performed before forming a first-layer gate electrode in a high breakdown voltage MOSFET, and a logic MOSF is formed.
ET is performed after the first-layer gate electrode is formed and before the second-layer gate electrode is formed. FIG.
At 0, reference numeral 4 denotes an insulating film for element isolation, and reference numeral 9 denotes
Reference numeral 10a denotes an insulating film, reference numeral 15 denotes a pair of n-type semiconductor regions serving as a source region and a drain region,
Reference numeral 16 denotes a pair of p serving as a source region and a drain region.
Type semiconductor region.

A method of manufacturing a semiconductor integrated circuit device having a high breakdown voltage MOSFET and a logic MOSFET will be described below with reference to FIGS. 11 to 16 (cross-sectional views for explaining the manufacturing method).
This will be described with reference to FIG. Note that in FIGS. 11 to 16,
FIG. 3A is a cross-sectional view of a region where a high voltage MOSFET is formed, and FIG. 3B is a cross-sectional view of a region where a logic MOSFET is formed.

First, an n-type well region 2 is formed in a high breakdown voltage MOS formation portion on a main surface of a p-type semiconductor substrate 1 made of single crystal silicon.
A and p-type well regions 3A are selectively formed, and n-type well regions 2B and p-type well regions 3B are selectively formed in a logic MOS formation portion on the main surface of the p-type semiconductor substrate 1. After that, an element isolation insulating film (field insulating film) 4 is formed in the element isolation region on the main surface of the p-type semiconductor substrate 1 by, for example, a known selective oxidation method, and then subjected to a thermal oxidation process to perform the p-type semiconductor substrate. The sacrificial oxide film 5 having a thickness of, for example, about 10 to 30 [nm] is formed in the element formation region on the main surface of the first element. The steps so far are shown in FIG.

Next, the logic MOS of the p-type semiconductor substrate 1
The formation portion is covered with a mask M, and then a threshold voltage controlling impurity 6 is introduced into the element formation region of the high breakdown voltage MOS formation portion of the p-type semiconductor substrate 1 by ion implantation, and the high breakdown voltage formed in this element formation region is formed. The threshold voltages of the n-type MOSFET (Qn3) for use and the p-type MOSFET (Qp3) for high withstand voltage are determined. Conditions for ion implantation are, for example, ion species; B
+ Or BF ₂ +, energy: 30 to 100 [KeV],
Dose amount: 1E11 to 5E12 cm-3. Mask M
Is formed by applying a photosensitive resin to the entire surface of a substrate by a spin coating method and then performing a baking process, a photosensitive process, a developing process, and the like. The steps so far are shown in FIG.

Next, the mask M is removed, and then the sacrificial oxide film 5 is removed by a wet etching method.
By performing a thermal oxidation process, a gate insulating film 7 made of a silicon oxide (SiO ₂ ) film having a thickness of, for example, about 10 to 30 [nm] is formed in the element formation region on the main surface of the p-type semiconductor substrate 1.

[0008] Next, p-type entire surface, for example, 100 to 200 as a first-layer gate material on the semiconductor substrate 1 [nm] about a polysilicon film 8 CVD (C hemical V apor D epo
sition) method. During or after the deposition of the polysilicon film 8, an impurity for reducing the resistance value is introduced.

Next, an insulating film 9 is formed on the entire surface of the polysilicon film 8. The insulating film 9 is formed of a multilayer film in which a silicon oxide film, a silicon nitride (Si ₃ N ₄ ) film, and a silicon oxide film are sequentially formed. The lower silicon oxide film is 9
This is a thermal oxide film formed in a dry atmosphere at a temperature of 00 to 1000 ° C., and has a thickness of, for example, about 10 to 30 [nm]. The silicon nitride film is formed by a CVD method and has a thickness of, for example, about 10 to 30 [nm]. The upper silicon oxide film is a thermal oxide film formed in a steam atmosphere at 900 to 1000 ° C. in order to reduce pinholes in the silicon nitride film, and has a thickness of, for example, about 3 to 5 [nm]. The steps so far are shown in FIG.

Next, patterning is sequentially performed on each of the insulating film 9 and the polysilicon film 8, and as shown in FIG. 14A, the gate insulation of the high breakdown voltage MOS forming portion of the p-type semiconductor substrate 1 is formed. A gate electrode 10 is formed on the film 7. In this step, as shown in FIG. 14B, the gate electrode 10 is not formed on the gate insulating film 7 in the logic MOS formation portion of the p-type semiconductor substrate 1.

Next, the logic MOS of the p-type semiconductor substrate 1
The gate insulating film 7 in the formation portion is removed by a wet etching method, and thereafter, a thermal oxidation process is performed to form, for example, 10 to 30 in the element formation region of the logic MOS formation portion of the p-type semiconductor substrate 1.
A sacrificial oxide film 11 having a thickness of about [nm] is formed. At this time, the side wall of the gate electrode 10 in the high breakdown voltage MOS formation portion is oxidized to form an insulating film 10a.

Next, the logic MOS of the p-type semiconductor substrate 1
A threshold voltage control impurity 12 is introduced into the element formation region of the formation portion by ion implantation, and an n-type MOSFET for logic (Qn4) and a p-type
The respective threshold voltages of the type MOSFET (Qp4) are determined. Conditions for ion implantation are, for example, ion species; BF ₂
+, Energy; 30 to 80 [KeV], dose amount: 1
E11 to 5E12 cm-3. In this process,
The threshold voltage controlling impurity 12 is introduced into the p-type semiconductor substrate 1.
This is performed without covering the high-breakdown-voltage MOS formation portion with a mask. The steps so far are shown in FIG.

Next, the sacrificial oxide film 11 is removed by a wet etching method, and thereafter, a thermal oxidation process is performed to cover the element formation region on the main surface of the p-type semiconductor substrate 1 with a film thickness of about 4 to 20 [nm]. A gate insulating film 13 made of a silicon oxide film is formed.

Next, a polysilicon film of, for example, about 100 to 200 [nm] and a tungsten silicide (WSi ₂ ) of about 100 to 200 [nm] are formed on the entire surface of the p-type semiconductor substrate 1 as a second-layer gate material. Each of the films is formed by the CVD method, and thereafter, the gate material of the second layer is patterned to form the gate electrode 14 on the gate insulating film 13 in the logic MOS formation portion of the p-type semiconductor substrate 1. The steps so far are shown in FIG.

Next, a pair of n-type semiconductor regions 15 as source and drain regions and a pair of p-type semiconductor regions 16 as source and drain regions are formed by ion implantation, respectively, as shown in FIG. As shown, an n-type MOSFET is
Qn3 and a p-type MOSFET Qp3 are formed, respectively.
N-type MOSF
Each of ETQn4 and p-type MOSFET Qp4 is formed.

[0016]

SUMMARY OF THE INVENTION An n-channel conductivity type MO
The threshold voltage of the SFET is

[0017]

## EQU1 ## Vth = Vfb + 2φf + SQR (2 · ε · εo · q ·
Na · (2φf)) / Cox, and the threshold voltage of the p-channel conductivity type MOSFET is

[0018]

## EQU2 ## Vth = Vfb-2φf-SQR (2 · ε · εo · q ·
Nd · (2φf)) / Cox.

Here, Vfb: flat band voltage, ε;
Relative dielectric constant of Si, εo; dielectric constant in vacuum, q; electron charge, Na; acceptor-type impurity concentration, Nd; donor-type impurity concentration, φf: Fermi potential, Cox: capacitance per unit area of gate insulating film is there. The capacitance per unit area of the gate insulating film is

[0020]

## EQU3 ## Cox = .epsilon..epsilon.ox / Tox .epsilon.ox; relative permittivity of the gate insulating film; Tox; thickness of the gate insulating film.

Here, for simplicity, an n-channel conductive type MOSFET in which the first gate material is used as a high breakdown voltage gate and the second layer gate material is used as a logic gate will be discussed.

The impurity concentration on the channel surface of the logic MOSFET of the 0.5 [μm] process generation is determined. As typical values, Vth = 0.5 [V], Vfb = −0.9 [V], 2φf =
0.7 [V], Tox = 13.5 [nm] Also, ε (relative permittivity of Si) = 11.9, εo = 8.85
4E-14F / cm, q = 1.602E-19C, εox
By substituting (relative dielectric constant of thermal oxide film) = 3.9 into the above equation, 0.5 = −0.9 + 0.7 + SQR (2 · 1
1.9.8.854E-14.1.602E-19.N
a.0.7) / (3.9.8.854E-14 / 135)
E-8), and when this is solved, Na = 1.4E17 cm
It becomes -3.

Similarly, the impurity concentration on the channel surface of the high breakdown voltage MOSFET is determined. As a representative value, Vth =
0.8 [V], Vfb = −0.9 [V], 2 · φf = 0.
When 7 [V] and Tox = 35 [nm] are substituted into the equation of [Equation 1], Na = 4.1E16 cm-3.

In order to obtain such an impurity concentration on the channel surface, the dose of channel ion implantation of the high breakdown voltage MOSFET is 1E12 to 3E12 cm−2, and the logic MO is used.
The dose of channel ion implantation of SFET is 1E1
2-3E12cm-2.

Here, although the surface impurity concentration of the high breakdown voltage MOSFET is not more than 1/3 of that of the logic MOSFET,
The doses are almost the same because of the heat treatment from the first channel ion implantation step to before the second layer channel ion implantation step. Generally, in the poly two-layer gate process, a capacitance is formed between the first and second gate electrodes as an analog device. However, as a poly interlayer insulating film, a composite of a silicon oxide film and a silicon nitride film having a low defect density is formed. Often a membrane is used. At this time, the thermal silicon oxide film formed on the polysilicon film is formed in a dry oxidation atmosphere at 900 to 1000 ° C. in order to reduce the defect density. Further, in order to reduce the defect density of the silicon nitride film, 900 to 10
Steam oxidation at 00 ° C. is often performed. At this time, the impurities implanted in the element formation region where the first-layer gate electrode is formed are diffused to lower the surface concentration. Further, sacrificial oxidation is performed before the impurity is implanted into the element formation region where the second-layer gate electrode is formed. At this time, boron is taken into the oxide film by segregation, so that the impurity concentration on the substrate surface is further reduced. . For this reason, the dose of impurities implanted into the element formation region where the first-layer gate electrode is formed is substantially the same as that of the second-layer.

FIG. 17 shows an example of the acceptor type impurity concentration distribution in the substrate depth direction of the logic MOSFT and the high breakdown voltage MOSFET. The distribution of the p-type well region is almost the same as that of the logic at a high withstand voltage, but the concentration of the logic is higher. This is because the punch-through resistance of the logic MOSFET is improved, and since the operating voltage is low, the logic MOSFET operates even when the withstand voltage is low. The distribution of impurities implanted in the channel ion implantation process is based on the MOSF for logic.
ET is on the surface of the substrate, whereas MOSFET for high breakdown voltage
Are also distributed inside the substrate.

FIG. 18 shows the distribution in the substrate depth direction obtained by subtracting the acceptor-type impurity concentration from the donor-type impurity concentration of the p-channel MOSFET. The distribution of the donor-type impurities implanted in the n-type well region has a high breakdown voltage and a diffusion length substantially the same as that of the logic, but the concentration of the logic is higher. This is the same reason as the n-channel MOSFET. In addition, since acceptor-type impurities due to channel ion implantation are distributed on the substrate surface and high withstand voltage are also distributed on the substrate surface, the distribution obtained by subtracting the acceptor type impurity concentration from the donor type is low on the substrate surface and the high withstand voltage is low. Is also low inside the substrate. If the concentration inside the substrate is low, the width of the depletion layer between the drain diffusion layer and the substrate and between the source diffusion layer and the substrate becomes large inside the substrate, and punch-through becomes easy. In order to prevent this, the gate length is increased in the high breakdown voltage p-type MOSFET.

As described above, the channel impurity of the first-layer gate extends from the second layer due to diffusion. Therefore, if ion implantation is performed without covering the logic region with a mask, the short-channel characteristics of the logic p-type MOSFET are deteriorated. There was a problem of becoming. For this reason, at the time of channel ion implantation of the element formation region where the first-layer gate electrode is formed, the element formation region where the second-layer gate electrode is formed is masked by the photo process. One step increased, and the process cost increased.

An object of the present invention is to provide a technique capable of reducing the manufacturing cost of a semiconductor integrated circuit device.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0031]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, channel ion implantation in the element formation region where the first-layer gate electrode is formed is performed on the entire surface including the element formation region where the second-layer gate electrode is formed.

According to the above-described means, the following effects can be obtained. 0.35 [μm] process generation logic MO
The impurity concentration on the channel surface of the SFET is determined. As typical values, Vth = 0.5 [V], Vfb = −0.9
When [V], 2φf = 0.7 [V] and Tox = 8 [nm] are substituted into the above equation (1), Na = 3.9E17 cm−3.
Becomes

Generally, a power supply for a logic MOSFET
(Vcc) low voltage, high voltage MOSF
The voltage reduction of the power supply (Vpp) of the ET is slow. For example, 0.5
[Μm] From Vcc = 5 [V] in the process, 0.35 [μm]
m] process, Vcc = 3.3 [V],
Vpp may remain at 12 [V]. in this case,
The thickness of the gate oxide film of the logic MOSFET is 0.
For 13.5 [nm] of 5 [μm] process, 0.3
At 5 [μm], it becomes 8 [nm].
The thickness of the gate oxide film of the OSFET remains at 35 [nm].

As described above, when the gate oxide film thickness of the high-breakdown-voltage MOSFET and the impurity concentration on the channel surface when the scaling of the threshold voltage are not performed, the impurity concentration is 0.5
[Μm] As in the process, Na = 4.1E16 cm−3.

In summary, the impurity concentration on the channel surface of the n-type MOSFET is 0.5 [μm] to 0.3 [μm].
5 [μm] process, Logic MOSFET; Na = 1.4E17cm-3
(0.5 μm) → 3.9E17 cm−3 (0.35 μm) High voltage MOSFET: Na = 4.1E16 cm−3 (0.
5 μm) → 4.1E16 cm−3 (0.35 μm).

In general, as the process generation progresses, the impurity concentration of the p-type well region and the n-type well region of the logic MOSFET is increased in order to improve the punch-through resistance. When the voltage is not reduced, the same is applied so as not to lower the junction breakdown voltage. At this time, the dose amount of the channel ion implantation is set to be the same as that of the high withstand voltage in order to keep the threshold voltage constant, while the logic increases.

In this case, if the channel ion implantation in the element formation region where the first-layer gate electrode is formed is performed on the entire surface without using a mask, the p-type MOSFET of the logic can also be formed.
An acceptor-type impurity concentration distribution having a long diffusion length is formed. However, since the concentration of the n-type well region is increased, deterioration of punch-through resistance is reduced.

Therefore, it is not necessary to mask the element formation region where the second-layer gate electrode is formed by the photo-step at the time of channel ion implantation of the element formation area where the first-layer gate electrode is to be formed. The number of steps can be reduced by one, and the manufacturing cost of the semiconductor integrated circuit device can be reduced.

[0040]

Embodiments of the present invention will be described below in detail with reference to the drawings.

In all the drawings for describing the embodiments of the present invention, components having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.

FIG. 1 is a block diagram showing a schematic configuration of a microcomputer (semiconductor integrated circuit device) according to one embodiment of the present invention.

As shown in FIG. 1, the microcomputer comprises a logic circuit unit (CPU) 21, a RAM circuit unit 22, a ROM circuit unit 23, a data input / output circuit unit 24, a clock oscillator (OSC) 25, and a power supply unit 26. And the like are mixedly mounted on the same substrate. Input / output data bus (I / O BUS) 2 between these units
7 are connected to each other. RAM unit 22
It is composed of a DRAM (D ynamic R andum A ccess M emory) or SRAM (S tatic R andom A ccess M emory). The ROM unit 23 includes a mask ROM ( R
is constituted by ead O nly M emory), or flash memory. The logic circuit unit 21 and the input-output circuit unit 24, etc., higher integration and for the purpose of reducing power consumption, n-channel conductivity type MOSFET and p CMOS using channel conductivity type MOSFET (C omplementary M
OS ) circuit configuration.

FIG. 2 is a sectional view showing a schematic configuration of the MOSFET mounted on the microcomputer. An n-channel conductivity type MOSFET-Qn shown in FIG.
2 and p-channel conductivity type MOSFET-Qp2 are logic MOSFETs constituting a logic circuit,
An n-channel conductivity type MOSFET shown in FIG.
-Qn1 and MOSFET of p-channel conductivity type -Qp1
Is a high breakdown voltage MOSFET in which the gate insulating film 7 is thicker than the gate insulating film 13 of the logic MOSFET. These MOSFETs are formed by a two-layer gate process, and the gate electrode 10 of the high-breakdown-voltage MOSFET (Qn1, Qp1) is formed of a first-layer gate material (for example, a polysilicon film), and a logic MOSFET (Qn2, Qn1).
The gate electrode 14 of p2) is formed of a second-layer gate material (for example, a polysilicon film and a tungsten silicide film). The high breakdown voltage MOSFET is used in the data input / output circuit unit 24, for example. Further, each of the high breakdown voltage MOSFETs has a longer gate length than the logic MOSFET.

The well region is different between the logic and the high breakdown voltage, and the impurity concentration is higher than that of the high breakdown voltage well region (the n-type well region 2A and the p-type well region 3A). The well region 3B) is higher. This is because the punch-through resistance of the logic MOSFET is improved, and since the operating voltage is low, the logic MOSFET operates even when the withstand voltage is low. In addition, as described below, introduction of channel impurities (introduction of impurities for controlling a threshold voltage) is performed before forming a first-layer gate electrode in a high breakdown voltage MOSFET, and a logic MOSF is formed.
ET is performed after the first-layer gate electrode is formed and before the second-layer gate electrode is formed. Note that FIG.
In the figure, reference numeral 4 denotes an insulating film for element isolation, and reference numeral 9 denotes
10a is an insulating film, 15 is a pair of n-type semiconductor regions serving as a source region and a drain region, and 16
Denotes a pair of p-type semiconductor regions serving as a source region and a drain region, reference numeral 17 denotes an interlayer insulating film, and reference numeral 18 denotes a wiring.

Hereinafter, a method for manufacturing a microcomputer having a MOSFET for high breakdown voltage and a MOSFET for logic will be described with reference to FIGS. 3 to 9 (cross-sectional views for explaining the manufacturing method). Note that, in FIGS. 3 to 9, (A)
FIG. 1 is a cross-sectional view of a region where a high breakdown voltage MOSFET is formed, and FIG. 2B is a cross-sectional view of a region where a logic MOSFET is formed.

First, an n-type well region 2 is formed in a high breakdown voltage MOS forming portion on the main surface of a p-type semiconductor substrate 1 made of single crystal silicon.
A and p-type well regions 3A are selectively formed, and n-type well regions 2B and p-type well regions 3B are selectively formed in a logic MOS formation portion on the main surface of the p-type semiconductor substrate 1. After that, an element isolation insulating film (field insulating film) 4 is formed in the element isolation region on the main surface of the p-type semiconductor substrate 1 by, for example, a known selective oxidation method, and then subjected to a thermal oxidation process to perform the p-type semiconductor substrate. The sacrificial oxide film 5 having a thickness of, for example, about 10 to 30 [nm] is formed in the element formation region on the main surface of the first element. The steps so far are shown in FIG.

Next, the logic MOS of the p-type semiconductor substrate 1
The formation portion is not covered with the mask, and the threshold voltage controlling impurity 6 is added to the element formation region of the high breakdown voltage MOS formation portion of the p-type semiconductor substrate 1.
Is introduced by an ion implantation method, and a high breakdown voltage n-type MOSFET (Qn1) and a high breakdown voltage p
Each threshold voltage of the type MOSFET (Qp1) is determined. Ion implantation conditions are, for example, ionic species; + B + or BF _2, energy; 30 to 100 [KeV], dose; a 1E11~5E12cm-3. In this step, the threshold voltage controlling impurity 6 is also introduced into the element formation region of the logic MOS formation portion of the p-type semiconductor substrate 1. The steps so far are shown in FIG.

Next, the sacrificial oxide film 5 is removed by a wet etching method, and thereafter, a thermal oxidation treatment is applied to the element formation region on the main surface of the p-type semiconductor substrate 1, for example, 10 to 30 [n].
m], a gate insulating film 7 made of a silicon oxide (SiO ₂ ) film is formed.

Next, p-type entire surface, for example, 100 to 200 as a first-layer gate material on the semiconductor substrate 1 [nm] about a polysilicon film 8 CVD (C hemical V apor D epo
sition) method. During or after the deposition of the polysilicon film 8, an impurity for reducing the resistance value is introduced.

Next, an insulating film 9 is formed on the entire surface of the polysilicon film 8. The insulating film 9 is formed of a multilayer film in which a silicon oxide film, a silicon nitride (Si ₃ N ₄ ) film, and a silicon oxide film are sequentially formed. The lower silicon oxide film is 9
This is a thermal oxide film formed in a dry atmosphere at a temperature of 00 to 1000 ° C., and has a thickness of, for example, about 10 to 30 [nm]. The silicon nitride film is formed by a CVD method and has a thickness of, for example, about 10 to 30 [nm]. The upper silicon oxide film is a thermal oxide film formed in a steam atmosphere at 900 to 1000 ° C. in order to reduce pinholes in the silicon nitride film, and has a thickness of, for example, about 3 to 5 [nm]. The steps so far are shown in FIG.

Next, the insulating film 9 and the polysilicon film 8 are sequentially patterned, and as shown in FIG. 6A, the gate insulation of the high breakdown voltage MOS forming portion of the p-type semiconductor substrate 1 is formed. A gate electrode 10 is formed on the film 7. In this step, as shown in FIG. 6B, the gate electrode 10 is not formed on the gate insulating film 7 in the logic MOS formation portion of the p-type semiconductor substrate 1.

Next, the logic MOS of the p-type semiconductor substrate 1
The gate insulating film 7 in the formation portion is removed by a wet etching method, and thereafter, a thermal oxidation process is performed to form, for example, 10 to 30 in the element formation region of the logic MOS formation portion of the p-type semiconductor substrate 1.
A sacrificial oxide film 11 having a thickness of about [nm] is formed. At this time, the side wall of the gate electrode 10 in the high breakdown voltage MOS formation portion is oxidized to form an insulating film 10a.

Next, the logic MOS of the p-type semiconductor substrate 1
Threshold voltage control impurities 12 are introduced into the element formation region of the formation portion by ion implantation, and an n-type MOSFET for logic (Qn2) and a p-type
The respective threshold voltages of the type MOSFET (Qp2) are determined. Conditions for ion implantation are, for example, ion species; BF
₂ +, energy; 30 to 80 [Kev], dose amount: 1
E11 to 5E12 cm-3. In this step, the introduction of the threshold voltage controlling impurity 12 is performed without covering the high breakdown voltage MOS formation portion of the p-type semiconductor substrate 1 with a mask. The steps so far are shown in FIG.

Next, the sacrificial oxide film 11 is removed by a wet etching method, and then a thermal oxidation process is performed to form a film having a thickness of about 4 to 20 [nm] on the element formation region on the main surface of the p-type semiconductor substrate 1. A gate insulating film 13 made of a silicon oxide film is formed.

Next, as a second layer gate material, for example, a polysilicon film of about 100 to 200 [nm] and tungsten silicide (WSi ₂ ) of about 100 to 200 [nm] are formed on the entire surface of the p-type semiconductor substrate 1. Each of the films is formed by the CVD method, and thereafter, the gate material of the second layer is patterned to form the gate electrode 14 on the gate insulating film 13 in the logic MOS formation portion of the p-type semiconductor substrate 1. During or after the deposition of the polysilicon film, which is the second-layer gate material, an impurity that reduces the resistance value is introduced. The steps so far are shown in FIG.

Next, a pair of n-type semiconductor regions 15 serving as a source region and a drain region and a pair of p-type semiconductor regions 16 serving as a source region and a drain region are formed by an ion implantation method. As shown, an n-type MOSFET Q
Each of an n1 and a p-type MOSFET Qp1 is formed, and an n-type MOSFET is formed in a logic MOS forming portion of the p-type semiconductor substrate 1.
Each of TQn2 and p-type MOSFET Qp2 is formed.

Next, an interlayer insulating film 17 made of, for example, a silicon oxide film is formed on the entire surface of the p-type semiconductor substrate 1 by a CVD method.
From the connection holes reaching the semiconductor regions (15, 16) and the upper surface of the interlayer insulating film 17, the gate electrode (1
0, 14) are formed, and thereafter, wiring 18 electrically connected to each of the semiconductor region of the MOSFET and the gate electrode is formed through these connection holes, whereby the state shown in FIG. Become. Thereafter, an interlayer insulating film and a wiring are further sequentially formed, and finally a final protective film is formed.

In this embodiment, generally, as the process generation advances, the logic MOSFETs (Qn2,
The impurity concentration of the p-type well region 3B and the n-type well region 2B of Qp2) is increased in order to improve the punch-through resistance, but the high breakdown voltage MOSFETs (Qn1, Qp1)
Are the same when the voltage of the power supply is not reduced. At this time, the dose amount of the channel ion implantation is set to be the same as that of the high withstand voltage in order to keep the threshold voltage constant, while the logic increases. In this case, if the channel ion implantation of the element formation region where the first-layer gate electrode is formed is performed over the entire surface without using a mask, a p-type MOSFET of logic is obtained.
In Qp2, an acceptor-type impurity concentration distribution having a long diffusion length is formed. However, since the concentration of the n-type well region 2B is increased, deterioration of punch-through resistance is reduced.

Therefore, it is not necessary to mask the element formation region where the second-layer gate electrode is formed by the photo-step at the time of channel ion implantation of the element formation area where the first-layer gate electrode is to be formed. The number of steps can be reduced by one, and the manufacturing cost of the semiconductor integrated circuit device can be reduced.

In this embodiment, an example using a MOSFET has been described. However, the present invention is not limited to this.
FET (M etal I nsulator S emiconductor F ield E
may be a ffect T ransistor) it is given a course.
The gate insulating film of the MISFET is, for example, a thermal oxide film formed of N.
It is formed of a Si-ON film oxidized in a ₂ O gas atmosphere. The MISFET using the gate insulating film made of the Si-ON film has, for example, improved hot carrier resistance.

As described above, the invention made by the present inventor is:
Although specifically described based on the embodiment, the present invention
It is needless to say that the present invention is not limited to the above-described embodiment, but can be variously modified without departing from the scope of the invention.

[0063]

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

The manufacturing cost of the semiconductor integrated circuit device can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a microcomputer (semiconductor integrated circuit device) according to an embodiment of the present invention.

FIG. 2 shows a MOS mounted on the microcomputer.
FIG. 2 is a cross-sectional view illustrating a schematic configuration of an FET.

FIG. 3 is a sectional view for explaining a method for manufacturing the microcomputer.

FIG. 4 is a cross-sectional view for explaining the method for manufacturing the microcomputer.

FIG. 5 is a cross-sectional view for explaining a method for manufacturing the microcomputer.

FIG. 6 is a cross-sectional view for explaining a method for manufacturing the microcomputer.

FIG. 7 is a cross-sectional view for explaining a method for manufacturing the microcomputer.

FIG. 8 is a cross-sectional view for explaining a method for manufacturing the microcomputer.

FIG. 9 is a cross-sectional view for explaining a method for manufacturing the microcomputer.

FIG. 10 shows an MO mounted on a conventional semiconductor integrated circuit device.
FIG. 2 is a cross-sectional view illustrating a schematic configuration of an SFET.

FIG. 11 is a cross-sectional view for explaining a conventional method for manufacturing a semiconductor integrated circuit device.

FIG. 12 is a cross-sectional view for explaining a conventional method for manufacturing a semiconductor integrated circuit device.

FIG. 13 is a cross-sectional view for explaining a conventional method of manufacturing a semiconductor integrated circuit device.

FIG. 14 is a cross-sectional view for explaining a conventional method for manufacturing a semiconductor integrated circuit device.

FIG. 15 is a cross-sectional view for describing a method for manufacturing a conventional semiconductor integrated circuit device.

FIG. 16 is a cross-sectional view for explaining a method for manufacturing a conventional semiconductor integrated circuit device.

FIG. 17 shows a MOSFET for logic and a MOSF for high breakdown voltage.
FIG. 5 is a diagram showing an acceptor-type impurity concentration distribution in the ET substrate depth direction.

FIG. 18 is a diagram showing a distribution in a substrate depth direction obtained by subtracting an acceptor-type impurity concentration from a donor-type impurity concentration of a p-channel MOSFET.

[Explanation of symbols]

1 ... p-type semiconductor substrate, 2A, 2B ... n-type well region, 3
A, 3B: p-type well region, 4: insulating film for element isolation, 5
... sacrifice oxide film, 6 ... impurity, 7 ... gate insulating film, 8 ... polysilicon film, 9 ... insulating film, 10 ... gate electrode, 10a
... insulating film, 11 ... sacrificial oxide film, 12 ... impurity, 13 ... gate insulating film, 14 ... gate electrode, 15 ... n-type semiconductor region, 16 ... p-type semiconductor region, 17 ... interlayer insulating film, 18 ...
Wiring, Qn1, Qn2, Qn3, Qn4... N-type MOSF
ET, Qp1, Qp2, Qp3, Qp4 ... p-type MOSF
ET.

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Koichi Nakagawa 15th Asahidai, Moroyama-cho, Iruma-gun, Saitama No. 5F048 AA09 AB10 BA01 BB06 BB07 BB15 BE03 DA10 DA25

Claims (3)

[Claims] 1. A first MISFET of an n-channel conductivity type and a second MIS of a p-channel conductivity type having a gate electrode formed in a first region on a main surface of a semiconductor substrate via a gate insulating film.
An n-channel conductive third MISFET and a p-channel conductive fourth MISFET in which a gate electrode is formed via a gate insulating film in a second region different from the first region of the main surface of the semiconductor substrate. Having the third MISFE
T, wherein each gate electrode of the fourth MISFET is a method of manufacturing a semiconductor integrated circuit device formed after forming each gate electrode of the first MISFET and the second MISFET. A method of manufacturing a semiconductor integrated circuit device, comprising: ion-implanting an impurity for controlling a threshold voltage into a first region including a second region on a main surface of the semiconductor substrate. 2. The third MISFET and a fourth MISFE.
T is a logic MIS constituting a logic circuit.
FET, the first MISFET, the second MISFE
T represents the third MISFET and the fourth MISFET, respectively.
2. A high-breakdown-voltage MISFET having a gate insulating film thicker than the respective gate insulating films.
3. The method for manufacturing a semiconductor integrated circuit device according to 1. 3. The first MISFET and the second MISFE.
T represents the third MISFET and the fourth MISFET, respectively.
2. The gate length is longer than each of the above.
A method of manufacturing a semiconductor integrated circuit device according to claim 2.