JP2000100679A - Substrate-to-substrate microregion solid-phase junction method with thinner piece and element structure - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electrical coupling in a microregion between substrates by separating a mechanism junction part from an electrical coupling part for joint, for a thinner substrate. SOLUTION: A structure comprising electrical coupling regions 6 and 7 and joint regions 10 and 11 comprising mechanical joint parts 17 and 19 between substrates 1 and 2 is formed on both substrates. After the substrate 2 is rotated in plate while the joint regions 10 and 11 on both substrates are so aligned as to face each other with the coupling regions 6 and 7 also aligned to face each other, the most substrates are applied with a pressurizing force 21 to joint the joint parts 17 and 19 together so that the coupling regions 6 and 7 are electrically coupled together in solid-phase joint. After the solid-phase joint, the substrate 2 is polished to a thin one, to provide an electrical joint in a microregion where an interface dislocation is brought about to the surface of the thin substrate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a thin film between substrates by thinning which realizes an electric connection in a very small region between substrates of the same or different materials (electrical connection with substantially no contact resistance at the bonding surface). The present invention relates to a regional solid-state bonding method and an element structure suitably realized by the bonding method.

[0002]

2. Description of the Related Art Conventionally, as a method of directly joining different kinds of semiconductors to each other for producing a light emitting device, there is a method disclosed in “Applied Physics”, No.
Vol. 3, No. 1 (Hiroshi Wada, Ken Kamijo, p.53, 1994)
InP / GaAs and InP
The bonding of the P / Si combination is obtained by cleaning the surface to be bonded and then performing a heat treatment at 700 ° C. for 30 minutes in a hydrogen atmosphere with a weight placed on the substrate.

[0003] Appl. Phys. Lett.
(Lincoln Lab., ZLLian, 56 (8), 19, Feb. 1990, p.737)
The bonding of the Inp / GaAs combination cleans the surfaces to be bonded and then at 750 ° C. in a hydrogen atmosphere in a cylindrical graphite / quartz reactor as described in
And by heat treatment.

[0004]

However, in the above-mentioned conventional example, since the bonding is performed at a high temperature of about 700 ° C. and the bonding is performed over the entire surface of the substrates, there are the following inconveniences. 1. In the case of joining different kinds of semiconductors having different thermal expansion coefficients,
After bonding at a high temperature as described above, during or after cooling to room temperature, a phenomenon in which the bonded substrate warps occurs, and the bonded portion is easily peeled. That is, residual stress is generated in the bonded substrate, and various problems occur. 2. Since the bonding combines electrical bonding and mechanical bonding strength (bonding strength for preventing the two materials from being peeled off), the bonding area is reduced in order to reduce the functional bonding portion. Decreasing the size reduces the mechanical bonding strength. In such a case, the decrease in the bonding strength causes peeling at the bonding portion during the process. Therefore, even if a small area is not required for any functional electrical connection, it is difficult to reduce the bonding area because the mechanical coupling strength must be ensured. In this way, it is difficult to join in a minute area, and it is difficult to reduce the joining area in response to a demand such as reducing the threshold value of a surface emitting semiconductor laser or the like. Third, since it is only the bonding between the substrates, it is difficult to bond a plurality of other micro-piece substrates to one substrate.

SUMMARY OF THE INVENTION In view of the above problems, it is an object of the present invention to separate a joint for securing mechanical coupling strength from an electrical joint for achieving electrical coupling and to join at least one of the substrates. An object of the present invention is to provide a microregion solid-state bonding method between substrates which achieves electrical coupling in a microregion between substrates of the same or different materials by thinning, and an element structure suitably realized by this bonding method.

[0006]

In order to achieve the above-mentioned object, the solid-state bonding method between substrates of the present invention according to the invention of the present application is a method of electrically coupling by bonding in a small region between the same or different semiconductor substrates. Wherein the first and second structures have a bonding region having an electrical connection and a bonding region having a bonding portion for providing a mechanical bonding force between the substrates.
After the at least one semiconductor substrate is rotated in the plane while the bonding regions and the bonding regions on the first and second semiconductor substrates are aligned so as to face each other, Joining the joining portions while applying a pressing force to the first and second semiconductor substrates to electrically couple the joining regions by solid-phase joining; and after the solid-phase joining, at least one of the semiconductor substrates is sliced. By performing the polishing, for example, a thinned substrate that fits in the bonding region is formed, and electrical bonding is realized in a minute region in which interfacial dislocations are brought to the surface of the thinned substrate. In the inter-substrate microregion solid-phase bonding method of the present invention, the substrates are provided with a mechanical bonding force only by bonding the material of the bonding portion, and at the same time, electrical bonding is obtained between the bonding regions of the substrates, and further after bonding, At least one of the semiconductor substrates was thinned and polished into a thinned substrate that fits in the bonding region, and interfacial dislocations were brought to the surface of the thinned substrate.

[0007] Since the joining is performed by the joining members, the electrical joining between the electrical joining surfaces and the sufficient mechanical strength between the joining portions can be obtained at a relatively low temperature, and the mechanical joining between the joining portions can be obtained. Since the force can be secured, the coupling area of the electric coupling surface can be made extremely small, and the electric coupling is simply pressed and brought close to the order of the interatomic distance and solid phase bonding is performed. It is possible to obtain electrical coupling between similar or dissimilar materials, regardless of the type of material. At this time, since the solid phase bonding is performed while at least one semiconductor substrate is rotated in the plane, when the substrate is subsequently thinned, the state of the interface dislocation generated on the electrically bonded solid bonded surface is determined by the thin flake. Therefore, when a mixed crystal semiconductor or a semiconductor substrate is further formed or bonded on the surface of the bonded exfoliated substrate, electrical coupling having various characteristics can be obtained. It becomes possible.

[0008] More specifically, the following is also possible. The first and second semiconductor substrates are configured such that a sealed atmosphere tank including a bonding region therein is formed by bonding the bonding portions on the bonding region. In this case, it is preferable that the joining portions on the joining region of the first and second semiconductor substrates are joined in a reduced-pressure atmosphere so that the closed atmosphere tank becomes a reduced-pressure atmosphere tank. This allows the electrical coupling to be positive pressure (atmospheric pressure)
The application is performed more reliably by the application.

The sealed atmosphere tank is formed, for example, by attaching a joint made of an adhesive having a concentric saw-tooth (irregular shape) cross section so as to surround the periphery of the joint region in at least one joint region of the semiconductor substrate. It can be achieved by forming.

[0010] Further, InGaAs is further formed on the thinned substrate.
A thin film layer made of a semiconductor such as a mixed crystal semiconductor of P, InGaAlP, or GaInAs is formed.

The third semiconductor substrate may be provided on the thinned substrate or the thinned substrate on which the thin film layer is formed, which is electrically connected in a very small area to the connecting region of the first or second semiconductor substrate. After the bonding regions are aligned so that the bonding regions formed on these semiconductor substrates face each other and the bonding regions face each other, a pressing force is applied to these semiconductor substrates to form a bonding portion of the bonding regions. The electrical connection is further performed by joining the two. Thereby, as described above, it is possible to obtain electrical coupling having various characteristics.

[0012] Also in this bonding, the semiconductor substrate and the third semiconductor substrate electrically coupled to the thinned substrate are connected to each other by a joint between the joints on the joint region. Preferably, it is configured to be formed. Needless to say, it is preferable that the joints on the joint region of the two substrates are joined in a reduced pressure atmosphere so that the closed atmosphere tank becomes a reduced pressure atmosphere tank. In some cases, the third semiconductor substrate is formed into a thinned substrate as described above. However, the third semiconductor substrate may be cut into a thinned substrate completely contained in the bonding region, and the sealed atmosphere tank may be eliminated. (In this case, the rigidity of the third semiconductor substrate is reduced, the positive pressure due to the atmospheric pressure is efficiently applied to the electrical coupling surface, and the effect of the reduced-pressure atmosphere tank becomes more effective.
When the device structure is exposed to the air, the electrical connection is further reliably and stably). Therefore, the reduced-pressure atmosphere in the reduced-pressure atmosphere tank may be a reduced-pressure air atmosphere, an inert gas atmosphere or a reducing gas atmosphere, or a reduced-pressure argon gas, nitrogen gas, hydrogen gas or a mixed gas of these gas types. In the case of an atmosphere or the like, deterioration of the electric coupling portion sealed therein is prevented, and the life is extended.

At the time of bonding between the first or second semiconductor substrate formed as the thinned substrate and the third semiconductor substrate, at least one of the semiconductor substrates may be rotated in a plane. At this time, the in-plane rotation angles of the semiconductor substrate that is not the sliced substrate and the third semiconductor substrate may be zero.

A temporary bonding portion is further formed on at least one of the semiconductor substrates. After the alignment, the substrates are temporarily bonded at the temporary bonding portion while applying a pressing force to the substrates. For example, the joining portions may be joined in a reduced-pressure atmosphere of an atmospheric pressure or less while applying pressure.

The semiconductor substrate is made of Si, InP, GaAs.
s, GaN, Ge, GaP, ZnS, CdS, InA
s, InSb, SiC, PbS, Se, and compound semiconductors formed on any of these semiconductor substrates,
It is a mixed crystal semiconductor of nGaAsP, InGaAlP, and GaInAs.

[0016] If a convex electric coupling surface is formed in at least one coupling region of the semiconductor substrate, electric coupling can be more reliably achieved.

The joint is made of a material having plastic deformability. Thereby, mechanical joining is performed well. Examples of the material having plastic deformability include metal materials, and metal materials having plastic deformability include Al, Au, Sn, Cu, and Z.
n, Pb, Ni and PbSn compounds.

The joining temperature is 350 ° C. or less or room temperature. Since the bonding is performed at a relatively low temperature, the occurrence of various problems due to the occurrence of residual stress in the bonded substrate is eliminated.

In order to join the substrate on which the light emitting element is formed and the substrate on which a mirror for forming a laser beam using the light of the light emitting element as excitation light is formed, optical coupling and electrical coupling are generated. Bonding in a small area can also be performed using a structure having a bonding region and a bonding region having a bonding portion for providing bonding force.

The same substrate may have a plurality of coupling regions for producing electrical coupling and a plurality of junction regions.

Further, in the element structure according to the present invention for achieving the above object, in order to obtain electrical coupling by bonding in a small area between the same or different semiconductor substrates, a coupling region for producing electrical coupling is provided. And a structure having a bonding region having a bonding portion for providing a mechanical bonding force between the substrates is formed on the first and second semiconductor substrates, and the bonding region and the bonding region are formed of the first and second semiconductor substrates. The first and second semiconductor substrates are connected to each other after at least one of the semiconductor substrates is rotated in the plane while the bonding regions and the bonding regions on the semiconductor substrate are aligned so as to face each other. When the joining portions are joined while applying a pressing force, the joining regions are shaped so as to be electrically coupled by solid-state joining, and after the solid-state joining, at least one semiconductor substrate is thinned. By being polished, for example It has been thinned substrate that fits to the binding region, characterized in that the electrical connection in a minute area leads to interfacial dislocations to the surface of the thin singulated substrate is realized.

The principle of the present invention will be described using a specific example.
In a typical example of the present invention, for example, the substrates are provided with bonding force only by bonding materials having plastic deformability, and at the same time, electrical coupling is obtained between the substrates with minute projections, and the electrical coupling surface is obtained. Is sealed with materials having plastic deformability. The bonding is performed by applying a load in a reduced-pressure atmosphere (in vacuum). When taken out to the atmosphere, the reduced-pressure atmosphere tank in which the electric coupling surface by the joining exists always receives a pressure of 1 atm. That is, the electrical connection is always under pressure. After the bonding, at least one of the substrates is flaked by polishing. Since the rigidity of the one substrate is reduced by the thinning, the electrical connection surface is further bonded and adhered over the entire surface. When the thinning polishing is further performed, only the minute bonded thinning substrate is bonded to the other substrate by solid-state bonding.

Further, the bonded thinned substrate bonded to the other substrate and another substrate are bonded by the same method as described above, and after bonding, the other substrate is bonded. Polishing for thinning. Alternatively, a thin film layer made of a mixed crystal semiconductor is formed on the bonded exfoliated substrate, and another thin film is formed on the thin film layer.
One substrate is bonded in the same manner as described above, and after bonding, the other substrate is polished for thinning. At this time, it is also possible to join the substrates in a state where they are rotated in a plane in advance. That is, it is possible to introduce an interface transition at an electrical coupling surface in a minute region between the substrates.

In the above process, a bonding surface for providing electrical connection between the substrates and a bonding region formed of a saw-toothed adhesive for providing mechanical bonding strength are provided on one of the substrates, and the other is provided on the other substrate. In the same manner, a bonding surface for providing electrical connection and a bonding region for providing mechanical bonding strength are provided.
Further, a temporary bonding portion is provided on at least one of the substrates.
Next, the two substrates are positioned so that the bonding surface and the bonding region face each other, and then a compressive load is applied to both substrates from both sides. By the application of the load, the joining is first started at the temporary joining portion in the joining region, and the mechanical joining strength is obtained.
Since the tacked joint has a structure intended only to maintain the above positioning even during handling, the joint surface is sealed even when the tacked joint is joined. Next, the temporary bonded assembly is introduced from the atmosphere into a reduced-pressure atmosphere (in a vacuum), and a compressive load is applied. By the application of the load, bonding is performed at the main bonding portion having the adhesive element, and mechanical strength is obtained. After the bonding, at least one of the substrates is polished for thinning. By the thinning polishing, the rigidity of the one substrate is gradually lost, and the above-mentioned bonding surfaces obtain electrical connection over the entire surface. That is, the two substrates come close to each other until the van der Waals force acts. When the thinning polishing is further continued, only the minute bonded thinned substrate remains as a bonding piece. That is, as a result, it is possible to bond the minute bonded thinned substrate and the other substrate which are rotated in the plane with each other. Interfacial dislocations can be introduced into the bonding surface between the substrates by the solid phase bonding. Therefore, when the lamination polishing is further continued, that is, when the bonded lamination substrate is further laminated, the state of the interface dislocation can be brought to the surface of the lamination substrate. Therefore, when a mixed crystal semiconductor is formed on the surface of the bonded exfoliated substrate or when the semiconductor substrate is bonded, it is possible to obtain electrical coupling having various characteristics.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, specific embodiments of the present invention will be described with reference to the drawings.

First Embodiment FIGS. 1 to 18 show the characteristics of the first embodiment of the present invention best. 1 and 2 are plan views of a structure of two substrates 1 and 5 to be joined, FIG. 3 is a plan view of a structure of a substrate 2 joined with in-plane rotation, and FIG. FIG. 5 is a plan view showing the state of in-plane rotation between each other (the substrate 2 in FIG. 4 is viewed from the back side of the substrate 2 in FIG. 3, and therefore rotates in the opposite direction as compared to FIG. 3), FIG. Is the substrate surface (10
FIG. 6, FIG. 7, and FIG. 8 showing the site of atom 8 in FIG.
FIG. 9 is a diagram showing interfacial dislocations at the time of substrate bonding at different in-plane rotation angles θ, FIG. 9 is a sectional view taken along the arrow A in FIG. 1, and FIG.
3 is a cross-sectional view taken along arrow B and FIG. 3 is a cross-sectional view taken along arrow C. FIG. 11 is a cross-sectional view of both substrates in an alignment state with in-plane rotation before bonding, and FIG. 13 is a cross-sectional view of the two substrates at the end of the application of the load, FIG. 14 is a cross-sectional view of a state in which the two substrates have been joined and polished, and FIG. FIG. 16 is a cross-sectional view of an aligned state of two substrates, FIG. 16 is a cross-sectional view of the substrates in an aligned state of FIG. 15 when a load is applied, and FIG. FIG. 18 is a cross-sectional view, and FIG.
FIG. 7 is a cross-sectional view when another substrate is being polished for thinning.

In the figure, reference numerals 1, 2 and 5 denote substrates for bonding (the substrate 5 is a substrate having a structure which does not take into account bonding with in-plane rotation), and 3 denotes a substrate 2 to the substrate 1. A bonded and thinned substrate formed when the substrate 2 is sliced after bonding, 6 is an electrical coupling surface on the substrate 1, 7 is an electrical coupling surface formed of a convex portion on the substrate 2, 8 and 9 are Positions of atoms when the bonding surface 6 and the bonding surface 7 are respectively viewed at the atomic level,
Numerals 10 and 11 denote bonding regions that provide mechanical bonding force in the substrates 1 and 2, respectively. Numerals 12 and 13 denote insulating layers formed on the substrates 1 and 2, respectively, for electrical insulation. The undercoat layers 16 and 17 are formed on the undercoat layers 14 and 15, respectively, to improve the adhesion of the layers sandwiching the insulating layers 12 and 13, respectively.
Is a temporary bonding portion made of a metal film formed on the bonding layer 16, and 19 is a main bonding portion (glue) made of a metal formed on the bonding layer 16 and formed of an adhesive having a concentric and saw-tooth cross section when viewed from above. 20 is a sealed decompression atmosphere tank formed after joining the two substrates 1 and 2 or the two substrates 1 and 5, and 21 is both substrates 1, 2 or both. The applied load 22 for bonding the substrates 1 and 5 is a removal area for thinning the substrate 5 so that the closed reduced-pressure atmosphere tank 20 works effectively on the bonding surface.

Next, a manufacturing method of the above configuration will be described. In the above configuration, a semiconductor substrate is used as one of the bonding substrates 1,
As shown in the cross-sectional view of FIG. 9, an insulating layer 12 made of an electrical insulating film is formed on the bonding region 10 around the bonding surface 6 by using a photolithography process using a resist mask. The undercoat layer 14 is formed on the undercoat layer 1.
A bonding layer 16 made of a metal film is formed on the substrate 4. Furthermore,
On the bonding layer 16, as shown in FIGS. 1 and 9, a main bonding portion 19 is formed concentrically around the bonding surface 6 by metal plating, and a similar photolithography process is used. Then, a temporary bonding portion 18 is formed. At this time, as shown in FIG. 9, the height from the bonding layer 16 is formed so that the temporary bonding portion 18 is higher than the main bonding portion 19.

Next, a semiconductor substrate is used as the other bonding substrate 2, and the periphery of the coupling surface 7 for electrical coupling is first etched in a concave shape by using a photolithography process using a resist mask. A convex coupling surface 7 is formed. As shown in FIG. 10, a flat area around the convex bonding surface 7 is defined as a bonding region 11, and the bonding region 11 is defined as a region that should bear mechanical bonding strength. An insulating layer 13 made of an electrical insulating film is formed in the bonding region 11, a subbing layer 15 is formed on the insulating layer 13, and a bonding layer made of a metal film is formed on the subbing layer 15. 17 is formed.

After the film formation, the substrates 1 and 2 are aligned by an alignment device (not shown) so that the bonding surfaces 6 and 7 face each other as shown in FIG. At this time, the substrates 1 and 2 are twisted (in-plane rotation) by an angle θ with respect to each other as seen in FIG. Thereby, when the bonding surfaces 6 and 7 are close to each other at an atomic level in order to obtain electrical coupling with each other, it is possible to predict the introduction of an interface transition depending on the twist angle θ at the interface between the bonding surfaces 6 and 7. . Its form is shown in FIG.
7 and 8 (these are different in the twist angle θ (the difference between the azimuths of the same semiconductor material and the same plane orientation, which is 45 degrees in FIG. 8). This is the case of bonding of surfaces having the same plane orientation with the material).

In the method using the alignment apparatus, the light transmitted through the substrate 1 and the substrate 2 by irradiating infrared light is subjected to CC.
This is a method in which light is received by a D camera, and the camera is rotated along an orthogonal X axis and Y axis while being rotated at a certain angle while being viewed on a monitor television, thereby performing alignment. For this reason, FIG.
As shown in FIG. 1, alignment is performed such that the coupling surfaces 6 and 7 face each other. After the completion of the alignment, a compressive load 21 is applied to the substrates 1 and 2 from both sides as shown in FIG. The application of the load 21 is stopped when the temporary bonding portion 18 of the substrate 1 and the bonding layer 17 of the substrate 2 are mechanically bonded to each other. By this operation, the substrates 1 and 2 are temporarily bonded while maintaining the aligned state (FIG. 12). Here, the substrates 1 and 2 are respectively connected to the coupling surfaces 6 in postures as shown in FIGS.
7, the substrates 1 and 2 in the temporary bonding.
Are rotated relative to each other by an angle of θ in the plane (twist) as shown in FIG. Temporarily bonded substrates 1 and 2
Are integrated and maintain the alignment state during handling.

In the following process, the temporarily bonded substrates 1 and 2
Is introduced into a reduced-pressure atmosphere (in a vacuum), and the space between the substrates 1 and 2 is evacuated. In the reduced pressure atmosphere, a load 21 is further applied from both sides of the substrates 1 and 2 as shown in FIG. According to the above process, as shown in FIG. 13, the main bonding portion 19 of the substrate 1 and the bonding layer 17 of the substrate 2 obtain a mechanical bonding with each other. When the applied load 21 is further increased, the coupling surface 6 of the substrate 1 and the coupling surface 7 of the substrate 2 are extremely close to each other. At this point, when the applied load 21 is released, the substrate 1 and the substrate 2 are firmly mechanically joined together with the plastic deformation of the temporary bonding portion 18 and the permanent bonding portion 19, and the substrate 1 and the substrate 2 The close distance therebetween is maintained, and at the same time, a closed reduced-pressure atmosphere tank 20 as shown in FIG. 13 is formed. That is,
The depressurized atmosphere tank 20 maintains a depressurized state (vacuum state).

Then, the substrate 2 side of the bonded substrates under the above-mentioned condition is thinned by polishing. During the thinning polishing under the atmospheric pressure, the bonding surfaces 6, 7 of the substrates 1, 2 are always subjected to a positive pressure of about 1 atm. By the thinning polishing, the second moment of area of the substrate 2 gradually decreases,
In other words, the rigidity is lost, and finally, the bonding surfaces 6 and 7 of the substrates 1 and 2 start to come into close contact with each other over the entire surface. In this manner, the thinning polishing is continued until the bonding at the bonding surfaces 6 and 7 by the Van der Waals force is possible.

As shown in FIG. 14, thinning polishing is continued until the insulating layer 12 is exposed. In the above-described process, as a result, the micro exfoliated substrate composed of the substrate 2, that is, the bonded exfoliated substrate 3 is bonded to the bonding surface 6 which is a micro area of the substrate 1.

Further, in the next step, as shown in FIG. 15, the substrate 1 in a state where the bonded thinned substrate 3 is bonded
(In this case, the film is formed again so as to have the same structure as that of FIG. 9 except for the bonded thinning substrate 3) and the substrate 5 (FIG. 10).
3 has the same structure as the substrate 2 of FIG. 3, but has a structure which does not assume in-plane rotation like the substrate 2 of FIG. 3). 17). After joining the substrates 1 and 5, the removal area 22 on the substrate 5 side is removed by thinning polishing as shown in FIG. The substrate 5 loses its rigidity by the thinning polishing, and the bonding surface 7 of the substrate 5 and the surface of the bonded thinning substrate 3 are in close contact with each other over the entire surface, and are more firmly bonded (FIG. 18). At this time, there is no in-plane rotation between the substrate 1 and the substrate 5.

In this embodiment, the substrate 1 is an N-type InP semiconductor substrate, the substrate 2 is an N-type InP semiconductor substrate, and the substrate 5 is a P-type InP semiconductor substrate. The in-plane rotation angle θ between the substrate 1 and the substrate 2 is about 45 °, and the in-plane rotation angle θ between the substrate 2 (the bonded thinned substrate 3) and the substrate 5 is about 45 ° (that is, the plane of the substrate 1 and the substrate 5). The internal rotation angle θ was about 0 °). Si nitride as insulating layers 12 and 13
A film is used, Cr is used as the undercoat layers 14 and 15, Au (gold) is used as the bonding layers 16 and 17, and Au (gold) is used as the temporary bonding portion 18 and the main bonding portion 19. . When a voltage was applied (not shown) to the joined body of the substrates 1 and 5 produced by the above method and procedure as shown in FIG. 18, light emission could be observed.

In this embodiment, as the insulating film, Si nitride
Although a film is used, a Si oxide film or an Al oxide film may be used instead, and the purpose of the present invention is not changed at all.
In the present embodiment, the bonding step is performed at room temperature. However, after the lamination polishing, a heat treatment (a temperature of 350 ° C. or lower) for removing the strain of the bonded bonded lamination substrate 3 is performed. Is also good. Further, in the present embodiment, an InP substrate was used for the substrates 1, 2 and 5, but if necessary, a material other than InP, for example, GaAs, Si, GaN, Ge, Se,
ZnS, CdS, GaP, SiC, InAs, InS
b, PbS, or a combination of different materials of these materials (electrical bonding), or a combination of compound semiconductors formed on these semiconductor substrates (electrical bonding), or a mixed crystal Semiconductors, for example, InGaAsP, InGaAlP, GaIn
Bonding (electrical connection) by combining As or by combining these dissimilar materials is also possible, and the intention of the present invention does not change at all. These are the same in a second embodiment described later.

Second Embodiment FIGS. 1 to 4, FIGS. 9 to 14, and FIGS. 19 to 24 show the characteristics of the second embodiment of the present invention best. FIG. 19 is a cross-sectional view in which the semiconductor 4 is formed on the bonded thinned substrate 3, and FIG. 20 is one substrate 1 before the bonding after the semiconductor 4 is formed.
21 is a cross-sectional view of the two substrates 1 and 26 in an alignment state after the semiconductor 4 is formed and before bonding to another substrate 26. FIG. 23 is a cross-sectional view of the substrates 1 and 26 during application of a load, FIG. 23 is a cross-sectional view of the substrates 1 and 26 at the end of the application of the load, and FIG. It is sectional drawing at the time of grinding.

In the same figure, reference numeral 4 denotes a thin film layer formed on the bonded exfoliated substrate 3, reference numeral 26 denotes another substrate, and the same reference numerals as those in the first embodiment denote the same functional parts. .

Next, a method of manufacturing the above-described structure will be described. In the above configuration, a semiconductor substrate is used as one of the bonding substrates 1,
As shown in FIG. 9, an insulating layer 12 made of an electric insulating film is formed on the bonding region 10 around the bonding surface 6 by using a photolithography process using a resist mask.
On the undercoat layer 14, a bonding layer 16 made of a metal film is formed. Further, the bonding layer 1
1 and 9, a main joint 19 is formed concentrically around the bonding surface 6 by gold plating, and a temporary bonding is performed on the bonding layer 16 using a similar photolithography process. The part 18 is formed. At this time, as shown in FIG. 9, the height from the bonding layer 16 is formed so that the temporary bonding portion 18 is higher than the main bonding portion 19.

Next, a semiconductor substrate is used as the other bonding substrate 2, and the periphery of the coupling surface 7 for electrical coupling is etched in a concave shape by using a photolithography process using a resist mask. The coupling surface 7 is formed.
As shown in FIG. 10, a flat portion around the convex bonding surface 7 is defined as a bonding region 11, and an insulating layer 13 made of an electrical insulating film is formed on the bonding region 11. An undercoat layer 15 is formed, and a bonding layer 17 made of a metal film is formed on the undercoat layer 15. After the film formation, the substrates 1 and 2 are aligned by an alignment device (not shown) such that the bonding surfaces 6 and 7 face each other as shown in FIG. At this time,
The substrates 1 and 2 are twisted (in-plane rotation) by an angle θ with respect to each other as seen in FIG. Thus, when the bonding surfaces 6 and 7 are close to each other at an atomic level in order to obtain an electrical connection with each other, an interface dislocation depending on the twist angle θ is introduced at the interface between the bonding surfaces 6 and 7.

Thus, using the above alignment apparatus,
In the same manner as in the first embodiment, as shown in FIG.
7 are opposed to each other, and then a compressive load 21 is applied from both sides of the substrates 1 and 2. When the temporary bonding portion 18 of the substrate 1 and the bonding layer 17 of the substrate 2 are mechanically bonded to each other, the load 21 is released. In the next step, the temporarily bonded substrates 1 and 2 are introduced into a reduced pressure atmosphere (in vacuum), and the space between the substrates 1 and 2 is evacuated.
In the reduced pressure atmosphere, an applied load 21 is further applied from both sides of the substrates 1 and 2 as shown in FIG. According to the above process, as shown in FIG.
Bonding layers 17 obtain a mechanical bond with each other.

When the applied load 21 is further increased, the coupling surface 6 of the substrate 1 and the coupling surface 7 of the substrate 2 are very close to each other. At this time, when the applied load 21 is released, the substrate 1 and the substrate 2 are firmly mechanically joined together with the plastic deformation of the temporary bonding portion 18 and the main bonding portion 19,
The close distance between the substrate and the substrate 2 is maintained, and at the same time, a closed reduced-pressure atmosphere tank 20 as shown in FIG. 13 is formed.

Then, the substrate 2 side of the bonded substrates under the above-mentioned condition is thinned by polishing. Since the lamination is performed under the atmospheric pressure, the bonding surfaces 6 of the substrates 1 and 2
7 always receives a positive pressure of about 1 atmosphere. The rigidity of the substrate 2 is gradually lost by the thinning polishing, and finally, the bonding surfaces 6 and 7 of the substrates 1 and 2 start to come into close contact with each other over the entire surface.
In this way, the thinning polishing is continued until the bonding by Van der Waals force is possible. As shown in FIG. 14, the thinning polishing is continued until the insulating layer 12 is exposed on the surface. In the above process, the bonding surface 6 which is a minute area of the substrate 1
Thinned substrate composed of: a bonded thinned substrate 3
As a result. The above steps are substantially the same as in the first embodiment.

Further, in the next step, a thin film layer 4 is formed on the bonded sliced substrate 3 as shown in FIG. In the next step, as shown in FIG. 21, the substrate 1 in a state where the thin film layer 4 is formed on the bonded exfoliated substrate 3 (this is shown in FIG.
Is reconfigured as shown in FIG.
Bonding is performed in the same manner as described above (FIG. 21, FIG. 22, FIG.
3). After the bonding of the substrates 1 and 26, as shown in FIG. 23, the removal region 22 on the substrate 26 side is removed by thinning polishing. The substrate 26 gradually loses its rigidity by the thinning polishing, and finally, the thin film layer 4 existing on the substrate 1 and the bonding surface 7 of the substrate 26 start to come into close contact with each other over the entire surface. Thus, the thinning polishing of the substrate 26 is continued until the bonding by the Van der Waals force is possible. By the above method, the bonding surface 7 of the thin film layer 4 and the substrate 26 is in close contact with the entire surface and is more firmly joined (FIG. 24).

In this embodiment, the substrates 1 and 2 are made of N-type In.
The P semiconductor substrate and the substrate 26 were a P-type InP semiconductor substrate, and the thin film layer 4 was formed of InGaAsP. The in-plane rotation angle θ between the substrate 1 and the substrate 2 was about 45 °, and the in-plane rotation angle θ between the substrate 1 and the substrate 26 was about 0 °. Then, a silicon oxide film is used as the insulating layers 12 and 13, and the undercoat layer 1 is used.
Cr is used as 4 and 15, and A is used as bonding layers 16 and 17.
u (gold) is used, and further, Au (gold) is used as the temporary bonding portion 18 and the main bonding portion 19. When a voltage was applied (not shown) to the joined body of the substrates 1 and 26 manufactured by the above method and procedure as shown in FIG. 24, light emission could be observed.

Also in this embodiment, the bonding step is performed at room temperature. However, after the lamination, the heat treatment for removing the distortion of the bonded lamination substrate 3 is performed at a low temperature (35 degrees).
(A temperature of 0 ° C. or less). In this embodiment, the InP substrate is used for the substrates 1, 2, and 26, but the same material as that described in the first embodiment may be used if necessary.

[0048]

As described above, according to the present invention, the substrates which have been rotated in-plane with each other are joined together with a mechanical joint strength at the joints, and the electrical coupling surfaces are electrically coupled. . At least one of the substrates is thinned and polished so that the rigidity of the substrate is lost and the entire surface of the electrical connection surface can be intimately bonded. Therefore, interfacial dislocations generated between the substrates are bonded and thinned. It can be brought to the surface of the substrate.

More specifically, mechanical bonding strength is obtained at the main joint using an adhesive between the substrates rotated in-plane with each other, and at the same time, the space including the electrical connection surface forms a closed space with the main joint. Form. Because the enclosed space is a reduced pressure atmosphere tank,
In the atmosphere, it is constantly under a pressure of about 1 atmosphere. By thinning and polishing at least one of the substrates, the rigidity of the substrate is lost, and the entire surface of the electrical coupling surface can be intimately bonded, and further, another mixed crystal semiconductor film or other Since the above methods are used to form or combine the semiconductors, respectively, the alignment of the two substrates can be performed at room temperature and in the air. 2. It is possible to make the region where the electrical coupling surface exists a reduced-pressure atmosphere. 3. By thinning and polishing the bonded substrate, even if there are a plurality of finely bonded thinned substrates, they can be electrically connected to another semiconductor substrate at the same time. 4. When the bonded thinning substrate is further thinned,
Interfacial dislocations occurring between the substrates can be brought to the surface of the bonded exfoliated substrate.

[Brief description of the drawings]

FIG. 1 is a plan view of an element structure of one substrate before bonding according to first and second embodiments of the present invention.

FIG. 2 is a plan view of the element structure of another substrate before bonding according to the first and second embodiments of the present invention.

FIG. 3 is a plan view of an element structure of another substrate before bonding according to the first and second embodiments of the present invention.

FIG. 4 is a plan view showing in-plane rotation between substrates during bonding according to the first and second embodiments of the present invention.

FIG. 5 shows a substrate surface (100) according to the first embodiment of the present invention.
FIG. 3 is a view showing an atomic site of FIG.

FIG. 6 is a diagram showing interfacial dislocations at the time of substrate bonding according to the first embodiment of the present invention.

FIG. 7 is a diagram showing interfacial dislocations at the time of substrate bonding according to the first embodiment of the present invention.

FIG. 8 is a diagram showing interface dislocations at the time of substrate bonding according to the first embodiment of the present invention.

FIG. 9 is a cross-sectional view of FIG.

10 is a cross-sectional view as viewed from the arrow B in FIG. 2 and a cross-sectional view as viewed in the direction of arrow C in FIG. 3;

FIG. 11 is a cross-sectional view of both substrates in an alignment state before bonding according to the first and second embodiments of the present invention.

FIG. 12 is a cross-sectional view of both substrates during application of a load according to the first and second embodiments of the present invention.

FIG. 13 is a cross-sectional view of both substrates at the end of load application according to the first and second embodiments of the present invention.

FIG. 14 is a cross-sectional view showing a state in which both substrates are bonded and thinned and polished according to the first and second embodiments of the present invention.

FIG. 15 is a cross-sectional view of an alignment state before bonding between the bonded thinned substrate and another substrate before bonding according to the first embodiment of the present invention.

FIG. 16 is a cross-sectional view of the substrates in the alignment state shown in FIG. 15 while a load is being applied to the substrates;

17 is a cross-sectional view of the substrates in the alignment state of FIG. 15 at the end of the application of a load between the substrates.

18 is a cross-sectional view of another substrate after the application of the load shown in FIG. 17 is finished and the other substrate is polished.

FIG. 19 is a sectional view showing a semiconductor film formed on a bonded exfoliated substrate according to a second embodiment of the present invention.

FIG. 20 is a diagram illustrating a semiconductor device according to a second embodiment of the present invention.
It is sectional drawing of the element structure of one board | substrate before joining.

FIG. 21 is a cross-sectional view of both substrates in an alignment state after a semiconductor film is formed and before bonding with another substrate according to the second embodiment of the present invention.

FIG. 22 is a cross-sectional view of both substrates during application of a load after semiconductor film formation according to the second embodiment of the present invention.

FIG. 23 is a cross-sectional view of both substrates at the time of completion of load application after semiconductor film formation according to the second embodiment of the present invention.

FIG. 24 is a cross-sectional view of a semiconductor device according to a second embodiment of the present invention, in which the two substrates are bonded together and then sliced and polished.

[Explanation of symbols]

 1, 2, 5, 26 substrate 3 bonded exfoliated substrate 4 thin film layer 6, 7 bonding surface 8, 9 atoms 10, 11 bonding region 12, 13 insulating film 14, 15 undercoat layer 16, 17 bonding layer 18 temporary bonding Part 19 Main joint 20 Decompression atmosphere layer 21 Applied load 22 Removal area

Claims (22)

[Claims] 1. A bonding method for obtaining electrical coupling by bonding in a small region between semiconductor substrates of the same type or different types, wherein a mechanical bonding force is formed between a bonding region in which electrical coupling occurs and a substrate. A structure having a bonding region having a bonding portion for providing is formed on the first and second semiconductor substrates, and the bonding regions on the first and second semiconductor substrates and the bonding regions are opposed to each other. After at least one of the semiconductor substrates is rotated in-plane while being aligned so as to perform alignment, the bonding portions are bonded to each other while applying a pressing force to the first and second semiconductor substrates, and the bonding regions are bonded to each other. Are electrically coupled by solid-phase bonding, and after the solid-phase bonding, at least one of the semiconductor substrates is sliced and polished to form a sliced substrate. Substrate characterized by realization of mechanical bonding Minute domains solid phase bonding method. 2. The semiconductor device according to claim 1, wherein the first and second semiconductor substrates are configured such that a sealed atmosphere tank including a bonding region therein is formed by bonding between bonding portions on the bonding region. Item 3. The method for solid-state bonding between substrates in a minute region according to Item 1. 3. The method according to claim 1, wherein the bonding between the bonding portions on the bonding region of the first and second semiconductor substrates is performed in a reduced-pressure atmosphere so that the sealed atmosphere tank becomes a reduced-pressure atmosphere tank. 3. The method for solid-state bonding between micro substrates between substrates according to 2. 4. A bonding portion comprising an adhesive having a concentric saw-tooth (irregular shape) cross-section so as to surround the bonding region in the bonding region of at least one semiconductor substrate. 4. The method for solid-state bonding of minute regions between substrates according to claim 2 or 3. 5. The method according to claim 1, wherein a thin film layer made of a semiconductor is further formed on the exfoliated substrate. 6. The semiconductor thin film layer is made of InGaAs.
6. The method according to claim 5, wherein the method is a mixed crystal semiconductor of P, InGaAlP or GaInAs. 7. A third semiconductor substrate, wherein the thinned substrate or the thinned layer on which the thin film layer is formed is electrically coupled in a very small area to a coupling region of the first or second semiconductor substrate. After the bonding regions are aligned so that the bonding regions formed on these semiconductor substrates face each other and the bonding regions face each other, a pressing force is applied to these semiconductor substrates to form a bonding portion of the bonding regions. 7. The method according to claim 1, wherein the electrical connection is further performed by bonding the substrates to each other. 8. The sealed atmosphere tank including the bonding region therein is formed by bonding the bonding portions on the bonding region to the semiconductor substrate and the third semiconductor substrate electrically connected to the thinning substrate. 8. A structure according to claim 7, wherein
The solid-state bonding method for micro regions between substrates described in the above. 9. The method according to claim 8, wherein the bonding between the bonding portions on the bonding region of the two substrates is performed in a reduced pressure atmosphere so that the closed atmosphere tank becomes a reduced pressure atmosphere tank. Small-area solid-state bonding method. 10. The method according to claim 9, wherein the reduced-pressure atmosphere in the reduced-pressure atmosphere tank is a reduced-pressure air atmosphere, an inert gas atmosphere, or a reducing gas atmosphere. 11. The substrate according to claim 10, wherein the reduced-pressure atmosphere in the reduced-pressure atmosphere tank is an atmosphere of reduced-pressure argon gas, nitrogen gas, hydrogen gas or a mixed gas of these gas types. Small-area solid-state bonding method. 12. The inter-substrate according to claim 7, wherein at least one of the semiconductor substrates is rotated in a plane at the time of bonding between the thinned substrate and the third semiconductor substrate. Small-area solid-state bonding method. 13. A temporary bonding portion is further formed on at least one of the semiconductor substrates, and after both substrates are temporarily bonded at the temporary bonding portion while applying a pressing force between the substrates after the alignment,
13. The solid-state bonding method according to claim 1, further comprising bonding the bonding portions while applying a pressing force to the substrates. 14. The semiconductor substrate according to claim 1, wherein said semiconductor substrate is Si, InP, Ga.
As, GaN, Ge, GaP, ZnS, CdS, InA
s, InSb, SiC, PbS, Se, and compound semiconductors formed on any of these semiconductor substrates,
14. The microregion solid-state bonding method between substrates according to claim 1, wherein the substrate is one of a mixed crystal semiconductor of nGaAsP, InGaAlP, and GaInAs. 15. The method according to claim 1, wherein a convex electric coupling surface is formed in at least one coupling region of the semiconductor substrate. 16. The method according to claim 1, wherein the joining portion is made of a material having a plastic deformation ability. 17. The method according to claim 16, wherein the material having plastic deformability is a metal material. 18. A metal material having plastic deformability is Al, A
18. The microregion solid-state bonding method between substrates according to claim 17, wherein the compound is any one of u, Sn, Cu, Zn, Pb, Ni, and a PbSn compound. 19. The method according to claim 1, wherein the bonding temperature is 350 ° C. or lower or room temperature. 20. A method for joining a substrate on which a light emitting element is formed and a substrate on which a mirror for forming a laser beam is formed,
20. The method according to claim 1, wherein the bonding is performed in a small area by using a structure having a bonding region where an optical coupling and an electrical coupling are generated and a bonding region having a bonding portion for providing a bonding force. The method for solid-state bonding of minute regions between substrates according to any one of the above. 21. The method for solid-state bonding between substrates according to claim 1, comprising a plurality of bonding regions and a plurality of bonding regions for forming a plurality of electrical connections on the same substrate. 22. A bonding portion for providing a mechanical bonding force between a coupling region for producing an electrical coupling and a mechanical bonding force between the substrates in order to obtain an electrical coupling in a small region between the same or different semiconductor substrates. A structure having a bonding region having the following structure is formed on the first and second semiconductor substrates. The bonding region and the bonding region are formed such that the bonding regions and the bonding regions on the first and second semiconductor substrates are in phase with each other. When at least one of the semiconductor substrates is brought into a state of being rotated in the plane while being aligned so as to face each other, and when the joining portions are joined while applying a pressing force to the first and second semiconductor substrates, The bonding regions are shaped so as to be electrically coupled by solid-phase bonding, and after the solid-phase bonding, at least one semiconductor substrate is thinned and polished to be a thinned substrate. Small area with interfacial dislocations up to the surface Element structure, characterized in that electrical connection is realized in.