JP2000183283A - Laminated-type circuit module and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a laminated-type circuit module whose latitude for arrangement can be enhanced, without being restricted by the arrangement of electrodes, the size of parts, or the like and at the same time can be miniaturized, and its manufacturing method. SOLUTION: Wirings 2 and 3 are formed on a wiring substrate 1, an insulation layer 8 is formed on it, and a bare chip 12 is incorporated into the insulation layer 8, while being electrically connected to the wiring 2 and 3. Wiring 10 and 11 is formed on the upper surface of the insulation layer 8, and an insulation layer 9 is laminated on the insulation layer 8. A bare chip 16 is incorporated into the insulation layer 9 while it is electrically connected to the wiring 10 and 11, and feedthrough electrodes 21 and 22 are incorporated into the insulation layer 8, while being electrically connected to the wiring 2, 3, 10, and 11. By arranging the wiring and bare chip in build-up structure, the arrangement of electrodes and the size of parts cannot be restricted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a laminated circuit module in which components such as bare chips are stacked and arranged, and a method of manufacturing the same.

[0002]

2. Description of the Related Art It is possible to reduce the size of a circuit board by laminating and mounting circuit components such as bare chips in a vertical direction. As such a lamination mounting method, for example, as shown in FIG. 13, a plurality of bare chips 100 in which wirings 100a and 100b are drawn out on a chip end face are stacked and a wiring 10 provided on the end face is provided.
There is a method of connecting chips at 1, 102, a method of mounting a bare chip on an interposer substrate, and a method of laminating the interposer substrate. This type of lamination method is called “A Re
view of 3-D Packaging Technology ”IEEE Transaction
s on components, packaging, and manufacturing techno
logy-part B, vol.21, No.1, Feb. 1998.

[0003]

However, FIG.
In many of the methods of directly stacking the bare chips 100 shown in (1), it is necessary to form a structure on the chip on which the electrodes are taken out on the chip end face, and it is difficult to apply the structure to an existing IC chip. Further, since the chips 100 to be stacked need to be the same size, they are not suitable for stacking chips of different sizes. Further, in the case of lamination using an interposer substrate, the size is increased by the size of the interposer substrate. As described above, in the conventional stacked mounting method, the size and the applicable IC
There are restrictions on chips, etc.

Accordingly, an object of the present invention is to provide a stacked circuit module which can be arranged with a high degree of freedom without being restricted by electrode arrangement and component size, and which can be miniaturized, and a method of manufacturing the same. It is in.

[0005]

According to a first aspect of the present invention, there is provided a laminated circuit module comprising: a first insulating layer formed on a first wiring; First component mounted in a state of being electrically connected, a second wiring formed on an upper surface of the first insulating layer, and a second insulating layer laminated on the first insulating layer Layer, a second surface-mounted component incorporated in the second insulating layer while being electrically connected to the second wiring, and electrically connected to the first and second wirings in the first insulating layer. And a feed-through electrode incorporated in a connected state.

By adopting such a configuration, the first and second surface-mounted components electrically connected to the wiring are built in the first and second insulating layers laminated, and The first surface-mounted component and the second surface-mounted component are electrically connected through a feedthrough electrode built in the layer.

Accordingly, the conventional bare chip 1 shown in FIG.
In the structure of directly laminating 00, it is necessary to build a structure for taking out electrodes on the chip end face on the chip, it is difficult to apply it to an existing IC chip, and the laminated chips need to be the same size and differ. It is not suitable for stacking chips of a size, and further, in stacking using an interposer substrate, the size is increased by the size of the interposer substrate. On the other hand, in the present invention, by arranging the wiring and the components in the build-up structure, it is necessary to provide a special structure for connecting the components to the component (a structure in which the electrodes are taken out from the chip end face is formed on the chip). ), It can be easily applied to existing IC chips, the chips to be stacked need not be the same size, chips of different sizes can be stacked and arranged, and furthermore, miniaturization can be achieved without an interposer substrate.

In this way, the degree of freedom in arrangement can be increased without being restricted by the arrangement of electrodes and component sizes, and the size can be reduced. Here, as described in claim 4, the feed-through electrode is:
If the top is thinner than the bottom, it is less likely to buckle.

Further, according to the method of manufacturing a laminated circuit module according to the fifth aspect, the base material having the first wiring formed on the upper surface is connected to the first wiring in a state of being electrically connected to the first wiring. One surface mount component is mounted, and a feedthrough electrode is arranged on the first wiring. Then, the first insulating layer is laminated on the base material with the upper surface of the feedthrough electrode exposed. Further, a second wiring electrically connected to the feed-through electrode is formed on the upper surface of the first insulating layer. Then, on the first insulating layer,
The second surface mount component is mounted in a state where it is electrically connected to the second wiring, and the second insulating layer is stacked on the first insulating layer. As a result, the multilayer circuit module according to the first aspect is obtained.

Here, according to the method of manufacturing a laminated circuit module according to the sixth aspect, the resin having fluidity is disposed, and the fluid resin is used to contact the upper portion of the feed-through electrode with the mold using the mold. Until the fluid resin is cured and the mold material is peeled off. Thus, the insulating layers are stacked.

Further, when a release layer is formed on the surface of the mold material, the mold material can be easily separated by interposing the release layer. Further, as described in claim 8, when a material that contracts in volume by curing is used as the fluid resin, the tip of the feedthrough electrode projects from the resin portion due to the volume contraction when the fluid resin is cured. It is formed.

According to a ninth aspect of the present invention, after the mold material is peeled off, the surface of the resin is ashed or the surface of the resin is mechanically polished, so that the resin remaining on the feedthrough electrode is removed. Electrical connection can be ensured.

When fine irregularities are formed on the surface of the mold material, the fine irregularities are transferred to the surface of the feed-through electrode, and the adhesion to the wiring disposed thereon is improved. I do.

According to a twelfth aspect of the present invention, when a convex portion for forming a component placement space is formed on the surface of the mold material, a space is formed in the insulating layer by the convex portion of the mold material, and electronic components are arranged in this space. can do.

According to a thirteenth aspect, when a projection for adjusting the thickness of the insulating layer is formed on the surface of the mold,
The thickness of the insulating layer can be adjusted by the projections of the mold. As described in claim 14, when an epoxy-based resin is used as the fluid resin, a volatile component is reduced and cavities (cavities) are less likely to be generated as compared with a case where a polyimide-based resin is used.

When a bare chip is used as a surface mounting component, the component can be made thinner and the insulating layer can be made thinner. Therefore, the feedthrough electrode can be reduced, and the aspect ratio can be reduced. As a result, the electrodes can be made smaller and the pitch can be made smaller.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) A first embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 to FIG. 4 are manufacturing process diagrams of the laminated circuit module in the present embodiment. In FIG. 4C,
1 shows an overall configuration of a laminated circuit module. Specifically, the entire configuration of the circuit module in a state where only two insulating layers (8, 9) are stacked is shown.

In FIG. 4C, first wirings (conductor patterns) 2 and 3 are formed on the wiring board 1, and the wirings 2 and 3 are passed through through holes 4 and 5 to form electrode terminals (rear surfaces) on the rear surface. (Conductor pattern) 6,7. The electrode terminals 6 and 7 are used to connect the finally completed circuit module to another circuit. In addition, wirings 2 and 3
An interlayer insulating layer (first insulating layer) 8 is formed on the wiring board 1 including the above, and an interlayer insulating layer (second insulating layer) 9 is laminated thereon. Second wirings (conductor patterns) 10 and 11 are formed on the upper surface of the insulating layer 8.

The insulating layer 8 has a built-in bare chip 12 as a first surface mount component. Bare chip 12
The bump electrodes 13 and 14 are formed on the lower surface of the substrate, and the bump electrodes 13 and 14 are formed by a resin 15 disposed below the bare chip 12.
14 is in contact with the wirings 2 and 3. As described above, the bare chip 12 is incorporated in the insulating layer 8 in a state of being electrically connected to the wirings 2 and 3.

Similarly, the insulating layer 9 has a built-in bare chip 16 as a second surface mount component. Bump electrodes 17 and 18 are formed on the lower surface of the bare chip 16, and the bump electrode 1 is formed by a resin 19 disposed under the bare chip 16.
7 and 18 are in contact with the wirings 10 and 11. Thus, the bare chip 16 is incorporated in the insulating layer 9 in a state of being electrically connected to the wirings 10 and 11.

Further, stud bumps 20 a and 20 b are stacked on the wiring 2 inside the insulating layer 8, and the stud bump 20 b is in contact with the wiring 10. The stud bumps 20a and 20b form a feed-through electrode 21, and the feed-through electrode 21 has a structure in which the feed-through electrode 21 is electrically connected to the wiring 2 and the wiring 10 and is embedded in the insulating layer 8. Similarly, stud bumps 22 a and 22 b are stacked on the wiring 3 inside the insulating layer 8, and the stud bump 22 b is in contact with the wiring 11. The stud bumps 22a and 22b form a feed-through electrode 23, and the feed-through electrode 23 is electrically connected to the wiring 3 and the wiring 11 while the insulating layer 8 is formed.
It has a built-in structure. The bare chips 12 and 16 are electrically connected through the feedthrough electrodes 21 and 23 and the wirings 2, 3, 10 and 11.

On the other hand, stud bumps 24a and 24b are stacked on the wiring 10 inside the insulating layer 9,
On the wiring 11, stud bumps 26a, 26b
Are piled up. Stud bumps 24a, 24b
And 26a, 26b constitute feed-through electrodes 25 and 27.

The feedthrough electrodes 21, 23, 2
5 and 27 are located near the bare chips 12 and 16. Although the wiring board 1 functions as a base material of the module, the wiring board 1 may be implemented without the wiring board 1 with respect to the multilayer circuit module shown in FIG.

Next, a description will be given of a method of manufacturing the laminated circuit module configured as described above. First, as shown in FIG. 1A, a wiring board 1 as a base material is prepared. Through holes 4 and 5 are formed in the wiring board 1, wirings 2 and 3 are formed on the surface (upper surface) of the substrate 1, and electrode terminals 6 and 7 are formed on the back surface (lower surface).

Then, as shown in FIGS. 1B and 1C, a bare chip 12 having bump electrodes 13 and 14 is prepared, and the bare chip is placed in a state where the bump electrodes 13 and 14 are positioned on the wirings 2 and 3. 12 is mounted face down with FC. As a mounting method, an anisotropic conductive paste (AC) in which a large number of conductive fillers are mixed in a thermosetting epoxy resin.
P) 30 is used. That is, as shown in FIG.
An appropriate amount of the anisotropic conductive paste 30 is applied to a predetermined position of the wiring board 1, and the bare chip 12 is placed face down as shown in FIG. Furthermore, while applying a pressure of several tens of grams per bump from the back surface of the chip,
A curing treatment is performed at 180 ° C. for several tens of seconds.

Subsequently, as shown in FIG. 1D, the stud bumps 20a, 20b and 22a, 22b are arranged on the wirings 2, 3 on the upper surface of the wiring board 1 so as to vertically overlap. In this manner, the high aspect ratio electrodes (20a, 2a) to be the feedthrough electrodes 21, 22 are formed.
0b, 22a, 22b).

FIG. 1D shows a case where two stud bumps are arranged in an overlapping manner, but the number is arbitrary. That is, the height h of the feed-through electrodes 21 and 23 (the stacked stud bumps 20a and 20b and 22a and 22b)
Is a value obtained by adding about 50 μm to the thickness t1 of the bare chip 12 including the bump electrodes 13 and 14. Specifically, the thickness of the bump electrodes 13 and 14 of the bare chip 12 is set to 30 μm.
m and the thickness of the chip 12 is 100 μm, the height h of the feedthrough electrodes 21 and 23 is 180 μm. In order to reduce the size, it is desirable that the feed-through electrodes 21 and 23 be installed as close to the bare chip 12 as possible.

If the thickness t1 of the bare chip 12 including the bump electrodes 13 and 14 is, for example, about 50 μm or less, a normal stud bump (one stud bump) is used as a feed-through electrode.

In this way, the bare chip 12 is mounted on the wiring board 1 while being electrically connected to the wirings 2 and 3, and the feed-through electrodes 21 and 23 are arranged on the wirings 2 and 3. . The order of the FC mounting and the step of forming the feed-through electrode may be reversed. That is, after forming the feed-through electrodes 21 and 23, the bare chip 12 may be mounted.

Subsequently, as shown in FIG. 2A, the upper surface of the wiring substrate 1, that is, the surface on which the FC mounting and the formation of the feed-through electrodes 21 and 23 are performed, is coated with an epoxy resin-based prepolymer (before curing). A resin 31 in a state of high fluidity is applied. Then, as shown in FIG. 2 (b), the prepolymer 31 is flattened and cured as shown in FIG. 2 (c), thereby forming the interlayer insulating layer 8 as shown in FIG. 3 (a).
To form In the present embodiment, the epoxy resin-based prepolymer 31 is used as a material having fluidity (fluid resin) and contracting in volume upon curing.

The step of flattening and curing the prepolymer 31 will be described in detail. As shown in FIG. 2B, a glass substrate 32 having a flat surface is prepared as a mold material. A silicone-based or Teflon-based release layer 33 is formed on the surface of the glass substrate 32. Then, the release layer 33 of the pressing glass substrate 32 is placed so as to face the upper surface of the substrate 1 on which the prepolymer 31 is applied, and the prepolymer 31 is pressed by moving the glass substrate 32 downward. In the pressing, the release layer 33 of the glass substrate 32 comes into contact with the upper portions of the feed-through electrodes 21 and 23, and the upper portions of the feed-through electrodes 21 and 23 are crushed and deformed to several tens to 100 μm in diameter (W value in the drawing). Do until. When the prepolymer 31 and the feed-through electrodes 21 and 23 are pressed, it is desirable to apply a force only in the vertical direction to avoid buckling of the feed-through electrodes 21 and 23.

As a result, the bare chip 12 and the feed-through electrodes 21 and 23 are buried with the resin (prepolymer) 31 having fluidity before curing, and the surface thereof is flattened.

Thereafter, as shown in FIG. 2C, the prepolymer 31 is cured by heating while being pressed, and the interlayer insulating layer 8 is formed. Curing conditions are, for example, 150 ° C.
180 ° C. for about 60 seconds. In this curing, the tips of the feed-through electrodes 21 and 23 project from the resin layer 8 due to the volume shrinkage of the resin.

Further, the pressing glass substrate 32 is peeled off from the surface of the interlayer insulating layer 8. As a result, the result is as shown in FIG. Since the release layer 33 is interposed between the glass substrate 32 and the interlayer insulating layer 8, the peeling can be easily (easily) performed by applying a very small external force. The surface of the interlayer insulating layer 8 after peeling has the same level of flatness as the surface of the glass substrate 32. Also, feed-through electrode 2
In the upper portions of the first and second electrodes 23 and 23, the epoxy resin is almost completely removed between the feed through electrodes 21 and 23 and the glass substrate 32, and the feed through electrodes 21 and 23 are exposed.

In this way, the insulating layer 8 is laminated on the wiring board 1 with the upper surfaces of the feed-through electrodes 21 and 23 exposed. Next, the feedthrough electrodes 21 and
3 and a second-layer wiring 1 to be formed thereafter as shown in FIG.
To ensure (completely) electrically connect 0 and 11, a small amount of epoxy resin remaining on the feed-through electrodes 21 and 23 is removed. Specifically, the entire surface of the interlayer insulating layer 8 is ashed with oxygen plasma.

Instead of the ashing treatment of the surface of the resin, the surface of the cured epoxy resin may be mechanically polished to surely remove the resin remaining on the feed-through electrodes 21 and 23. . Also in this case, prepolymer 3
By selecting a material having a relatively large volume shrinkage upon curing as described above, the feed-through electrode 2
The top ends of the feedthrough electrodes 21 and 23, which are easy to protrude from the surface of the resin portion (the interlayer insulating layer 8) and slightly project from the other portions, can be polished with a flat polishing table. , Feed-through electrodes 21 and 23
The epoxy resin remaining on the upper portion can be selectively removed.

Then, as shown in FIG. 3B, a wiring material 34 is formed on the entire surface of the insulating layer 8 by vapor deposition.
As shown in (c), patterning is performed by an etching process. The process temperature is 25 considering the heat resistance of the epoxy.
The upper limit is about 0 ° C. Thereby, the second-layer wirings 10 and 11 electrically connected to the feed-through electrodes 21 and 23 are formed on the upper surface of the insulating layer 8.

Thereafter, as shown in FIG. 4A, the bare chip 16 is mounted by FC in the same manner as in the first layer. That is, the bare chip 16 is mounted on the insulating layer 8 while being electrically connected to the wirings 10 and 11.

Thereafter, as shown in FIG. 4B, feed-through electrodes 25 and 27 are formed in the same manner, and as shown in FIG.
As shown in (c), the insulating layer 9 is laminated on the insulating layer 8 by embedding with an epoxy resin. 4A to 4C.
The circuit module is completed by repeating the steps of chip mounting, electrode formation and resin filling shown in (1). In the state of FIG. 4 (c), the wirings 2, 3, 1
Bare chips 12 and 16 electrically connected to 0 and 11 are built in, and bare chips 12 and 1 are passed through feed-through electrodes 21 and 23 built in insulating layer 8.
6 are electrically connected.

Here, the fluid resin (prepolymer 31)
Since the epoxy resin is used, the volatile component is small and cavities (cavities) are less likely to occur as compared with the case where a polyimide resin is used. In addition, bare chip 1 as a surface mount component
Since 2,16 are used, the surface mount components can be made thinner,
The insulating layers 8 and 9 can also be made thin. Therefore, the feedthrough electrodes 21, 23, 25, and 27 can be reduced, and the aspect ratio can be reduced. As a result, the electrodes 21, 23, 25, 27
And the pitch can be narrowed.

Further, by forming a laminated structure by the above-described manufacturing method, it is possible to freely lay out wiring between chips without using an interposer substrate. Further, when formed by this method, the layer thickness per layer can be increased by adding several tens of μm to the thickness of the bare chip, so that the size in the thickness direction can be reduced much more than when an interposer substrate is used. In addition, since the chip is mounted by using the conventional FC mounting, it is not necessary to provide a special structure on the chip itself, and a normal bare chip can be used as it is.

Further, in the present manufacturing method, as shown in FIG. 3A, since the insulating layer 8 is formed and at the same time the feedthrough electrodes 21 and 23 can be taken out from the surface of the insulating layer 8, the manufacturing process can be simplified.

As described above, this embodiment has the following features. (A) By arranging the wiring and the bare chip in a build-up structure, the degree of freedom of the arrangement can be increased without being restricted by the electrode arrangement and the component size, and the size can be reduced. In other words, in the structure shown in FIG. 13, it is necessary to form a structure for taking out electrodes on the chip end face on the chip, it is difficult to apply the structure to an existing IC chip, and the stacked chips need to be the same size and differ. It is not suitable for stacking chips of a size, and further, in stacking using an interposer substrate, the size is increased by the size of the interposer substrate. On the other hand, in the present embodiment, the present invention can be easily applied to an existing IC chip without providing a special structure for connection to the bare chip (there is no need to build a structure for taking out electrodes on the chip end surface on the chip). Also, the chips 12 and 16 to be stacked need not be the same size, and chips of different sizes can be stacked and arranged, and further, miniaturization can be achieved without an interposer substrate. (Second Embodiment) Next, a second embodiment will be described with reference to the first embodiment.
The following description focuses on the differences from this embodiment. 5 to 7
1 shows a manufacturing process diagram of the multilayer circuit module in the present embodiment.

In the first embodiment, the stud bumps 20a, 20b, 22a, 22b, 2
4a, 24b, 26a, and 26b were used, and vapor deposition and etching were used for wiring formation. In contrast,
In the present embodiment, JPS (Jet Printing System) is used. JPS is capable of forming ultrafine particles of several tens μm to 100 μm
This is a method of drawing by spraying a predetermined minute position of a substrate from a fine nozzle at a high speed. As described above, in the present embodiment, the JPS electrodes 40, 41, 42, and 43 are used as the feed-through electrodes as shown in FIG.
The shape of the feed-through electrodes 40 to 43 is thinner at the top than at the bottom, and has a structure that is less likely to buckle. In addition, the feedthrough electrodes 40 to 4 are formed by using JPS.
3 and bumps 44, 45, 46, 47 and wiring 4
8, 49, 50 and 51 are collectively formed.

The feed-through electrode, wiring,
Batch formation of bumps is performed as shown in FIG. First, FIG.
As shown in (a), wirings 2, 3 and electrode terminals 6, 7
Is prepared. Then, as shown in FIG. 5B, the wiring substrate 1 is fixed to the XY stage 55 in the JPS device, and is heated to 100 to 250 ° C. this is,
This is for improving the adhesion of the formed electrode. JPS
The Au ultra-fine particles 56 formed in the ultra-fine particle generation chamber (not shown) of the apparatus are directly above the XY stage 55,
It is jetted at high speed from the nozzle 57 having a diameter of 100 μm which is separated by about 00 μm to the wiring board 1. The ultrafine particles 56 that have collided with the wiring substrate 1 at high speed are deposited on the wiring substrate 1 to form an Au thin film.

At this time, X is injected simultaneously with the injection of the ultrafine particles 56.
By moving the Y stage 55, an arbitrary wiring pattern can be formed. In addition, the feedthrough electrodes 40 and 41 and the bumps 4 are provided at arbitrary positions on the wirings 48 and 49.
4, 45 are formed. This formation is performed by stopping the XY stage 55 with the ultrafine particles 56 being jetted. That is, the feed-through electrodes 40 and 41 and the bumps 44 and 45 can be formed by forming the ultrafine particles 56 so as to stand perpendicular to the wiring substrate 1. The height of these electrode portions is adjusted by the stop time of the XY stage 55.

With such a forming method, as shown in FIG. 5C, the feedthrough electrode 4 having a height of about 400 μm is formed.
0, 41 can be formed at a narrow pitch of 200 μm or less. Thereafter, similarly to the first embodiment, FC mounting and embedding with epoxy resin are performed to complete a circuit module. That is, as shown in FIG.
And a prepolymer 31 as shown in FIG.
Are arranged, pressed by the substrate 32, and further subjected to a curing process.
Then, as shown in FIG.
Then, as shown in FIG. 7A, feed-through electrodes 42 and 43, wirings 50 and 51, and bumps 46 and 47 are formed by the JPS. Thereafter, as shown in FIG. 7 (b), the bare chip 16 is mounted, and as shown in FIG. 7 (c), the interlayer insulating layer 9 is arranged and pressed by the substrate.
Harden. Thereafter, the same operation is performed.

As described above, in the first embodiment, the stud bumps 20a, 20b, 22a, 2
2b, 24a, 24b, 26a, 26b were stacked vertically, but in this case, it was difficult to arbitrarily set the height h of the feed-through electrode. In contrast, in the present embodiment, J
By using PS, feed-through electrodes 40 to 43 having an arbitrary height can be easily obtained, and the degree of freedom of manufacturing conditions is increased.

The use of the JPS makes it possible to omit the mask process for forming the wirings (patterns) 10 and 11 required in the first embodiment. In addition, the bump forming step can be omitted from the chip-side manufacturing process because the bumps required for FC mounting of the bare chips 12 and 16 can be formed simultaneously with the wiring formation on the substrate 1 side.

Further, by directly drawing the wiring and the feed-through electrode, the photo step and the etching step can be eliminated, and the manufacturing process can be greatly simplified and the number of trial manufacturing steps can be reduced.

As an application example of this embodiment, the feed-through electrodes may be arranged by a printing method instead of JPS. (Third Embodiment) Next, a third embodiment will be described with reference to a second embodiment.
The following description focuses on the differences from this embodiment. In FIG.
FIG. 4 shows a manufacturing process diagram of the laminated circuit module in the present embodiment.

In this embodiment, the surface of the pressing substrate 60 used for pressing the prepolymer is roughened. This is for the purpose of improving the adhesiveness of the wiring material of the second and subsequent layers formed on the epoxy layer.

As shown in FIG. 8A, the surface of the pressing substrate 60 as a mold material is roughened to form fine irregularities 60a. After that, a release layer 61 is formed. The prepolymer 31 is pressed by the substrate, and the prepolymer 31 is further cured. Then, as shown in FIG. 8B, the pressing substrate 60 is peeled off. Then, the feedthrough electrode 4
0, 41 and the surface of the interlayer insulating layer 8
The unevenness similar to the unevenness 60a formed in the above is transferred (formed).

The surface roughening for the purpose of improving the adhesion can be performed by ashing or mechanical polishing of the surface of the epoxy layer by the oxygen plasma performed in the first embodiment. By using the method shown, surface roughening can be achieved more easily and with good reproducibility.

The method of roughening the surface of the pressing substrate 60 is as follows.
In addition, for example, when the pressing substrate 60 is a glass substrate, irregularities may be formed by dry etching using CF4 or forming a polysilicon film on the glass substrate and growing the polysilicon by grain growth by heat treatment. There is also a method of mechanically forming unevenness by a method such as sandblasting. (Fourth Embodiment) Next, a fourth embodiment will be described with reference to a second embodiment.
The following description focuses on the differences from this embodiment. 9 to 1
FIG. 1 shows a manufacturing process diagram of the multilayer circuit module in the present embodiment.

When actually configuring a circuit, it is often necessary to mount discrete components (functional components) such as capacitors for the purpose of bypass capacitors and smoothing capacitors in addition to bare chips. While the bare chip can be thinned to an arbitrary thickness of about several tens of μm by polishing the back surface, the discrete component has a specific thickness on the order of mm. If components having different thicknesses, such as a bare chip and a chip capacitor, are arranged on the same surface and the thickness of the insulating layer is adjusted to the thickness of the discrete component, it will be an obstacle to miniaturization. Also, the feedthrough electrode needs to be higher than the discrete component, and its formation is extremely difficult.

Therefore, when components of different heights are mixed, the following is performed. First, as shown in FIG. 9A, the substrate 1 on which the wirings 2, 3, 70 are formed is
As shown in FIG. 9B, feed-through electrodes 40 and 41, bumps 44 and 45, and wirings 48 and 49 are formed.
As shown in (c), the bare chip 12 is mounted. Thereafter, as shown in FIG. 10A, a convex portion 72 corresponding to the thickness of the epoxy layer after pressing is provided at a predetermined position (a discrete component mounting position) of the pressing substrate 71. In this way, as shown in FIG. 11A, the concave portion 73 for embedding the discrete component in the interlayer insulating layer 8 can be easily formed. Subsequently, as shown in FIG. 11B, wiring is formed in the concave portion 73, and a discrete component 74 is mounted with a resin 75 made of an anisotropic conductive paste (ACP).

Then, as shown in FIGS. 11C and 11D, wirings 50 and 51, bumps 46 and 47, feed-through electrodes 42 and 43 are formed, and the second-layer bare chip 16 is mounted. Further, the discrete component 74 is completely embedded in the interlayer insulating layer 9. In this manner, components 12 (16) and 74 having different thicknesses can be efficiently laminated.

As described above, in the present embodiment, FIG.
As shown in FIG. 7, a mold 71 having a convex portion 72 for forming a component placement space formed on the surface thereof is used. Therefore, a concave portion 73 is formed in the insulating layer 8 by the convex portion 72 of the mold material. An electronic component 74 can be arranged in the space 73. (Fifth Embodiment) Next, a fifth embodiment will be described with reference to a fourth embodiment.
The following description focuses on the differences from this embodiment. FIG. 12 shows a manufacturing process diagram of the multilayer circuit module in the present embodiment. In the present embodiment, the protrusions 72 of FIG. 10 are arranged at several places in the periphery of the chip arrangement region to form spacers for keeping the thickness of the interlayer insulating layer 31 uniform in the plane.
That is, in the embodiments described above, the film thickness of the interlayer insulating layers 8 and 9 is
5, 27, 40 to 43 were determined using spacers. However, when the density of the feed-through electrode is low or the distribution is extremely non-uniform, it becomes difficult to keep the thickness of the interlayer insulating layers 8 and 9 uniform with the feed-through electrode. In this case, as in the present embodiment shown in FIG.
Are placed evenly. Thereby, uniformity of the film thickness of the interlayer insulating layer can be easily ensured.

As described above, in the present embodiment, the shape 7
Since the convex portions 80 for adjusting the thickness of the insulating layer are formed on the surface of the substrate 1, the thickness of the insulating layer can be easily adjusted by the convex portions 80 of the mold.

In addition to those described above, the present invention may be carried out as follows. In the first to fifth embodiments, a thermosetting epoxy resin is used as the interlayer insulating material. However, a resin material other than a photocurable resin or epoxy can be widely used.

In the embodiments described above, the FC mounting is performed face down, but it is also applicable to face up. Furthermore, in the embodiments described so far, a description of one circuit module is described, but a plurality of circuit modules are collectively laminated using a large substrate, and after lamination, each circuit module is separated to be more efficient. Production is possible.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining a manufacturing process of a multilayer circuit module according to a first embodiment.

FIG. 2 is a view for explaining a manufacturing process of the laminated circuit module.

FIG. 3 is a view for explaining a manufacturing process of the laminated circuit module.

FIG. 4 is a view for explaining a manufacturing process of the laminated circuit module.

FIG. 5 is a diagram for explaining a manufacturing process of the multilayer circuit module according to the second embodiment.

FIG. 6 is a view for explaining a manufacturing process of the laminated circuit module.

FIG. 7 is a view for explaining a manufacturing process of the laminated circuit module.

FIG. 8 is a diagram for explaining a manufacturing process of the multilayer circuit module according to the third embodiment.

FIG. 9 is a diagram for explaining a manufacturing process of the multilayer circuit module according to the fourth embodiment.

FIG. 10 is a view for explaining a manufacturing process of the laminated circuit module.

FIG. 11 is a view for explaining a manufacturing process of the laminated circuit module.

FIG. 12 is a diagram for explaining a manufacturing process of the multilayer circuit module according to the fifth embodiment.

FIG. 13 is a view showing a conventional laminated circuit module.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Wiring board, 2, 3 ... Wiring, 8 ... Insulating layer, 9 ... Insulating layer, 10 ... 11 Wiring, 12 ... Bare chip, 16 ... Bare chip, 20a, 20b ... Stud bump, 21 ... Feedthrough electrode, 22a, 22b ... stud bump, 2
3 ... feed-through electrode, 31 ... prepolymer, 32 ...
Glass substrate, 33 release layer, 40 feed-through electrode, 41 feed-through electrode, 60 pressing substrate, 6
0a: unevenness, 72: convex portion.

Claims (15)

[Claims] A first wiring, a first insulating layer formed on the first wiring, and a state in which the first wiring is electrically connected to the first wiring in the first insulating layer. A built-in first surface mount component, a second wiring formed on an upper surface of the first insulating layer, a second insulating layer laminated on the first insulating layer, A second surface-mounted component embedded in the second insulating layer while being electrically connected to the second wiring; and electrically connected to the first and second wirings in the first insulating layer. And a feed-through electrode embedded in the stacked state. 2. The multilayer circuit module according to claim 1, wherein said feed-through electrode is formed by stud bumps. 3. The multilayer circuit module according to claim 2, wherein a plurality of said stud bumps are stacked. 4. The multilayer circuit module according to claim 1, wherein the feed-through electrode has an upper portion thinner than a bottom portion. 5. A first surface-mounted component is mounted on a base material having a first wiring formed on an upper surface thereof while being electrically connected to the first wiring, and the first wiring is mounted on the first wiring. Disposing a feed-through electrode; laminating a first insulating layer on the base material in a state where an upper surface of the feed-through electrode is exposed; Forming a second wiring electrically connected to the through electrode; and forming a second surface-mounted component on the first insulating layer while being electrically connected to the second wiring. A method for manufacturing a laminated circuit module, comprising: a mounting step; and a step of laminating a second insulating layer on the first insulating layer. 6. The laminating step of the insulating layer includes: a step of arranging a resin having fluidity; and a step of using a mold to press the fluid resin until the upper part of the feedthrough electrode contacts the mold. The method according to claim 5, further comprising: a step of curing the fluid resin; and a step of removing the mold material. 7. The method for manufacturing a multilayer circuit module according to claim 6, wherein a release layer is formed on a surface of said mold material. 8. The method for manufacturing a multilayer circuit module according to claim 6, wherein a resin that contracts in volume upon curing is used as the fluid resin. 9. The method for manufacturing a multilayer circuit module according to claim 6, wherein after the mold material is peeled off, the surface of the resin is ashed or the surface of the resin is mechanically polished. 10. The method according to claim 6, wherein fine irregularities are formed on the surface of the mold. 11. The arrangement of the feed-through electrode is J
6. The method according to claim 5, wherein the method is performed by a PS or a printing method. 12. The method for manufacturing a multilayer circuit module according to claim 5, wherein a convex portion for forming a component arrangement space is formed on a surface of said mold member. 13. A method according to claim 5, wherein a projection for adjusting the thickness of the insulating layer is formed on the surface of the mold.
3. The method for manufacturing a laminated circuit module according to item 1. 14. The method according to claim 6, wherein an epoxy resin is used as the fluid resin. 15. The method according to claim 5, wherein a bare chip is used as the surface mount component.