JP2000181401A - Drive circuit of capacitive load and display device using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce loss with respect to the charging and discharging of capacitive load by providing a flow passage flowing to a high-voltage power source terminal via a parallel diode of a pull-up switch of a high-voltage output stage from a panel capacitor with a reverse-current limiting means. SOLUTION: The flow passage flowing to the high-voltage power source terminal 71 via the parallel diode 97 of the pull-up switch 85 of the high-voltage output stage 75 from the panel capacitor is provided with the reverse-current limiting means (reverse-current limiting switch 96). Namely, a switching means 96 which is the reverse-current limiting switch, the parallel diode 97 of the reverse-current limiting switch 96 and a terminal 95 for connecting the reverse- current limiting switch 96 are added to the high-voltage output stage 75. In such a case, the reverse-current limiting switch 96 is connected between the pull-up switch 85 and a pull-down switch 88 in series to these switching means 85 and 86. More specifically, the one end of the pull-up switch 85 is connected to the terminal 80 of the high-voltage output means 75 and the other end of the pull-up switch 85 is connected to the one end of the reverse-current limiting switch 96.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a driving circuit and an integrated circuit (hereinafter referred to as a driver IC) for driving a capacitive load such as a plasma display panel and a display device using the same.

[0002]

2. Description of the Related Art The prior art will be described below using an example of the structure of a plasma display panel (hereinafter referred to as PDP).

FIG. 2 shows a schematic view of a PDP and each electrode. 3
0 is a PDP, 31 is a scan drive circuit, Y1 ... Ym is a scan electrode, 32 is a sustain drive circuit, X1 ... Xm is a sustain electrode, 33 is an address drive circuit, R1, G
1, B1... Rn, Gn, Bn are address electrodes, and 34 is a unit cell. One pixel is composed of three unit cells of R, G, and B. For example, in a PDP having 1024 × 768 pixels (cells), the number of scan electrodes and sustain electrodes is 768, and the number of address electrodes is 3072. Each of a plurality of electrodes (scan electrodes Y, sustain electrodes X, address electrodes R, G, and B) connected to the unit cells 34 arranged in a matrix is controlled to emit light by a drive signal to display an image. is there.

The address electrodes (R1, G1, B1... Rn, Gn, Bn) connected to the address drive circuit 33 and the scan electrodes (Y1... Y) connected to the scan drive circuit 31.
m), the unit cell 34 to be lit is selected, and then the scan drive circuit 31 and the sustain drive circuit 32 are driven to drive the electrodes (Y) connected to the drive circuits 31, 32.
1... Ym) (X... Xm).

FIG. 3 is a schematic sectional view of the unit cell 34.

[0006] 50 is a front glass substrate, 51 is a dielectric layer,
52 is a protective film, 53, 54, and 55 are phosphors, 56 is a scan electrode, 57 is a sustain electrode, 58 is an address electrode, and 59 and 60 are address electrodes adjacent to 58.

[0007] The main load when driving the address electrodes 58 in the address driving circuit, the address electrodes - and ^{- (+ Ca + = Ca)} , address electrodes - capacity Ca-a between the address electrodes scan electrodes, between sustain electrode The capacity is Ca-xy.

The power loss in actual discharge is very small, and most of the power loss at the address electrodes
-A, Ca-xy). It is well known that this power loss is large, and reduction is required from both the power consumption of the PDP and the allowable loss of the driver IC.

Therefore, as described in Japanese Patent Application Laid-Open No. 8-160901, there has been proposed a method of recovering charges by connecting a coil for recovering charges and a coil.

FIG. 4 shows an example of the configuration of a driving circuit using a conventionally used driver IC, and FIG. 5 shows an example of operation waveforms.

Reference numeral 65 denotes a high-voltage power supply, Cref denotes a recovery capacitor, L denotes a recovery coil, 66 denotes a low-voltage power supply, 67 denotes an n-output driver IC, 68 denotes a low-voltage input terminal, 69 denotes a low-voltage power supply terminal, and 70 denotes a low-voltage GND terminal. , 71 are high voltage power supply terminals,
72 is a high voltage GND terminal, 73 is a low voltage section, 74 is a high voltage logic section, 75 is a high voltage output stage, Q1 ... Qn are high voltage output terminals, C
p1... Cpn are panel capacitances. Cref is Cp1
.. + Cp2 +... + Cpn.
The operation waveform indicated by VIC in FIG. 5 is the potential of the high-voltage power supply terminal 71, and the operation waveform indicated by Vout is the high-voltage output terminals Q1.
It shows the potential of n. Here, the low-voltage power supply is L
It refers to a power supply having a voltage value usually used for the SI logic system, and is, for example, 3V to 5V. The high-voltage power supply refers to a power supply for driving a load having a larger voltage value than the low-voltage power supply, and is, for example, 40 V to 70 V in a PDP. A description will be given below using the definitions of the high pressure and the low pressure.

The configuration of the driver IC is simply shown for the low-voltage system.

First, the operation of the driver IC will be briefly described. The signal input from the low voltage input terminal 68 is subjected to serial-parallel conversion or the like by the low voltage unit 73, and is input to the high voltage logic unit 74. A signal for driving the high voltage output stage 75 is formed by performing a level shift or the like by the high voltage logic unit 74. From the high voltage output stage 75, the high voltage output terminals Q1.
The charge and discharge of panel capacitances Cp1... Cpn are performed via n.

Next, the collecting operation will be briefly described with reference to FIGS.

In the period t1 in FIG. 5, SW1 is off and SW2
Is turned on, and the pull-up switch of the high voltage output stage is turned on. At this time, Cr having a potential of about half of the high voltage power supply 65
From ef, charges flow into the high-voltage power supply terminal 71 via SW2 and L. High-voltage power supply terminal 7 whose initial state is GND level
The potential of 1 ideally rises to the high voltage power supply level due to LC resonance. The pull-up switch of the high-voltage output stage 75 which is turned on from the high-voltage power supply terminal 71, the high-voltage output terminal Q1 ...
Charges flow into the panel capacitors Cp1... Cpn via Qn.

During the period of t2, SW1 is turned on and SW2 is turned off. During the period of t1, the panel capacitances Cp1.
Charge that does not reach the high-voltage power supply level.

During the period of t3, SW1 is turned off and SW2 is turned on. At this time, the electric charges of the panel capacitors Cp1... Cpn are transferred to the high voltage output terminals Q1.
1, L, and flows into Cref via SW2. as a result,
Ideally, by LC resonance, the high voltage output terminals Q1.
The potential of the high voltage power supply terminal 71 drops to the GND level.

During the period of t4, SW2 is turned off, the pull-up switch of the high-voltage output stage 75 is turned off, and the pull-down switch of the high-voltage output stage 75 is turned on. During the period of t3, the panel capacitances Cp1,. The portion where the potential does not reach the GND level is discharged.

As described above, the panel capacitances Cp1.
Ideally, all the charge and discharge charges of Cpn are covered by the exchange with Cref, and the outflow of charges from the high-voltage power supply 65 is eliminated, and the loss is reduced. There is also a reduction in loss by using LC resonance.

[0020]

However, in the above-mentioned conventional example, the signal of a continuous high signal is notched every pulse. In other words, extra charge / discharge for the continuous high level increases the loss.

Further, by vibrating the power supply voltage of the high-voltage logic section 74 connected to the high-voltage power supply terminal 71 together with the high-voltage output stage 75, the parallel capacitance of the elements constituting the high-voltage logic section 74 is also used as a load. This parallel capacitance is in the order of several pF and cannot be ignored in terms of resonance conditions, resonance period, and the like, and is disadvantageous for loss reduction.

Further, when the power supply voltage of the high-voltage logic unit 74 is varied, the determination of the high-voltage logic is delayed due to the Vth of the constituent elements, and the operation of the high-voltage output stage 75 is delayed, which is disadvantageous for loss reduction.

Further, there is no means for preventing the driver IC 67 from being destroyed with respect to the electric charge flowing backward from the panel capacitances Cp1... Cpn. That is, the panel capacitance Cp1
... There is a period during which there is no path through which the charge flowing backward from Cpn escapes via the parallel diode of the pull-up switch of the high-voltage output stage 75, and the driver ICs become abnormal because the potentials of the high-voltage output terminals Q1. There is a possibility of breakdown, and both loss reduction and IC breakdown resistance have not been achieved.

Although ideally LC resonance, it is actually LCR resonance via the on-resistance of the pull-up switch of the high-voltage output stage 75, and this on-resistance is high. No consideration is given to reducing the loss reduction effect.

It is an object of the present invention to provide a drive circuit and a driver IC capable of reducing a loss in charging and discharging a capacitive load, and a display device using the same.

[0026]

As a first means for achieving the object, a high voltage power supply terminal 7 is connected to a panel capacitor via a parallel diode of a pull-up switch of a high voltage output stage.
1 is provided with a reverse current limiting means.

As a second means for achieving the object,
The high-voltage logic unit power terminal and the high-voltage output stage power terminal are provided independently of each other.

As a third means for achieving the object,
The high-voltage logic unit power supply terminal and the high-voltage output stage power supply terminal are provided independently of each other, and a reverse current conducting means is provided between the high-voltage output terminal and the high-voltage logic unit power supply terminal.

As a fourth means for achieving the object,
Means for reducing on-resistance at the start of resonance is provided.

[0030]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment will be described with reference to FIGS. 1, 6, 7 and 8. FIG.

First, for comparison with the embodiment, the internal configuration of the conventional high-voltage output stage 75 in FIG. 4 will be described with reference to FIG.

In FIG. 6A, reference numeral 80 denotes a terminal connected to the high voltage power supply terminal 71, 81 denotes a terminal connected to the high voltage GND terminal 72, 82 and 83 denote terminals connected to the high voltage logic unit 74, and 84 denotes terminals connected to the high voltage output terminal. , 85 is terminal 8
0 is a pull-up switch located between the terminal 84 and 86; 86 is a parallel diode of a pull-up switch 85 having an anode connected to the terminal 84 side; 87 is a pull-down switch located between the terminal 81 and the terminal 84; This is a parallel diode of the pull-down switch 87 whose anode is connected to the side. The pull-up switch 85 is turned on / off using the signal at the terminal 82 as a control signal. The same applies to the relationship between the terminal 83 and the pull-down switch 87. The parallel diodes 86 and 88 are protection diodes for the switches 85 and 87.

Here, the current path from the terminal 80 to the terminal 84 is turned on / off by the pull-up switch 85 to turn on / off.
Although non-conduction can be selected, the current path from the terminal 84 to the terminal 80 is always on by the parallel diode 86.

FIG. 6B shows a specific example. The pull-up switch 85 shown in FIG.
9. The pull-down switch 87 is replaced with a high-voltage nMOSFET 90. Usually, these MOSFETs have their own parallel diodes, so the parallel diodes 86, 87
Although they are included in the circuit symbols of the MOSFETs 89 and 90, they are illustrated for convenience of explanation.

Next, the configuration of the first embodiment will be described with reference to FIG.

FIG. 1 is a first circuit diagram showing the internal circuit configuration of the high-voltage output stage 75, which is a feature of the present embodiment, and the configuration of its peripheral circuits.
This is an embodiment of the present invention. Driver IC6 for simplicity of explanation
The high voltage output of No. 7 is set to one output of Q1. Driver IC
The high-voltage power supply terminal 71 of 67 is connected to the high potential side of the high-voltage power supply 65 via the switch means SW1 (for example, a semiconductor switching element). The high voltage GND terminal 72 of the driver IC 67 is connected to the GND potential side of the high voltage power supply 65.
The high-voltage power supply terminal 71 is connected to one end of a power recovery capacitor Cref via a power recovery coil L and a switch SW2 connected in series. Further, the high voltage GND terminal 72 is connected to the other end of the collection capacitor Cref. In the driver IC 67, a high-voltage output stage 75 for driving the panel capacitance Cp1 by switch means 85, 96, 87 is connected between the high-voltage power supply terminal 71 and the high-voltage GND terminal power supply 72. That is, the terminals 80 and 81 of the high-voltage output stage are connected to the high-voltage power supply terminal 71 and the high-voltage GND terminal 72, respectively. The output terminal 84 of the high voltage output stage 75 is connected to the high voltage output terminal Q1 of the driver IC. The panel capacitance Cp1 is connected to the high voltage output terminal Q1, and the panel capacitance Cp1 is charged and discharged by the voltage applied to the high voltage output terminal Q1. The high voltage output stage 75 is controlled by a high voltage logic 74 connected between the high voltage power supply terminal 71 and the high voltage GND terminal power supply 72. That is, in the high-voltage logic unit 74, the switching means 8 of the high-voltage output stage 75
A plurality of outputs for outputting signals for driving 5, 96, 87 are provided to input terminals 82, 95, 8 of high voltage output stage 75, respectively.
3 is connected. In the driver IC 67, the input of the high-voltage logic unit 74 is connected to the output of the low-voltage unit 73 that performs signal processing. Here, for simplicity, the low voltage input terminal is 1
Although only one is shown, there are actually a plurality of terminals. For example, there are power recovery control terminals, which are one of the features of the present invention, in addition to data input, data output, clock, and latch control terminals. The input of the low voltage unit 73 is connected to the low voltage input terminal 68 of the driver IC. A signal externally input to the low-voltage input terminal 68 is input to the low-voltage unit 73 and is input to the low-voltage unit 7.
The signal is subjected to signal processing such as serial-parallel conversion by 3 and output from the low voltage unit 73. The output signal is input to the high voltage logic unit 74, subjected to signal processing such as level shift in the high voltage logic unit 74, and output as a drive signal for the high voltage output stage 75. The power supply of the low voltage unit 73 is a high voltage power supply 6
The low-voltage power supply 66 has a voltage lower than 5. Low voltage power supply 66
The high potential side and the GND side of the
Are connected to a low-voltage power supply terminal 69 and a low-voltage GND terminal 70. The low-voltage unit 73 is connected between the low-voltage power supply terminal 69 and the low-voltage GND terminal 70, so that a voltage is applied from the low-voltage power supply 66. Cref is a large capacity that maintains a substantially constant potential even when the charge and discharge charges of Cp1 move.

The configuration of the high voltage output stage 75 will be described.
This is because the switch means 96 serving as a backflow limiting switch and the backflow limiting switch means 96 in FIG.
And a terminal 95 for controlling the reverse current limiting switch 96 is newly added. That is, the pull-up switch means 85 and the pull-down switch means 8
Between 8, the backflow limiting switch means 96 is connected in series with these switch means. Specifically, one end of the pull-up switch means 85 is connected to the terminal 80 of the high-voltage output stage 75. The other end of the pull-up switch means 85 is connected to one end of the backflow restriction switch means 96. The other end of the backflow restriction switch means 96 is connected to one end of the pull-down switch means 87. The other end of the pull-down switch means 87 is connected to a terminal 81 of the high voltage output stage 75. A diode is connected to each switch means in parallel.
Diode 8 connected to pull-up switch means 85
The direction of the diode 88 connected to the pull-down switch 6 and the pull-down switch 87 is a direction in which a current flows from the other end of each switch to one end. On the other hand, the direction of the diode 97 connected to the reverse current limiting switch means 96 is opposite to that of the other diodes, that is, the direction in which current flows from one end of the switch means to the other end. As described below, the conduction / non-conduction of the current path from the terminal 84 to the terminal 80 can be controlled by the reverse current limiting switch 96.

FIG. 7 shows an example of the operation waveform of this embodiment. In the figure, VIC indicates the potential of the high-voltage power supply terminal 71, and Vout indicates the potential of the high-voltage output terminal Q1.

The operation will be described with reference to FIGS.

In the period of t1, SW1 is off, SW2 is on, SW85 is on, SW96 is off, and SW87 is off. Vout, whose initial state was at the GND level, causes the charge stored in Cref to be SW2, L, the high-voltage power supply terminal 71, the terminals 80, SW85, and SW96 due to LC resonance between L and Cp1 (+ parasitic capacitance of a driver IC or the like). Through the parallel diode 97, the terminal 84, and the high voltage output terminal Q1,
By flowing into Cp1, it ideally rises to the high voltage power supply level. VIC also ideally rises to the high voltage power supply level.

In the period of t2, SW1 is on, SW2 is off, SW85 is on, SW96 is off, and SW87 is off. During the period of t1, Vout and VIC are charged from the high-voltage power supply 65 via SW1 for the portion that does not reach the high-voltage power supply level.

In the period of t3, SW1 is off, SW2 is on, SW85 is on, SW96 is off, and SW87 is off. In the conventional high-voltage output stage 75 configuration (FIG. 6A), Vout here causes the charge stored in Cp1 to drop to the high-voltage output terminal Q due to LC resonance as indicated by the broken line 100.
1, parallel diode 86, terminal 80, high voltage power supply terminal 7
Ideally, the voltage drops to the GND level by flowing into Cref via 1, L, and SW2. VIC also ideally falls to the GND level. However, in this embodiment, since the reverse current limiting switch 96 is turned off and the direction of the parallel diode is reversed, the terminal 84 is connected to the terminal 80.
The current path to the VIC can be made non-conductive to suppress the drop of the VIC. VIC falls to near the GND level.

In the period of t4, SW1 is off, SW2 is off, SW85 is on, SW96 is off, and SW87 is off. Vout maintains the high voltage power supply level. In the conventional high-voltage output stage 75 configuration (FIG. 6A), Vout
Indicates that Vout is G during the period of t3 as indicated by the broken line 100.
The portion that does not reach the ND level is discharged using SW87.

In the period of t5, SW1 is off, SW2 is on, SW85 is on, SW96 is off, and SW87 is off. Vout maintains the high voltage power supply level. In the conventional high-voltage output stage 75 configuration (FIG. 6A), Vout
Rises to near the high voltage power supply level as shown by the dashed line 100.

In the period of t6, SW1 is on, SW2 is off, SW85 is on, SW96 is off, and SW87 is off. Vout maintains the high voltage power supply level. In the conventional high-voltage output stage 75 configuration (FIG. 6A), Vout
Charges the portion that does not reach the high-voltage power supply level during the period of t5.

In the period of t7, SW1 is off, SW2 is on, SW85 is off, SW96 is on, and SW87 is off. Due to the LC resonance, Vout causes the charge stored in Cp1 to be changed so that the parallel diodes 86 of the high-voltage output terminals Q1, SW96 and SW85, the terminal 80, the high-voltage power supply terminals 71, L,
Ideally, G flows into Cref via SW2.
It falls to the ND level. VIC is ideally G
It falls to the ND level.

During the period of t8, SW1 is off, SW2 is off, SW85 is off, SW96 is on, and SW87 is on. During the period of t7, the portion where Vout does not reach the GND level is discharged using SW87.

FIG. 8 shows an example in which the switches 85, 96 and 87 of FIG. 1 are replaced by high-voltage MOSFETs. Reference numeral 89 denotes a high gate withstand voltage and high voltage pMOSFET. The source is connected to the terminal 80, the gate is connected to the terminal 82, and the drain is connected to the source of the high gate withstand voltage and high voltage nMOSFET 98. High gate withstand voltage high voltage nMOSFET98
Has a drain connected to the terminal 84 and the drain of the high-voltage nMOSFET 90, and a gate connected to the terminal 95. High pressure
The nMOSFET 90 has a source connected to the terminal 81 and a gate connected to the terminal 83. High gate breakdown voltage MOSFET can apply the same high voltage between the gate and source as between the source and drain by thickening the gate oxide film and increasing the gate breakdown voltage
MOSFET. By using a high gate breakdown voltage MOSFET for the SW 96, the gate signal of the terminal 95 can be easily generated by the high voltage logic unit 74, and the configuration is simplified.

As described above, the parallel diodes 86, 97, and 88 are parasitic diodes unique to the inside of the MOSFETs 89, 98, and 90, respectively. Although the case where the switch 86 is a high gate withstand voltage and high voltage nMOSFET has been described with reference to FIG. 8, the switch 86 may be implemented with a high gate withstand voltage and high voltage pMOSFET.

According to the first embodiment described above, when a continuous high pulse is output, the driver IC that can suppress the increase in power loss because the high-voltage output does not have a step and can reduce the power loss is provided. Can be provided.

The types of the constituent MOSFETs are not limited to the present embodiment, and similar effects can be obtained with other switch elements if attention is paid to the direction of the parallel diode.

A second embodiment will be described with reference to FIGS.

FIG. 9 is a view showing a second embodiment of the present invention, which is characterized in that a recovery power supply terminal 105 is provided. It is to be noted that the low-voltage system shown in FIG. 1 is omitted, and parasitic capacitances 106 and 107 necessary for explanation are shown. In order to simplify the explanation, the high voltage output of the driver IC 67 is set to one output of Q1. The description that overlaps with FIG. 1 is omitted.

The parasitic capacitance 106 of the element constituting the high voltage output stage 75 and the parasitic capacitance 10 of the element constituting the high voltage logic section 74
7 are present. Each of these has about several pF, and may be several hundred pF or more as a whole. High voltage power supply terminal 7
In the power recovery method in which the voltage of 1 is oscillated, these parasitic capacitances 106 and 107 also become loads, and the load capacity increases as compared with the case without power recovery. Therefore, in this embodiment, the high-voltage output stage 7
5 and a power supply terminal of the high voltage logic unit 74, respectively.
5 is connected to the high-voltage power supply terminal 71 directly connected to the high-voltage logic unit 74.
And the recovery power supply terminal 105 connected to L is connected to the output stage 75, and the load capacity at the time of power recovery is reduced by the parasitic capacitance 107 of the element constituting the high-voltage logic unit 74 as compared with the conventional one.

FIG. 12 shows a configuration example of the high voltage logic unit 74.
For the sake of simplicity, only the part that generates a control signal to be input to the terminal 82 for the pull-up switch 85 of the high-voltage output stage 75 is shown.

Reference numeral 120 denotes a terminal connected to the high-voltage power supply terminal 71; 121, a terminal connected to the high-voltage GND terminal 72;
2 is a low-voltage input terminal to which a signal from the low-voltage section is input;
3 is a high voltage output terminal for outputting control signals to the terminals 82 and 95 for the pull-up switch 85 and the reverse current limit switch 96 of the high voltage output stage 75, 124 and 125 are high gate withstand voltage high voltage pMOSFETs, 126 and 127 are high voltage nMOSFETs,
128 is an inverter.

When outputting a low voltage to the high voltage output terminal 123, a low voltage is input to the low voltage input terminal 122. At this time, the high voltage nMOSFET 126 is turned off, and the high voltage nMOS in which the high voltage is applied to the gate by the inverter 128 is applied.
The FET 127 turns on. As a result, high gate withstand voltage and high voltage pMOSFE
When T 124 is turned on and the high gate withstand voltage high voltage pMOSFET 125 is turned off, a low voltage is output to the high voltage output terminal 123.

When outputting a high voltage to the high voltage output terminal 123, a high voltage is input to the low voltage input terminal 122. At this time, the high-voltage nMOSFET 126 is turned on, and the low voltage is applied to the gate by the inverter 128.
FET 127 turns off. As a result, high gate withstand voltage and high voltage pMOSFE
By turning off T124 and turning on the high gate withstand voltage high voltage pMOSFET 125, a high voltage is output to the high voltage output terminal 123.

When the power supply terminals of the high-voltage output stage 75 and the high-voltage logic section 74 are shared, when the power supply terminal voltage decreases to near the GND level and rises from the GND level, the voltage of the terminal 120 also temporarily increases to the vicinity of the GND level. Falling and rising. This voltage is a high gate withstand voltage high voltage pMOSFET 124,12
5 (for example, about 5 to 15 [V]).
The potential of the high voltage output terminal 123 is indeterminate. When the power terminals of the high voltage output stage 75 and the high voltage logic unit 74 are provided independently,
The voltage of the terminal 120 is constant at the high voltage power supply level, and the above problem does not occur.

According to the above-described second embodiment, the driver I that improves the loss reduction effect by reducing the load during power recovery.
C can be provided.

Further, since the potential of the high voltage logic unit 74 is stable, the high voltage output stage 75 which is the output of the high voltage logic unit 74 is used.
Is stable, the operation of the output-stage MOSFET can be hastened, and resonance can occur efficiently. That is, it is possible to provide a driver IC that enhances the loss reduction effect.

The internal circuit configuration of the high-voltage output stage 75 is not limited to that shown in FIG. 9, and the same effect can be obtained with the configuration shown in FIG. 8, for example.

A third embodiment will be described with reference to FIGS.

FIG. 10 is a view showing a third embodiment of the present invention, which is characterized in that a recovery power supply terminal 105 is provided. The low-voltage system and high-voltage logic unit 74 shown in FIG. 1 are omitted, and the reverse current protection diodes 111 and 1 necessary for describing the present invention.
12 is illustrated. The anode of the diode 111 is Q1,
The cathode is connected to terminal 71. The diode 112 has an anode connected to the terminal 110 and a cathode connected to Q1.
In order to simplify the explanation, the high-voltage output of driver IC 67 is Q
One output of one. The description that overlaps with FIG. 1 is omitted.

In a driver IC driven by using a capacitance as a load, the resistance to a current (hereinafter referred to as abnormal discharge) flowing backward from the load capacitance at an unexpected time is important.

In the conventional power recovery system using an IC, in the period when both SW1 and SW2 shown at t4 in FIG. 5 are off, or when SW1 shown at t1 and t3 in FIG.
During the ON period, the path for releasing the charge flowing into the driver IC due to the abnormal discharge from Cp1 is cut off or becomes high impedance. At this time, if an abnormal discharge occurs, the potential of the high voltage output terminal Q1 abnormally rises, and the driver IC 75 is destroyed. Therefore, in the present invention, the reverse current protection diodes 111 and 112 are provided, and the high voltage output stage 75 is provided.
And a power supply terminal for abnormal discharge. The high-voltage power supply terminal 71 directly connected to the high-voltage power supply 65 is connected to the cathode side of the reverse current protection diode 111, and the recovery power supply terminal 105 connected to L is connected to the output stage 75. By connecting the anode side of the backflow current protection diode 111 to the high voltage output terminal Q1, it is possible to always provide a charge extraction path for Cp1, Q1, the backflow current protection diode 111, the high voltage power supply terminal 71, and the high voltage power supply 65.

According to the third embodiment described above, it is possible to provide a driver IC having a withstand capability against abnormal discharge while maintaining the effect of power recovery.

The internal circuit configuration of the high voltage output stage 75 is shown in FIG.
The same effect can be obtained with the configuration shown in FIG.

A fourth embodiment will be described with reference to FIG.

FIG. 11 shows the high-voltage logic section 74 and the parasitic capacitances 106 and 107 omitted in FIG. For simplicity of explanation, the high-voltage output of the driver IC 67 is set to one output of Q1 as in FIG. The description of points that are the same as in FIGS. 1, 9, and 10 will be omitted. In the present invention, the high voltage logic unit 7
4 and the high-voltage power supply terminal 71 for abnormal discharge are shared, and a recovery power supply terminal 105 is additionally provided.

According to the above-described fourth embodiment, by sharing the high-voltage power supply of the high-voltage logic unit 74 and the backflow protection diode 111, the effects of the second and third embodiments can be improved.
67 can be realized while simplifying the wiring.

The internal circuit configuration of the high voltage output stage 75 is shown in FIG.
The same effect can be obtained with the configuration shown in FIG.

FIGS. 9 and 13 to 1 for the fifth embodiment.
7 will be described.

The operation of charging Cp1 with electric charge will be described with reference to FIG.

Cre having half the potential of the high voltage power supply 65
The charge stored in f is SW2, L, and the power supply terminal for recovery 10
5, flows into Cp1 via terminal 80, pull-up switch 85, terminal 80, and high voltage output terminal Q1. At this time, the potential of the high-voltage output terminal Q1 is higher than the potential of Cref due to L, Cp1, and the LCR resonance caused by the ON resistance of the pull-up switch 85, and if the resistance is zero, it is ideal for a certain period. Rises to a voltage twice the potential of Cref, that is, the potential of the high-voltage power supply.

The resonance condition of LCR resonance is R <2√ (L / C). For this reason, the on-resistance of the pull-up switch 85 needs to be low. Also, the power loss at LC resonance is basically zero, but if there is a resistance,
There is resistance loss. When the current value is I, the resistance loss is IR ²
Therefore, the on-resistance of the pull-up switch 85 also needs to be low.

In this embodiment, the on-resistance of the pull-up switch 85 is reduced by the configuration shown in FIG.

FIG. 13 shows the parasitic capacitances 106 and 107 of FIG.
Is omitted, and the pull-up switch 85 is set to a high gate withstand voltage and high voltage.
nMOSFET 130 and pull-down switch 87 are connected to high-voltage nMOSFET
90. High gate withstand voltage high voltage nMOSFE
The source of T130 is connected to terminal 84, the drain is connected to terminal 80, and the gate is connected to terminal 82. The source of the high-voltage nMOSFET 90 is a terminal 81, a drain is a terminal 84, and a gate is a terminal 83.
Connected to. High gate breakdown voltage MOSFET can apply the same high voltage between the gate and source as between the source and drain
MOSFET. The reduction of the on-resistance by using the high gate withstand voltage and high voltage nMOSFET 130 as the pull-up switch 85 will be described below.

FIG. 14A shows the high voltage logic section 74 of FIG.
And the configuration of the high gate voltage high voltage nMOSFET 130 and Cp1. FIG. 14B shows the gate-source voltage characteristics of the high gate voltage high voltage nMOSFET 130 with respect to the source potential of the high gate voltage high voltage nMOSFET 130 in the high voltage output level mode. Here is an example. At this time, for simplicity of explanation, C
The potential of p1 is fixed at the GND level.

The potential of the terminal 105 changes from the GND level to the high-voltage power supply level (here, supposed to be 50 [V]), but the potential of the terminal 71 is fixed at the high-voltage power supply level. Therefore, the gate applied voltage (= high power supply level) for turning on the high gate withstand voltage high voltage nMOSFET 130 is supplied to the gate G in a stable manner. At this time, the gate-source voltage with respect to the potential of the terminal 105 shows the characteristics of the straight line 116.

Next, the case where the power supply terminals of the high voltage output stage 75 and the high voltage logic section 74 are shared is shown in FIG.
FIGS. 15 (a) and 15 (b) show the same ones as (a) and (b).

The potential of the terminal 71 changes from the GND level to the high-voltage power supply level (here, supposed to be 50 [V]). Accordingly, the gate applied voltage for turning on the high gate withstand voltage high voltage nMOSFET 130 also changes from the GND level to the high voltage power supply level, and is supplied to the gate G. Terminal 7 at that time
The gate-source voltage for a potential of 1 shows the characteristics of the straight line 115.

Next, in the case where a high gate withstand voltage and high voltage pMOSFET 89 is provided in place of the high gate withstand voltage and high voltage nMOSFET 130, a structure similar to FIGS.
(A) and (b) show.

The potential of the terminal 105 changes from the GND level to the high-voltage power supply level (here, supposed to be 50 [V]), and the potential of the terminal 71 is fixed at the high-voltage power supply level. The gate applied voltage (= GND level) for turning on the high gate withstand voltage high voltage pMOSFET 89 is stably supplied to the gate G. However, since the source of the high gate withstand voltage and high voltage pMOSFET 89 is on the terminal 105 side, the voltage between the gate and the source with respect to the potential of the terminal 105 shows the characteristic of the straight line 131.

FIG. 17 shows the on-resistance characteristics of the pull-up switch with respect to the voltage of the voltage terminal to which the pull-up switch 85 of the high-voltage output unit 75 is connected, as shown in FIGS. 14 (b), 15 (b) and 16 (b). An example is shown below.

A curve 117 indicates a high gate withstand voltage and high voltage nMOSFET 1
FIG. 14 shows the characteristics of FIG. 14 in which 30 is used as a pull-up switch and the power supply terminals of the high voltage output stage 75 and the high voltage logic unit 74 are provided independently. Curve 118 shows a high gate withstand voltage high voltage nMOSFET 130
15 in which the power supply terminal of the high-voltage output stage 75 and the high-voltage logic unit 74 are made common, and FIG. 1 in which the high gate withstand voltage high-voltage pMOSFET 89 is used as the pull-up switch.
6 is the characteristic.

FIG. 17 shows that, in particular, at the initial stage of recovery (high-voltage output section 7).
5 when the voltage of the voltage terminal to which the pull-up switch 5 is connected is low).
It can be seen that when the power supply terminal of the high voltage output stage 75 and the power terminal of the high voltage logic section 74 are provided independently using 30 as a pull-up switch, the value becomes extremely small.

According to the fifth embodiment described above, it is possible to provide a driver IC in which the resistance at the initial stage of recovery is reduced, the effect of power recovery is improved, and the effect of reducing power loss is enhanced.

The configuration of the high-voltage output stage 75 is not limited to this. For example, the high-gate withstand voltage high-voltage pMOSFET 89 shown in FIG.
The same effect can be obtained by replacing with a high gate withstand voltage and high voltage nMOSFET.

FIGS. 1, 18 and 1 show a sixth embodiment.
This will be described with reference to FIG.

FIG. 18 is a simple block diagram focusing on the PDP video system.

140 is a PDP device, 141 is a video signal input terminal, 142 connected to the terminal 141 is a video signal processing block, and 14 is connected to the video signal processing block 142.
3 is a control block. 31 is a scan drive circuit, 1
46 is a power recovery circuit of the scan drive circuit 31, 32 is a sustain drive circuit, 147 is a power recovery circuit of the sustain drive circuit 32, 33 is an address drive circuit according to the present invention, and 148 is power of the address drive circuit 33 according to the present invention. It is a recovery circuit. These circuits 31, 146, 32, 14
7, 33, and 148 are connected to the control block 143. Reference numeral 145 denotes a high-voltage power supply block which is a power recovery circuit 14.
6, 147, 148 and 149, 151, 15 respectively
0 high voltage power supply lines. Reference numeral 30 denotes a display panel (PDP). The low-voltage power supply and the GND line are omitted. In addition, although one control signal line is output from each control block for each block for simplification of the drawing, this indicates a plurality of control lines. Also,
The power recovery circuit 146 of the scan drive circuit and the power recovery circuit 147 of the stin drive circuit may not be provided. In that case, the high-voltage power supply line 149 is connected to the scan drive circuit 31.
The high-voltage power supply line 151 is directly input to the sustain drive circuit 32.

The video signal input from the input terminal 141 is input to the control block 143 after being subjected to A / D conversion and the like in the video signal processing block 142.
In the control block 143, the scan drive circuit 31, the power recovery circuit 146, the sustain drive circuit 32, the power recovery circuit 147, the address drive circuit 33, and the power recovery circuit 148
Is generated and input to each block. Each block applies a voltage to the display panel 30 according to the input control signal and the signals of the power recovery circuits 146, 147, and 148 (the address system is indicated by 160), and displays an image on the display panel 30.

FIG. 19 is a block diagram of the power recovery circuit 148 of the address drive circuit 33. FIG. 19 is a diagram obtained by adding a SW control signal to a part of FIG. 1, and a description overlapping with that described in FIG. 1 will be omitted. 155 is a power terminal connected to the high voltage power line 150, 156 is connected to the control block 143, a control signal input terminal for controlling SW2, 157 is connected to the control block 143, a control signal input terminal for controlling SW1, 158 is a GND terminal, Fifteen
9 is an output terminal connected to the address drive circuit 33.

FIG. 21 shows a simple configuration of the address drive circuit 33.

Reference numerals 67-1 to 67-n denote n driver ICs.
And each has n high-voltage output terminals Q1 to Qn.
A signal from the power recovery circuit 148 is input from the input terminal 165 and supplied to the high-voltage power supply terminal 71 of each driver IC 67. High voltage output terminal group 1 of address drive circuit 33
66 is connected to the display panel 30.

FIG. 18 shows one power recovery circuit 148 and one address drive circuit 33.
C67 is divided into several groups, and each group has a power recovery circuit.
148 may be provided.

Here, the driver ICs 67-1 to 67-n
1 is the same as that of the driver IC 67 of FIG. 1, and a reverse current limiting switch 96 is provided in the high voltage output stage 75 to control the conduction / non-conduction of the current path from the terminal 84 to the terminal 80.

According to the sixth embodiment described above, when a continuous high pulse is output, a display device is provided which does not have a step in the high voltage output, suppresses an increase in loss, and reduces power loss. can do. In addition, since power loss is reduced, power can be used for high image quality such as an increase in gradation, and a display device with high image quality can be provided.

FIGS. 9, 20 and 2 show a seventh embodiment.
2 will be described.

FIG. 20 is provided with signal paths indicated by high-voltage power supply blocks 145 to 161 in addition to FIG.
Duplicate description will be omitted. 9 is also omitted.

FIG. 22 is different from FIG. 21 in that the high voltage power supply terminal 16
7 is provided. Each of the driver ICs 67-1 to 67-67 from the high-voltage power supply block 145 via the high-voltage power supply terminal 167
−n high-voltage power supply terminal 71. A signal supplied from the power recovery circuit 148 via the input terminal 165 is input to the recovery power supply terminal 105 of each of the driver ICs 67-1 to 67-n.

Here, the driver ICs 67-1 to 67-n
Is similar to that of the driver IC 67 in FIG. 9, and the high-voltage power supply terminal 71 and the recovery power supply terminal 105 are provided independently. Although one power recovery circuit 148 and one address drive circuit 33 are shown in FIG. 20, the driver ICs 67 may be divided into several groups, and a power recovery circuit 148 may be provided for each group.

According to the present embodiment, by separating the power supply terminals of the high-voltage logic section and the high-voltage output stage, the load capacity at the time of power recovery can be reduced, and the efficiency of the output stage MOSFET can be increased by speeding up the operation of the output stage MOSFET. Thus, it is possible to provide a display device capable of causing resonance in a specific manner and thereby enhancing the power loss reduction effect.

An eighth embodiment will be described with reference to FIGS. 10, 20, and 22.

In this embodiment, the configuration of the driver IC 67 in the address drive circuit 33 is the same as the configuration of the driver IC 67 in FIG. 10 in the same configuration as in FIGS. 20 and 22. 10, FIG. 20, and FIG.

According to this embodiment, the power supply terminal for the abnormal discharge and the power supply terminal of the high voltage output stage are separated from each other, so that it is possible to provide a display device having a sufficient resistance to the abnormal discharge while maintaining the effect of power recovery.

The ninth embodiment will be described with reference to FIGS. 11, 20, and 22.

In this embodiment, the configuration of the driver IC 67 in the address drive circuit 33 is the same as the configuration of the driver IC 67 of FIG. 11 in the same configuration as that of FIGS. 20 and 22. 11, FIG. 20, and FIG.

According to the present embodiment, the high voltage power supply for the high voltage logic unit 74 and the backflow protection diode 111 is shared,
The effects of the seventh and eighth embodiments can be realized while simplifying the wiring of the driver IC 67 and the wiring around it.

The tenth embodiment will be described with reference to FIGS.
This will be described with reference to FIG.

In this embodiment, the configuration of the driver IC 67 in the address drive circuit 33 is the same as the configuration of the driver IC 67 in FIG. 13 in the same configuration as in FIGS. 20 and 22. 13, FIG. 20, and FIG.

According to the present embodiment, the high-voltage logic section and the power supply terminal of the high-voltage output stage are separated, and the pull-up switch is a high-gate withstand voltage and high-voltage nMOSFET, thereby lowering the initial resistance of recovery and improving the power recovery effect. In addition, it is possible to provide a display device with an improved power loss reduction effect.

The eleventh embodiment will be described with reference to FIGS.

FIG. 23 shows the high-voltage output means 75 in FIG.
As the high-voltage logic unit 74, embodiments other than those shown in FIGS. 6B, 8, 13 and 12 are shown. The high-voltage output means 75 includes a high-voltage nMOSFET 900 corresponding to the pull-up switch 85, a parallel diode 86 inherent in the high-voltage nMOSFET 900, and a gate-source voltage when outputting a high-voltage power supply level HV (hereinafter HV level). , A zener diode 920 for protecting the generated voltage from exceeding the gate-source breakdown voltage of the high-voltage nMOSFET 900, a high-voltage nMOSFET 90 corresponding to the pull-down switch 87, and a parallel diode 88 thereof.

The high voltage logic unit 74 includes a level conversion circuit composed of a high gate withstand voltage high voltage pMOSFET and a high voltage nMOSFET shown in FIG. 12, a high voltage diode 1231 and a high voltage nMOSFE.
It consists of T1270.

The low voltage logic circuit 73 mainly comprises a shift register, a data latch circuit, and a low voltage drive circuit 7300 as shown in FIG. Data input terminal 68a
Is input to the low voltage drive circuit 7300 via the data latch circuit, and at the same time, passes through the shift register circuit and is output from the data output terminal 68b. A clock signal is input to the shift register, a latch control signal is input to the data latch circuit, and a power recovery control signal and the latched address data signal are input to the low voltage drive circuit.

Next, main circuit operations of the recovery circuit and the driver IC 67 used therein will be described.

Since the pull-up switch 85 is a normal high-voltage nMOSFET 900 having a low gate withstand voltage (for example, 5 V), the time corresponding to t1 and t5 in FIG. Can be shorter. As a result, the speed of the power recovery operation can be increased, so that high-efficiency power recovery can be achieved even in a high-definition display having a large number of data lines.

The reason that the times t1 and t5 can be shortened is that the high gate withstand voltage high voltage MOSFET cannot achieve the full performance unless the voltage of the high voltage power supply level HV is applied between the gate and the source (high ON resistance and small operation current). Normal high pressure nM
This is because in the case of OSFET, when 5 V is applied between the gate and the source, the performance is fully achieved. Further, since the gate oxide film is thin, the threshold voltage can be reduced, which is also advantageous for speeding up.

However, when a normal high-voltage nMOSFET is used on the pull-up side of the high-voltage output stage 75, the high-voltage logic unit 7
4, the power recovery efficiency does not improve even if the circuit of FIG. 12 is used as it is. The reason is described below.

In the first half of the power recovery period (corresponding to t3 and t7 in FIG. 7), among the panel capacitances Cp1 to Cpn (only Cp1 and circuits connected thereto are shown for simplicity in the figure), HV The charge stored in the panel capacitance Cpm charged to the level passes through the high-voltage output terminal Qm, the parallel diode 86, the terminal 80, the high-voltage power supply terminal 71, the inductor L, and the switch SW2, and is collected by the recovery capacitor Cref.
Need to flow into. The potential of Cpm ideally drops to the GND level due to the LCR series resonance.

At this time, when the level conversion circuit of FIG. 12 is used for the high voltage logic unit, the voltage of the output terminal 123 is set to GND.
Must be level. This is a high-voltage nMOSFET125
Is turned on and the output voltage of the terminal 123 is kept at the HV level, the terminal 123 and the terminal 80 are connected via the resistor 910 inside the high voltage output stage 75, and the current flows from the high voltage power supply 65 toward the terminal 80. This is because a predetermined operation cannot be obtained. However, when the voltage of the output terminal 123 is set to the GND level, the charge of Cpm at the HV level flows into the terminal 123 via the resistor 910 and the terminal 901 and the power recovery efficiency is significantly reduced.

In order to prevent this, in the present invention, the terminal 1230 is provided, and the high voltage diode 1231 is provided between the node corresponding to the terminal 123 and the terminal 1230. The anode and cathode of the high-voltage diode 1231 are connected to a node and a terminal 1230, respectively, corresponding to the terminal 123. Even when the high-voltage nMOSFET 127 is turned on to set the node corresponding to the terminal 123 to the GND level, the panel capacitance Cp
No electric charge flows from m to the terminal 123 side.

The terminals shown inside the driver IC 67, for example, 120, 80, 1230, 83, 122, 1
Reference numerals 220, 1221, etc. are virtual terminals, and bonding pads and the like are not there.

In addition to the above, the driver IC shown in FIG.
In order for the 67 to operate normally as a power recovery driver IC, it is necessary to appropriately operate the high-voltage nMOSFETs 90 and 1270. FIG. 24 shows the contents of the operation.
This will be described below using (b). The driving circuit 7300 includes:
It comprises a NOR circuit 7303, a NAND circuit 7304, inverters 7305, 7306, 7307, and a terminal 7
A power recovery control signal is input from the terminal 301, and an address data signal is input from the terminal 7302, and four output signals are sent to the terminals 122, 1220, 1221, and 83 through the logic circuit.
Is input to GND by normal inverter circuit operation
To output a level, the high-voltage nMOSFET 90 is turned on, the high gate withstand voltage high-voltage pMOSFET 125 is turned off, and the high-voltage nMOSFET 127 is turned off.
Is turned on, and when outputting HV level,
nMOSFET 90 is off, high gate withstand voltage high voltage pMOSFET 125
Is turned on, and the high-voltage nMOSFET 127 is turned off.

However, the time t in the first half of the power recovery period
At 3 and t7 (see FIG. 7), the high-voltage nMOSFETs 90 and 1270 are turned off and the high-voltage nMOSFET 1
27 is on, and the high gate withstand voltage high voltage pMOSFET 125 needs to be turned off, which does not match the normal inverter circuit operation.

Therefore, the low-voltage power supply level (hereinafter, referred to as "GND") and the low-voltage power supply level (hereinafter, referred to as "t3" and "t7") in the first half of the power recovery period.
(Vcc level), and the logic of the address data signal is obtained by using the power recovery control signal to make the high-voltage nMOSFETs 90 and 1270 and the high-voltage nMOSFET 127 turn off at the same time only during times t3 and t7.

In FIG. 24B, when the power recovery control signal goes to the Vcc level, the NOR circuit 7303 and the NA
The output of ND circuit 7304 is forced to GND level and Vcc level, respectively, regardless of the address data signal.
Therefore, signals at the GND, Vcc, GND, and GND levels are input to the terminals 122, 1220, 1221, and 83, respectively.
The high voltage nMOSFET 1270 is turned off, and the high voltage nMOSFET 90 is turned off.

When the power recovery control signal is at the GND level, the output voltage level is determined in accordance with the address data signal. Is output, and the normal inverter operation described above is realized.

At the time of power recovery, the resonance frequency changes depending on the capacitance value of the panel capacitance Cp1 and the series resistance value of the circuit.
The values of the times t3 and t7 also change. The panel capacitance value varies depending on the panel manufacturer and the model of the panel, and varies depending on the manufacturing variation between the same manufacturer and the same model. Is appropriately adjusted in accordance with the capacity of the panel that performs power recovery, etc., so that the power recovery efficiency can be improved.

In FIG. 23, high-voltage nMOSFET 127
0 assists the high-voltage nMOSFET 90. When the output terminal Q1 is set to the GND level, the forward voltage drop of the Zener diode 920 looks transient only with the high voltage nMOSFET 90. Therefore, the output of the output terminal Q1 is lowered to the GND level through the resistor 910 using the high-voltage nMOSFET 1270. Therefore, when the forward voltage drop is not a problem, it can be eliminated.

The twelfth embodiment will be described with reference to FIGS. 25 and 26.

FIG. 25 is a diagram showing the high voltage logic unit 74 in FIG.
Is a constant current source drive type level conversion circuit instead of a level conversion circuit using a high gate withstand voltage and high voltage pMOSFET.

The high-voltage logic section 74 includes high-voltage nMOSFETs 1260, 1261, and a high-voltage pMOSF constituting a current mirror circuit.
ET 1250, resistor 1251, zener diode 12
52. Resistance 1251, Zener diode 12
52 functions similarly to the resistor 910 and the zener diode 920 of the high-voltage output stage 75 described above.

FIG. 26 shows a schematic circuit configuration of the low voltage logic circuit 73 in the case of the above high voltage logic circuit. Low voltage drive circuit 73
Other than 10 is the same as FIG. 24 described above. Low voltage drive circuit 73
Reference numeral 10 mainly includes a constant current source 7315 for flowing a small current, a constant current source 7316 for flowing a large current, a logic circuit (not shown) for switching between them, and NOR circuits 7313 and 7314. The reason for having two types of constant current sources, large and small, is that when the output voltage of the output terminal Q1 is switched (at the time of rising and falling), the level conversion circuit is operated at high speed by using a constant current source of a large current.
This is because, in the steady state after switching, the power consumption is reduced by changing to a constant current source having a small current. The constant current sources are both turned off when the output of the NOR circuit 7313 is at the Vcc level. Therefore, when the power recovery control signal reaches the Vcc level, both constant current sources are turned off. As a result, at times t3 and t7 in the first half of the power recovery period, the high-voltage pMOSFET 1250
Gate voltage is raised to HV level, and high-voltage pMOSFE
T1250 turns off. Therefore, the output terminal 1232 of the high voltage logic unit 74 is in a high impedance state, and does not hinder the power recovery operation.

A thirteenth embodiment will be described with reference to FIGS.

FIG. 27 is a circuit diagram showing a high voltage logic unit 74 shown in FIG.
Is implemented by another circuit. In this embodiment, instead of providing the diode 1231 of FIG.
An FET 1272, a high gate withstand voltage and high voltage pMOSFET 1240, and a resistor 1241 are provided. This part does not operate during the normal inverter operation, and operates only when the power recovery control signal becomes the Vcc level at times t3 and t7 in the first half of the power recovery period. Then, the gate voltage of the high gate withstand voltage high voltage pMOSFET 125 is raised to the HV level, and the high gate withstand voltage high voltage pMOSFET 125 is increased.
The FET 125 is turned off.

As can be seen from FIG. 28B, when the power recovery control signal is at the HV level, the NOR circuit 732
3,7324 output are both at GND level and high voltage nM
OSFETs 126 and 127 are both turned off. As a result, at times t3 and t7, the output terminal 123 of the high-voltage logic unit 74 enters a high impedance state, and does not hinder the power recovery operation.

The normal operation of the inverter is the same as that of the above-described embodiment, and the description is omitted.

The fourteenth embodiment will be described with reference to FIG.

FIG. 29 shows a high-voltage output stage 75 in FIG.
High withstand voltage high voltage pMOSFE in parallel with high voltage nMOSFET 900
T 930 is provided, and its gate terminal 931 is connected to the high voltage logic unit 7.
4 is connected to another output terminal 1242 (an inverted signal of the terminal 1230 is output). If a high-voltage nMOSFET is used as the pull-up transistor of the high-voltage output stage 75, the voltage of the output terminal Q1 rises at the time of output rise and H
When approaching the V level, the gate-source voltage becomes 5 V
Then, the load driving capability decreases. As a result, the ultimate voltage at the times t1 and t5 (see FIG. 7) in the latter half of the power recovery period decreases, which also affects the recovery efficiency. Therefore, the high gate withstand voltage and high voltage pMOSFET 930 are operated in parallel to prevent a reduction in the reached voltage. The configuration and operation of the low voltage logic circuit 73 are the same as those in FIG.

The fifteenth embodiment will be described with reference to FIGS.

FIG. 30 shows the high voltage output means 7 in FIG.
5, a high-gate withstand voltage high-voltage nMOSFET 98 (the high-gate withstand voltage high-voltage nMOSFET 98 in FIG.
Same as above). The purpose is the same as that described in the first embodiment.

For this reason, the high-gate withstand voltage and high-voltage nMOSFET 98 which is off during the normal operation is replaced with the GND when the power is recovered.
It is necessary to turn on only the high gate withstand voltage and high voltage nMOSFET 98 of the high voltage output stage 75 corresponding to the output terminal that outputs the level, and keep it off corresponding to the output terminal that outputs the HV level.

Therefore, in this embodiment, the high-voltage logic section 74 is provided with the high-voltage nMOSFET 1280 and the resistor 1281, and the low-voltage logic circuit is provided with the NOR circuit 7334a and the inverters 7338 and 7337.
a was added.

Thus, when the output terminal Q1 goes to the GND level, that is, when the address data signal shown in FIG.
At the cc level, the output of NAND circuit 7334a is Vc
c level, and the high-voltage nMOSFET 1280 is turned off.
Kept at the level. Times t3 and t in the first half of the power recovery period
At 7, the potential of the terminal 80 falls below the HV level, so that a gate-source voltage is generated in the forward direction, and the high gate withstand voltage and high voltage nMOSFET 98 is turned on. Therefore, charge recovery of the panel capacitance Cp1 is performed. On the other hand, when the output terminal Q1 is at the HV level, that is, when the address data signal is GND.
When the level is at the level, when the power recovery control signal goes to the Vcc level, the output of the NAND circuit 7334a goes to the GND level.
As a result, a Vcc level signal is input to the terminal 1283 of the high voltage logic unit 74, the high voltage nMOSFET 1280 is turned on, and the gate voltage of the high gate withstand voltage high voltage nMOSFET 98 is set to G.
High gate breakdown voltage and high voltage nMOSFE
T98 is kept almost off.

At the time of rising of the output, the parallel diode 97 built in the high gate withstand voltage and high voltage nMOSFET 98 operates, so that there is no problem in the rising operation.

A sixteenth embodiment will be described with reference to FIGS.

FIG. 32 shows the high-voltage output stage 75 in FIG.
In this case, a high gate withstand voltage and high voltage pMOSFET 98a is used instead of the high gate withstand voltage and high voltage nMOSFET 98.

Also in the present embodiment, the high gate withstand voltage and high voltage pMOSFET 98a which is off during the normal operation is replaced by the
Only the high gate withstand voltage and high voltage nMOSFET 98 of the high voltage output stage 75 corresponding to the output terminal for outputting the GND level is turned on.
The circuit of the low voltage drive circuit 7340 is configured so as to keep the off state corresponding to the output terminal that outputs the V level.

As described above, in the first to sixteenth embodiments, the PD
Although P has been described as an example, the present invention is not limited to this, and the present invention is effective for a display panel serving as a capacitive load such as an electroluminescent panel or a liquid crystal panel, or a driver IC for driving the display panel.

[0153]

As described above, according to the present invention, a drive circuit and a driver IC for a capacitive load suitable for reducing power loss, and a display device including a display panel serving as a capacitive load are realized. can do.

Specifically, the power recovery efficiency can be improved. In addition, a high-speed power recovery circuit that can support a high-definition display can be obtained. Further, by adjusting the pulse width of the power recovery control signal in accordance with the panel capacity, it is possible to realize an optimal power recovery operation for all types of panels. As a result, high recovery efficiency can be obtained relatively easily.

[Brief description of the drawings]

FIG. 1 illustrates a driver IC and a recovery circuit according to a first embodiment.

FIG. 2 is a schematic view of a PDP and each electrode.

FIG. 3 is a schematic cross-sectional view of a unit cell.

FIG. 4 shows a conventional example of a driver IC and a recovery circuit.

FIG. 5 is an operation waveform of a conventional example.

FIG. 6 shows a conventional high-voltage output stage configuration.

FIG. 7 is an operation waveform of the first embodiment.

FIG. 8 shows a high-voltage output stage configuration of the first embodiment.

FIG. 9 shows a driver IC and a recovery circuit according to a second embodiment.

FIG. 10 shows a driver IC and a recovery circuit according to a third embodiment.

FIG. 11 shows a driver IC and a recovery circuit according to a fourth embodiment.

FIG. 12 is a configuration example of a high-voltage logic unit.

FIG. 13 illustrates a driver IC and a recovery circuit according to a fifth embodiment.

FIG. 14 shows a high gate withstand voltage and high voltage nMOSFET.

FIG. 15 is a comparison of a high gate withstand voltage and high voltage nMOSFET.

FIG. 16 shows a high gate withstand voltage and high voltage pMOSFET.

FIG. 17 shows recovery power supply voltage versus on-resistance characteristics.

FIG. 18 shows a display device according to a sixth embodiment.

FIG. 19 is a recovery circuit according to a sixth embodiment.

FIG. 20 shows a display device according to a seventh embodiment.

FIG. 21 is an example of an address drive circuit configuration.

FIG. 22 is a configuration example of an address driving circuit.

FIG. 23 shows a driver IC and a recovery circuit according to the eleventh embodiment.

FIG. 24 shows a low-voltage logic circuit inside the driver IC according to the eleventh embodiment.

FIG. 25 illustrates a driver IC and a recovery circuit according to a twelfth embodiment.

FIG. 26 shows a low voltage logic circuit inside the driver IC according to the twelfth embodiment.

FIG. 27 shows a driver IC and a recovery circuit according to a thirteenth embodiment.

FIG. 28 shows a low-voltage logic circuit inside the driver IC according to the thirteenth embodiment.

FIG. 29 illustrates a driver IC and a recovery circuit according to a fourteenth embodiment.

FIG. 30 shows a driver IC and a recovery circuit according to a fifteenth embodiment.

FIG. 31 shows a low voltage logic circuit inside the driver IC according to the fifteenth embodiment.

FIG. 32 shows a driver IC and a recovery circuit according to a sixteenth embodiment.

FIG. 33 shows a low-voltage logic circuit inside the driver IC according to the sixteenth embodiment.

[Explanation of symbols]

Reference numeral 30: PDP, 33: address drive circuit, 67: driver IC, 71: high-voltage power supply terminal, 73: low-voltage logic circuit, 7
4 high voltage logic section, 75 high voltage output stage, 85, 87, 96
... switch means, 86, 88, 97 ... parallel diodes,
89 high gate withstand voltage high voltage pMOSFET, 98 high gate withstand voltage high voltage nMOSFET, 106, 107 parasitic capacitance, 108 high voltage power supply terminal for recovery, 111, 112 reverse current protection diode 117, 118 on-resistance characteristic, 142 Video signal processing block, 143: control block, 145: high-voltage power supply block, 146, 147, 148: recovery circuit,
7300, 7310, 7320, 7330, 7340 ...
Low voltage drive circuit.

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Koichi Inoue 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Inside Hitachi, Ltd. Hitachi Research Laboratory, Ltd. (72) Inventor Yuji Sano 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture. Address: Hitachi Display Co., Ltd. New Display Business Promotion Center (72) Inventor Hiroshi Ohira 292, Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Hitachi Display Co., Ltd. New Display Business Promotion Center (72) Inventor: Michitaka Osawa Yokohama, Kanagawa Prefecture 292 Yoshida-cho, Totsuka-ku, Hitachi New Display Business Promotion Center, Hitachi, Ltd.

Claims (18)

[Claims] An electric power recovery circuit comprising a capacitor and a coil is connected to a first power supply terminal, and a first power supply terminal having a cathode connected between the first power supply terminal and an output terminal. A first switch means having a parallel diode is connected, and a capacitive load is connected to the output terminal, between the first switch means and the first power supply terminal, or
A second parallel diode having a second parallel diode in a direction opposite to the first parallel diode between the first switch means and the output terminal;
A drive circuit characterized in that the switch means is connected. A first power supply terminal connected to a power recovery circuit including a capacitor and a coil; and a first power supply terminal having a cathode connected between the first power supply terminal and the output terminal. A first switch means having a parallel diode is connected, and a capacitive load is connected to the output terminal. The drive circuit is independent of the first power supply terminal connected to the first switch means. A drive circuit comprising a second power supply terminal connected to high-voltage logic means for controlling one switch means. A first power supply terminal connected to a power recovery circuit including a capacitor and a coil; and a first power supply terminal having a cathode connected between the first power supply terminal and the output terminal. Wherein the first switch means having a parallel diode is connected and a capacitive load is connected to the output terminal, wherein the output is independent of the first power supply terminal connected to the first switch means. A drive circuit, comprising: a third power supply terminal having a terminal connected to a cathode of a diode having an anode connected thereto. 4. The drive circuit according to claim 2, wherein a cathode of said diode having an anode connected to said output terminal is connected to said second power supply terminal. 5. The method according to claim 5, wherein said first switch means has a source-drain withstand voltage greater than a maximum voltage applied to said first power supply terminal, and operates at a voltage lower than a maximum voltage applied to said first power supply terminal. 3. The driving circuit according to claim 2, wherein the nMOSFET has a large gate-source withstand voltage. 6. A power recovery circuit including a capacitor and a coil, a high voltage power supply, and an integrated circuit for driving a capacitive load of a display unit, wherein the integrated circuit includes the power recovery circuit and a first circuit.
And a first switch means having a first parallel diode having a cathode connected to the first power supply terminal, between the first power supply terminal and the output terminal. A capacitive load of a display unit is connected between the first switch means and the first power supply terminal, or between the first switch means and the output terminal, in a direction opposite to the first parallel diode. A second switch means having the second parallel diode is connected. 7. A power recovery circuit including a capacitor and a coil, a high-voltage power supply, and an integrated circuit for driving a capacitive load of a display unit, wherein the integrated circuit is connected to the recovery circuit and a first power supply terminal;
A first switching means having a first parallel diode having a cathode connected to the first power supply terminal between the first power supply terminal and the output terminal, wherein a capacitive load of a display unit is provided at the output terminal; A drive circuit provided with a second power supply terminal connected to the high-voltage logic means for controlling the first switch means, independently of the first power supply terminal connected to the first switch means, The display device, wherein the first power supply terminal is connected to the recovery circuit, and the second power supply terminal is connected to the high voltage power supply. 8. A power recovery circuit including a capacitor and a coil, a high-voltage power supply, and a drive circuit for driving a capacitive load of a display unit, wherein the drive circuit is connected to the recovery circuit and a first power supply terminal;
A first switching means having a first parallel diode having a cathode connected to the first power supply terminal between the first power supply terminal and the output terminal, wherein a capacitive load of a display unit is provided at the output terminal; Connected to a first power supply terminal connected to the first switch means, the drive circuit having a third power supply terminal connected to a cathode of a diode having an anode connected to the output terminal. A display device comprising an IC, wherein the first power supply terminal is connected to the recovery circuit, and the third power supply terminal is connected to the high-voltage power supply. 9. A driving circuit in which a cathode of said diode having an anode connected to said output terminal is connected to said second power supply terminal, said first power supply terminal being connected to said recovery circuit, The display device according to claim 7, wherein the second power supply terminal is connected to the high-voltage power supply. 10. The first switching means has a source-drain breakdown voltage greater than a maximum voltage applied to the first power supply terminal, and is higher than a maximum voltage applied to the first power supply terminal. The driving circuit comprising an nMOSFET having a gate-source withstand voltage, wherein the first power supply terminal is connected to the recovery circuit, and the second power supply terminal is connected to the high-voltage power supply. Item 8. The display device according to Item 7. 11. A circuit for driving a capacitive load, comprising: a first parallel diode between a first power supply terminal and an output terminal, the first parallel diode having a cathode connected to the first power supply terminal.
Is connected between the first switch means and the first power supply terminal, or
A second parallel diode having a second parallel diode in a direction opposite to the first parallel diode between the first switch means and the output terminal;
An integrated circuit, wherein said switch means is connected. 12. A circuit for driving a capacitive load, comprising a first parallel diode between a first power supply terminal and an output terminal, the first parallel diode having a cathode connected to the first power supply terminal.
And a second power supply terminal connected to high-voltage logic means for controlling the first switch means, independently of the first power supply terminal connected to the first switch means. Integrated circuit characterized. 13. A circuit for driving a capacitive load, comprising: a first parallel diode between a first power supply terminal and an output terminal, the first parallel diode having a cathode connected to the first power supply terminal.
Is connected between the first switch means and the first power supply terminal, or
A second parallel diode having a second parallel diode in a direction opposite to the first parallel diode between the first switch means and the output terminal;
And a second power supply terminal connected to high-voltage logic means for controlling the first switch means, independently of the first power supply terminal connected to the first switch means. Integrated circuit characterized. 14. A circuit for driving a capacitive load, wherein a first parallel diode having a cathode connected to the first power supply terminal is provided between a first power supply terminal and an output terminal.
And a third power supply terminal connected to a cathode of a diode having an anode connected to the output terminal, independently of the first power supply terminal connected to the first switch means. An integrated circuit characterized by the above. 15. A circuit for driving a capacitive load, wherein said first switch means has a source-drain breakdown voltage greater than a maximum voltage applied to said first power supply terminal,
14. An nMOSFET having a gate-source withstand voltage larger than a maximum voltage applied to the first power supply terminal.
An integrated circuit as described. 16. A circuit for driving a capacitive load, wherein a third switch means is connected between a fourth power supply terminal connected to the lowest potential and an output terminal, and a signal output to the output terminal. An integrated circuit having logic means for forcibly turning off the third switch means only for a predetermined period of the power recovery period irrespective of a data signal for determining the level of the third switch. 17. The integrated circuit according to claim 16, further comprising a first control terminal to which a control signal for operating said logic means is input during said predetermined period of said power recovery period. 18. A display device using the integrated circuit according to claim 16.