JP2000172380A - Microcomputer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To load a reset vector corresponding to a prescribed address in an internal RAM area and to restart after resetting by using program data already transferred to the internal RAM area when resetting while the data of the internal RAM area is maintained in an energized state after the program data is transferred from an external ROM to the internal RAM area. SOLUTION: When starting after power is applied, a reset signal/reset is 0(zero) V, a candidate value 1 corresponding to a prescribed address of an external ROM 3 is selected as a reset vector, and the start is performed by program data in the ROM 3. When reset is performed in an energized state, the reset signal/reset is 7 V, a candidate value 2 corresponding to a prescribed address of an internal RAM area 25 is selected as a reset vector, and start is performed by program data in the area 25.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to a microcomputer which can be reset while retaining data in an AM area, and more particularly to a microcomputer which can initialize a program counter in the microcomputer based on an arbitrary reset vector among a plurality of reset vectors after reset. About computers.

[0002]

2. Description of the Related Art Generally, a microcomputer having a RAM (random access memory) area internally executes a program stored in an externally connected ROM (read only memory) when executing program data stored in an external ROM.
The data is transferred from the OM to the internal RAM area, and the program data is read from the internal RAM area and executed.

[0003] When such a microcomputer is reset, as shown in FIG.
The reset signal / reset (the signal preceded by “/” in this specification indicates low active) is input to the Schmitt inverter circuit 12.
Reset circuit 13 inside the microcomputer
Sent to The reset circuit 13 determines whether the reset signal / reset is active,
When active, an address value based on a predetermined reset vector is loaded into a program counter (not shown) in the microcomputer and is initialized.

[0004]

In the configuration of the conventional reset circuit shown in FIG. 4, the reset signal / reset is active or inactive, that is, whether the reset signal / reset is "L (low)" having a relatively low potential level. Only a binary state of “H (high)” having a high level can be identified. The value of the address initially loaded into the program counter, that is, the reset vector has a fixed value. Therefore, when the reset signal / reset is active, the same reset vector is always loaded into the program counter.

Therefore, the reset vector corresponds to a predetermined address in the external ROM, and the program data is transferred from the external ROM to the internal RAM area, and is operated by the program data stored in the internal RAM area. When the microcomputer is reset while retaining the data in the internal RAM area and the same program is restarted, the program is transferred from the external ROM to the internal RAM area again even though the program data has already been transferred to the internal RAM area. Since data is transferred, there is an inconvenience that it takes time to restart after reset.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems. In a microcomputer having an internal RAM area and capable of resetting while retaining data in the internal RAM area in the energized state, the present invention provides Internal RAM
When resetting while retaining the data in the area, the internal R
A reset vector corresponding to a predetermined address in the AM area can be loaded, so that once the program data is transferred from the external ROM to the internal RAM area, the program data transferred to the internal RAM area is used. To obtain a microcomputer which can be restarted after reset.

[0007]

In order to achieve the above object, the present invention relates to a microcomputer having an internal RAM area and capable of resetting while holding data in the internal RAM area in an energized state. A vector table storing a plurality of reset vectors corresponding to the addresses of the reset terminal, a reset terminal to which two or more different levels of voltage can be applied at the time of reset, and the vector corresponding to the voltage level applied to the reset terminal. A selection circuit for selecting one of the reset vectors from the table, and a program counter for storing the reset vector selected by the selection circuit are provided.

According to the present invention, in a microcomputer having an internal RAM area and capable of resetting while holding data in the internal RAM area in an energized state, a plurality of reset vectors corresponding to a plurality of different addresses are vectorized. At the time of resetting, two or more levels of voltages different from each other can be applied to the reset terminal, and the selection circuit corresponds to the voltage level applied to the reset terminal. One of the reset vectors is selected, and the selected reset vector is stored in the program counter.

In the present invention, at least one of the plurality of reset vectors is capable of arbitrarily changing a corresponding address, and includes a port for setting a corresponding address of the reset vector. Is also good.

According to the present invention, at least one reset vector can be arbitrarily changed via the port.

The present invention has an internal RAM area and is connected to an external ROM storing program data. The program data is transferred and stored in the internal RAM area, and stored in the internal RAM area. A microcomputer that can read and execute the program data that has been reset and hold the data in the internal RAM area while being energized, and that correspond to a predetermined address in the external ROM and a predetermined address in the internal RAM area, respectively. The first reset vector and the second reset vector
A reset table to which two different levels of voltage can be applied at the time of reset, and one of the reset vectors from the vector table corresponding to the voltage level applied to the reset terminal. And a program counter for storing the reset vector selected by the selection circuit.

According to the present invention, the internal RAM area is connected to the external ROM storing the program data, the program data is transferred to the internal RAM area and stored, and the program data is stored in the internal RAM area. A microcomputer which can read out and execute the program data stored therein and reset the data in the energized state while retaining the data in the internal RAM area, wherein a first address corresponding to a predetermined address in the external ROM and a first address corresponding to the predetermined address in the internal RAM area, And the second reset vector are stored in the vector table,
At the time of reset, two different levels of voltage can be applied to the reset terminal. One of the reset vectors is selected from a vector table by a selection circuit in accordance with the voltage level applied to the reset terminal, The selected reset vector is stored in the program counter.

In the above invention, the selection circuit is configured to select a reset start signal for starting initialization of a program counter and a reset vector candidate based on a voltage level applied to the reset terminal. Generate a candidate selection signal.

According to this invention, the reset circuit generates the reset start signal and the candidate selection signal based on the voltage level applied to the reset terminal, and starts the initialization of the program counter based on each of the signals. And a reset vector candidate is selected.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of a microcomputer according to the present invention will be described in detail with reference to the accompanying drawings.

Embodiment 1 FIG. 1 is a block diagram showing a main part of the microcomputer according to the first embodiment of the present invention. The microcomputer 2 has, for example, three voltage levels, for example, but not limited to, 0 voltage levels.
(Zero) V, a reset terminal 20 to which a reset signal / reset of a voltage level of 3 to 5 V and 7 V is input, a vector table 21 storing two candidate values (candidate value 1 and candidate value 2) of the reset vector, and reset Signal / r
a selection circuit 22 for selecting a reset vector candidate value from the vector table 21 based on the voltage level of the reset, and a decoder 2 for decoding an output signal of the selection circuit 22
3. Program counter 24 comprising a register for storing the selected reset vector, and internal RAM area 2
5 is provided.

The microcomputer 2 has an external RO storing, for example, configuration data (program data) of a program executed by the microcomputer 2.
M3, and further includes an instruction register 26 for storing the instruction word value read from the external ROM 3 and the internal RAM area 25, and an instruction decoder 27 for decoding the instruction word value.

Between the program counter 24 and the internal RAM area 25, and between the program counter 24 and the external RO
Each is connected to M3 by an address bus. Between the internal RAM area 25 and the instruction register 26,
The external ROM 3 and the instruction register 26 are connected by a data bus.

Since other details not related to the reset are not related to the present invention, illustration and description are omitted.

The reset vector candidate value 1 corresponds to, for example, a predetermined address in the external ROM 3 and is selected when the microcomputer 2 first starts up after the power is turned on.

The reset vector candidate value 2 corresponds to a predetermined address in the internal RAM area 25, for example.
This is selected when the microcomputer 2 is reset while the data in the internal RAM area 25 is held in the energized state.

FIG. 2 is a circuit diagram showing an example of the selection circuit 22. The selection circuit 22 includes a Schmitt inverter circuit 41, an inverter circuit 42, a P-channel MOS transistor (hereinafter, referred to as PMOS) 43, and an N-channel MOS transistor (hereinafter, referred to as NMOS) 44.

The Schmitt inverter circuit 41 receives a reset signal / reset and receives a reset start signal Ss
Output t. For example, reset start signal Sst is at “H” level when the voltage levels of reset signal / reset are 0 (zero) V and 7 V, and
When the reset voltage level is 3-5 V, it is at the "L" level. Only when the reset start signal Sst is at “H” level, the initialization of the program counter 24 is started.

The PMOS 43 and the NMOS 44 are CM
An OS inverter circuit is configured, and their drains are commonly connected to input terminals of the inverter circuit 42, and their gates are commonly connected to a power supply Vcc line. The source of the PMOS 43 is connected to a reset signal / re.
The source of the NMOS 44 is connected to the ground Vss line.

The threshold voltage of the PMOS 43 is, for example, when the voltage level of the reset signal / reset is 0 (zero) V or 7 V, that is, when the source potential of the PMOS 43 is 0
It is adjusted to be in the off state or the on state at (zero) V or 7 V, respectively. Similarly, NMOS4
4 is, for example, the reset signal / reset
Is adjusted to be in an on state regardless of whether the voltage level is 0 (zero) V or 7 V.

Therefore, when the voltage level of the reset signal / reset is 0 (zero) V, the output of the CMOS inverter circuit is 0 (zero) V. That is, an "L" level signal is input to the inverter circuit 42. Therefore, the inverter circuit 42 outputs the “H” level candidate selection signal Ssel to the decoder 23. On the other hand, when the voltage level of the reset signal / reset is 7 V, the CMO
The output of the S inverter circuit is a PMOS 43 and an NMO
The potential determined by each ON resistance of S44, that is, an intermediate potential between 0 (zero) V and 7V (about 3 to 5V)
Becomes In other words, an “H” level signal is input to the inverter circuit 42, so that the inverter circuit 4
2 is at “L” level.

The decoder 23 outputs a signal S1 for selecting the reset vector candidate value 1 when the candidate selection signal Ssel is at "H" level, and outputs a reset vector candidate when the candidate selection signal Ssel is at "L" level. A signal S2 for selecting the value 2 is output.

That is, when the voltage level of the reset signal / reset is 0 (zero) V, the reset start signal Ss
Both t and the candidate selection signal Ssel become “H” level, the reset value is selected to select the reset vector candidate value 1, and the reset is started. Therefore, the program fetch is started from the program data of the external ROM 3 at a predetermined address. Since this corresponds to the process at the time of the first startup immediately after the power is turned on, the reset signal / reset at the time of the startup immediately after the power is turned on is set.
t is 0 (zero) V.

When the voltage level of the reset signal / reset is 3 to 5 V, the reset start signal Sst becomes "L" level, and the reset is not started. Since this corresponds to the case where the microcomputer 2 is performing the normal operation, the reset signal / reset input to the reset terminal 20 during the normal operation is 3 to 5V.

When the voltage level of the reset signal / reset is 7 V, the reset start signal Sst is "H".
Level, while the candidate selection signal Ssel goes to the “L” level, so that the reset is started by selecting the candidate value 2 of the reset vector, so that the program fetch starts from the program data of the internal RAM area 25 at a predetermined address. Is done. This is because the internal RAM area 25
And the reset signal / reset at that time is 7V.

Next, the operation of the first embodiment will be described. When the microcomputer 2 is first started immediately after the power is turned on, a reset signal / reset of 0 (zero) V is input to the reset terminal 20. As a result, the selection circuit 22 outputs the “H” level reset start signal Ss
A candidate selection signal Ssel of t and “H” level is generated, and these signals Sst and Ssel are sent to the program counter 24 and the decoder 23, respectively. The program counter 24 enters the reset vector loading start state in response to the input of the reset start signal Sst. On the other hand, the decoder 23 selects the reset vector candidate value 1 in response to the input of the candidate selection signal Ssel.

The program counter 24 loads the candidate value 1 of the reset vector, whereby the instruction word value at a predetermined address in the external ROM 3 is sent to the instruction register 26, decoded by the instruction decoder 27, and read from the external ROM 3 to the internal RAM. Transfer of the program data to the area 25 is started.

Thereafter, the normal operation is started, and the address of the internal RAM area 25 is sequentially loaded into the program counter 24, and the microcomputer 2 sequentially reads the instruction word value corresponding to the address from the internal RAM area 25, and reads the instruction word value. Instruction decoder 27 via register 26
, And sends an instruction to each relevant unit. During the normal operation, the reset signal / reset is not active because the potential level of the reset signal / reset is 3 to 5V.

In this state, that is, in the energized state, the internal RAM
When the microcomputer 2 is reset while holding the data in the area 25, a reset signal / reset of 7 V is input to the reset terminal 20. Then, the selection circuit 22 generates an “H” level reset start signal Sst and an “L” level candidate selection signal Ssel, and sends these signals Sst and Ssel to the program counter 24 and the decoder 23, respectively.

As a result, the program counter 24
The reset vector candidate value 2 is loaded, and the addresses of the internal RAM area 25 are sequentially loaded. The microcomputer 2 sequentially reads out the instruction word values corresponding to the loaded addresses from the internal RAM area 25, decodes them by the instruction decoder 27 via the instruction register 26, and sends instructions to the relevant sections.

According to the first embodiment, the external ROM 3
And reads out the program data transferred to the internal RAM area 25 from the internal RAM area 25 and executes it.
In the microcomputer 2 that can be reset while holding the data in the area 25, (1) the reset signal / re
During normal operation when set is 3 to 5 V, it is not reset,
(2) When the power is turned on when the reset signal / reset is 0 (zero) V, a reset vector corresponding to a predetermined address in the external ROM 3 is selected, and the program data in the external ROM 3 is read and started. At the time of reset in the energized state where the reset signal / reset is 7 V, a reset vector corresponding to a predetermined address in the internal RAM area 25 is selected, and program data in the internal RAM area 25 is read to start. Since it is not necessary to re-transfer the program data at the time of reset in the energized state, it is possible to quickly restart.

Embodiment 2 FIG. 3 is a block diagram illustrating a main part of the microcomputer according to the second embodiment of the present invention. The microcomputer 200 according to the second embodiment is different from the first embodiment shown in FIG. 1 in that the reset vector candidate value 2 in the vector table 21 can be changed, and the microcomputer 200 Is provided with a port 28 for changing Other configurations are the same as those of the first embodiment, and thus, the same components as those of the first embodiment are denoted by the same reference numerals and description thereof will be omitted.

The candidate value 2 is calculated by the microcomputer 200
The voltage is set by reading the applied voltage level of an external input terminal provided outside through the port 28. The change of the candidate value 2 is performed, for example, by switching the voltage applied to the external input terminal using hardware such as a switch.

According to the second embodiment, at the time of reset in the energized state, the reset vector candidate value 2 is set to the value corresponding to the predetermined address in the internal RAM area 25 via the port 28, and the reset vector 2 Is selected, the program data in the internal RAM area 25 can be read out and started in the same manner as in the first embodiment, so that the program data does not need to be re-transferred at the time of reset in the energized state. Can be restarted.

According to the second embodiment, the port 28
Since the reset vector can be arbitrarily changed through the resetting, the program counter 24 can be dynamically initialized at the time of reset by setting an appropriate reset vector to the port 28 for each reset. The program to be restarted after reset can be started from an arbitrary state, or the program to be started after reset can be changed.

In the above, the present invention provides a vector table 2
1, three or more reset vector candidate values are stored, and a reset signal / reset having a multi-value level capable of individually selecting these candidate values is supplied to the reset terminal 20 to supply three or more reset vector candidate values. Any of the candidate values may be selected.

[0042]

As described above, according to the present invention, one of a plurality of reset vectors is selected from a vector table corresponding to a voltage level applied to a reset terminal, and the selected reset vector is selected. Since the vector is stored in the program counter, for example, when the power is turned on, a reset vector corresponding to a predetermined address in the external ROM is selected, whereby the internal RA is stored in the external ROM.
When the program is started after transferring the program data to the M area, and the reset is performed while the data in the internal RAM area is held in the energized state, a reset vector corresponding to a predetermined address in the internal RAM area is selected, thereby By restarting using the program data held in the internal RAM area without re-transferring the data, it is possible to quickly restart when resetting in the energized state.

According to the present invention, at least one reset vector can be arbitrarily changed via a port. Therefore, by setting an appropriate reset vector to the port for each reset, the program at the time of reset can be changed. Since the counter can be initialized dynamically, a program to be restarted after reset can be started from an arbitrary state, or a program to be started after reset can be changed.

According to the next invention, one of the two reset vectors is selected from the vector table in accordance with the voltage level applied to the reset terminal, and the selected reset vector is stored in the program counter. Therefore, when the power is turned on, a reset vector corresponding to a predetermined address in the external ROM is selected, whereby the program data is transferred from the external ROM to the internal RAM area, and then the internal RAM area is activated. When the reset is performed while retaining the data, a reset vector corresponding to a predetermined address in the internal RAM area is selected, thereby using the program data retained in the internal RAM area without transferring the program data again. Restarts quickly when power is on and resets. It can be dynamic.

According to the next invention, the reset start signal and the candidate selection signal are generated based on the voltage level applied to the reset terminal, and the initialization of the program counter is started based on the respective signals. Since the reset vector candidate is selected, it is possible to select an appropriate reset vector from a plurality of reset vectors and restart using the reset vector.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a main part of a microcomputer according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of a selection circuit of the microcomputer.

FIG. 3 is a block diagram illustrating a main part of a microcomputer according to a second embodiment of the present invention;

FIG. 4 is a schematic diagram showing a flow of a reset signal from a reset terminal to a reset circuit in a conventional microcomputer.

[Explanation of symbols]

Sst reset start signal, Ssel candidate selection signal,
2,200 microcomputer, 20 reset terminal, 21 vector table, 22 selection circuit, 24 program counter, 25 internal RAM area, 28 ports, 3 external ROM.

Claims (4)

[Claims] 1. A microcomputer having an internal RAM area and capable of resetting while holding data in the internal RAM area in an energized state, a vector table storing a plurality of reset vectors corresponding to a plurality of addresses different from each other. A reset terminal to which two or more different levels of voltage can be applied at the time of reset; a selection circuit for selecting any one of the reset vectors from the vector table in accordance with the voltage level applied to the reset terminal; A program counter for storing a reset vector selected by the selection circuit. 2. The method according to claim 1, wherein at least one of the plurality of reset vectors is capable of arbitrarily changing a corresponding address, and includes a port for setting a corresponding address of the reset vector. The microcomputer according to claim 1, wherein: 3. A program which has an internal RAM area, is connected to an external ROM storing program data, transfers and stores the program data to the internal RAM area, and stores the program data stored in the internal RAM area. While reading and executing data, the internal R
A microcomputer capable of resetting while holding data in an AM area, wherein a predetermined address in the external ROM and the internal RAM
A vector table storing a first reset vector and a second reset vector respectively corresponding to a predetermined address in an area, a reset terminal to which two different voltages can be applied at the time of reset, and a reset terminal applied to the reset terminal. A selection circuit for selecting one of the reset vectors from the vector table in accordance with the voltage level, and a program counter for storing the reset vector selected by the selection circuit. . 4. A reset start signal for starting initialization of a program counter based on a voltage level applied to the reset terminal, and a candidate selection signal for selecting a reset vector candidate. 4. The microcomputer according to claim 1, wherein the microcomputer generates: