JP2000163955A - Refresh timer and adjusting method for its refresh cycle - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a refresh timer and adjusting method for its refresh cycle which can surely compensate refresh cycles with respect to variation at ambient temperature, improves the stability of the refresh cycles, suppresses increase in current consumption, due to the shortening of the refresh cycles and reduces area of a circuit as a whole. SOLUTION: A capacity element 28, a current source 12 which is connected between the capacity element 28 and a ground electrode, a P-channel transistor 20 which charges the capacity element 28 according to a refresh request signal RCLK, and a logic circuit part which detects the potential of the capacity element 28 and generates a refresh request signal RCLK are provided, and then a current source 12 increases in current quantity when the temperature is high and decreases in current quantity when the temperature is low.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a refresh timer for obtaining a predetermined refresh cycle at the time of refreshing a DRAM having a self-refresh function, and a method of adjusting the refresh cycle.

[0002]

2. Description of the Related Art Conventionally, in a DRAM (Dynamic Random Access Memory) having a self-refresh function, a refresh timer has been widely used to obtain a predetermined refresh cycle when the DRAM is refreshed. .

As such a refresh timer, for example, a timer that obtains a predetermined refresh cycle using a ring oscillator and its oscillating frequency, or monitors a leak current of about 1000 memory cells, and monitors the leak current. In some cases, the refresh cycle is adjusted in accordance with the change in the ambient temperature obtained based on the current, and the change due to the change in the ambient temperature in the refresh cycle is compensated.

[0004]

However, in the above-described conventional refresh timer, when the oscillation output of the ring oscillator is used for the refresh timer, the oscillation frequency of the ring oscillator decreases when the ambient temperature rises. When the oscillation frequency is set to satisfy the requirement at high temperature, the oscillation frequency becomes high at low temperature, and the refresh cycle as a refresh timer becomes short at low temperature, and refresh is performed unnecessarily frequently. Therefore, there is a problem that current consumption increases.

On the other hand, the leak current of a memory cell tends to increase when the ambient temperature rises. Based on the change in the ambient temperature obtained by monitoring the leak current, the leak current due to the change in the ambient temperature in the refresh cycle is obtained. Although the change can be compensated for, the leakage current of one memory cell is very small (about several fA) for compensation, so that many (1
It is necessary to monitor the leak current of about 000 memory cells), and there is also a problem that a configuration having a large area as a whole is required due to the circuit arrangement for the monitoring.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned conventional problems, and can surely compensate a refresh cycle for a change in ambient temperature, improve the stability of the refresh cycle, and shorten the refresh cycle. The present invention provides a refresh timer and a method for adjusting the refresh cycle thereof, which can suppress an increase in current consumption due to the above and can reduce the circuit area as a whole.

[0007]

In order to solve the above-mentioned problems, the refresh timer of the present invention increases the refresh cycle when the ambient temperature increases, and decreases the refresh cycle when the ambient temperature is low. This protects the charge retention characteristics from deteriorating due to an increase in leakage current at high temperatures, suppresses unnecessary operating currents at low temperatures, and can rescue memory devices with poor charge retention characteristics, and also consumes current of normal memory devices. Characterized in that the amount is reduced.

Further, the method of adjusting a refresh cycle according to the present invention can relieve a memory element having poor charge retention characteristics, reduce the current consumption of a normal memory element, and improve the refresh cycle. The refresh cycle can be easily adjusted.

As described above, the refresh cycle can be reliably compensated for the change in the ambient temperature, the stability of the refresh cycle can be improved, and the increase in current consumption due to the shortening of the refresh cycle can be suppressed. In addition, the circuit area can be reduced as a whole.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A refresh timer according to a first aspect of the present invention is a refresh timer for obtaining a predetermined refresh cycle when refreshing a memory element, and one end of which is a ground electrode. , A current source connected between the other end of the capacitive element and the ground electrode, and a charging circuit for charging the capacitive element in response to a refresh request signal when refreshing the memory element And a logic circuit unit that generates the refresh request signal when the voltage level of the capacitive element has reached a predetermined potential, wherein the amount of current flowing through the current source is proportional to an increase in ambient temperature. And increase the characteristics.

According to a second aspect of the present invention, there is provided a refresh timer including the current source according to the first aspect, a first P-channel transistor having a source connected to a power supply, a gate and a drain connected to a first node, and a drain. Is connected to a second node, a gate is connected to the first node, and a source is connected to the power supply via a resistor. A second P-channel transistor is connected to the power supply. Are connected to the second node, and a first N-channel transistor whose drain is connected to a ground electrode, and a second N-channel transistor whose source and gate are connected to the second node and whose drain is connected to the ground electrode. A third channel transistor having a gate connected to the second node, a source connected to the ground electrode, and a drain serving as an output node;
And an N-channel transistor.

According to the above configuration, the refresh period increases when the ambient temperature increases, and the refresh period decreases when the ambient temperature is low. Protect and suppress unnecessary operating current at low temperature.

A refresh timer according to a third aspect of the present invention has a configuration in which the current source according to the first aspect is provided with adjusting means for adjusting the amount of current flowing through the current source. A refresh timer according to a fourth aspect of the present invention has a configuration in which the current source according to the first aspect is provided with an adjusting unit that includes a transistor and a fuse element and that adjusts an amount of current flowing through the current source.

According to a fifth aspect of the present invention, there is provided a refresh timer including the current source according to the first aspect, a first P-channel transistor having a source connected to a power supply, a gate and a drain connected to a first node, and a drain. Is connected to a second node, a gate is connected to the first node, and a source is connected to the power supply via a resistor. A second P-channel transistor is connected to the power supply. Are connected to the second node, and a first N-channel transistor whose drain is connected to a ground electrode, and a second N-channel transistor whose source and gate are connected to the second node and whose drain is connected to the ground electrode. A channel transistor and a gate are connected to the second node via a plurality of first fuse elements that can be trimmed, and the channel transistor can be trimmed. Connected to said ground electrode via a second fuse element number, and a plurality of source drain is connected to the ground electrode is an output node a third N
The current source is adjusted by trimming the fuse element of the adjusting unit with the adjusting unit including a channel transistor.

According to the above configuration, it is possible to relieve a memory element having poor charge retention characteristics, and to reduce the current consumption of a normal memory element. According to a sixth aspect of the present invention, there is provided a method of manufacturing a semiconductor memory device including a refresh timer including the adjusting unit according to the third, fourth, and fifth aspects. Is cut by laser irradiation, and the refresh cycle of the refresh timer is adjusted.

According to this method, it is possible to relieve a memory element having poor charge retention characteristics, and to reduce the current consumption of a normal memory element. The method for adjusting a refresh cycle according to claim 7 is a method for adjusting a refresh cycle according to claims 3, 4, and 5.
In the method for manufacturing a semiconductor memory device including a refresh timer provided with the adjusting means according to the above, the adjusting means for adjusting the refresh cycle of the refresh timer is adjusted in a redundant memory replacement process.

According to this method, when the refresh cycle is adjusted, the refresh cycle can be easily adjusted. The refresh timer according to claim 8 is configured such that a plurality of the third N-channel transistors according to claim 5 have a channel width that is twice as large as the channel width of one transistor. , And the other transistor is sequentially configured to have a width twice as large as that of the first transistor, and the channel width of the plurality of third N-channel transistors is configured to be a binary configuration.

According to this configuration, when the refresh cycle is adjusted, the refresh cycle can be easily adjusted in a wide range. Hereinafter, a refresh timer and a method of adjusting a refresh cycle thereof according to an embodiment of the present invention will be specifically described with reference to the drawings.

FIG. 1 is a block diagram schematically showing a configuration of a refresh timer according to an embodiment of the present invention.
In FIG. 1, reference numeral 10 denotes a refresh timer, 11 denotes a detection circuit, and 12 denotes a current source. Refresh timer 1
0 is constituted by the functional blocks of the detection circuit 11 and the current source 12.

FIG. 2 is a circuit diagram of the refresh timer 10 shown in the block diagram of FIG. In FIG. 2, 20,
21 is a P-channel transistor, 22 is an N-channel transistor, 23 is a NAND element, 24, 25 and 26 are inverters, 27 is a delay element having a delay time τ, 28 is a capacitance element having a capacitance CR, and RCLK is a refresh request signal. is there.

The source of the P-channel transistor 20 is connected to the power supply VDD, the drain is connected to the current source 12, the capacitor 28, and the gate of the P-channel transistor 21, and the gate is connected to the output of the inverter 26. The source is connected to the power supply VDD, and the drain is connected to the source of the N-channel transistor 22, the input of the delay element 27, and the input of the NAND element 23. The gate width of the N-channel transistor 22 is selected to be sufficiently smaller than the gate width of the P-channel transistor 21.

The other end of the capacitive element 28 is connected to a ground electrode and is grounded to a ground potential. The output of the delay element 27 is connected to the input of the NAND element 23 via the inverter 25.
The output of the NAND element 23 is output via an inverter 24
It is output as a refresh request signal RCLK and is connected to the input of the inverter 26.

FIG. 3 shows the refresh timer 1 shown in FIG.
FIG. 2 is a circuit diagram showing a configuration of a current source 12 of zero. 3, the current source 12 includes a set of P-channel transistors 31 and 35, a set of N-channel transistors 36, 37 and 39, and a resistance element 38, which are connected in a current mirror type.

The current source 12 has a substrate and a source connected to the power supply voltage VDD, and a gate and a drain connected to the node 3.
2, a substrate and a source are connected to a node 33, and a gate is connected to a node 32.
A P-channel transistor 35 having a drain connected to the node 34; an N-channel transistor 36 having a source and a gate connected to the node 34; a drain connected to the ground; a source connected to the node 32; a gate connected to the node 34; N channel transistor 37 and power supply voltage V
It includes a resistance element 38 connected between DD and node 33, and an N-channel transistor 39 whose gate is connected to node 34, whose source is grounded and whose drain receives an output current.

Next, the refresh timer 1 shown in FIG.
0, the current source 1 shown in FIG.
Operation 2 will be briefly described. N-channel transition
Size and threshold of the star 36 and the N-channel transistor 37
If the value voltages Vtn are equal, an N-channel transistor
Since the data 36 and 37 constitute a current mirror,
The current Io flowing through the N-channel transistors 36 and 37 is
The current also flows through the P-channel transistors 31 and 35. P Cha
The threshold values of the tunnel transistors 31 and 35 are equal to Vtp
Then, the current flows through each of the transistors 31, 35, 36, and 37.
Current Io = β₃₁・ (V₃₂−VDD−Vtp)^Two Io = β₃₅・ (V₃₂−VDD + Io · R₃₈-Vtp)^Two Io = β₃₆・ (V₃₄-Vtn)^Two Io = β₃₇・ (V₃₄-Vtn)^Two Given by Where V₃₂Is the voltage at node 32, V₃₄
Is the voltage at node 34, R ₃₈Is the resistance value of the resistance element 38
You.

[0026] by modifying the above equation from where β ₃₆ = β _37, obtain ^{_{Io = 1 / (R 38 2}} · β 31) · (1- (β 31 / β 35) 0.5) 2. Further, since the N-channel transistor 36 and the N-channel transistor 39 constitute a current mirror, this circuit outputs a current Ia which is a constant multiple of Io.

On the other hand, according to this configuration, it can be seen that the current output from the current source 12 is proportional to 1 / β. That is, the current source 12 shown in FIG. 3 has a characteristic that the current increases when the operating temperature of the circuit is high, and decreases when the operating temperature is low.

Next, the operation of the refresh timer 10 shown in FIG. 2 will be described. A description will be given with reference to a time chart of FIG. 4, where the potential of the gate of the P-channel transistor 21 is VG and the potential of the drain is VD.

When the refresh request signal RCLK is at a low level, the P-channel transistor 20 is off, and the gate potential of the P-channel transistor 21 is lowered by the current source 12. Assuming that the threshold voltage of the P-channel transistor 21 is Vt, the voltage is VDD−V
At time t, the P-channel transistor 21 is turned on, and the drain voltage is charged to VDD. As a result, the refresh request signal RCLK is set to the high level. The refresh request signal RCLK is at a high level for a time τ, during which time the P-channel transistor 2
0 is turned on. One row address is refreshed in the high level period τ. Refresh request signal R
CLK goes low and the P-channel transistor 20
The pause time tREF from turning off the P-channel transistor 21 to turning on the P-channel transistor 21 is given by CR · Vt / Ia.

As described above, according to the configuration of the present invention, the current Ia which determines the length of the pause time tREF has a characteristic that the current increases at high temperatures and decreases at low temperatures. Therefore, the pause time tREF is short at high temperatures and long at low temperatures.

In general, the charge retention characteristics of a DRAM deteriorate at high temperatures, and it is necessary to frequently perform a refresh operation. The use of the refresh timer 10 according to the present configuration makes it possible to shorten the refresh interval at high temperatures and to increase the refresh interval at low temperatures.

In the above embodiment, the output of the current source 12 is the N-channel transistor 39, but a circuit as shown in FIG. 3 may be used. Hereinafter, this circuit will be described.

In the circuit shown in FIG. 3, a circuit shown in FIG. 5 is used instead of N-channel transistor 39. In FIG. 5, 50 to 53 are N-channel transistors, 54 is an operation side fuse element, and 55 is a ground side fuse element. These fuse elements are formed by wiring conductors.

The node 34 has a plurality of operating side fuse elements 5
4 are connected to the gates of N-channel transistors 50 to 53. Also, N-channel transistors 50 to 5
The gates 3 are grounded via the ground-side fuse elements 55, and the drains are similarly grounded. The sources of the N-channel transistors 50 to 53 serve as outputs (output nodes) of the current source 12. Operating fuse element 54
The ground-side fuse element 55 serves as an adjusting unit for adjusting the amount of current flowing from the current source 12.

These N-channel transistors 50 to 53
May be all the same, but each has a binary size channel width of W, 2W, 4W,
It may be set to 8W. Hereinafter, the operation of the circuit shown in FIG. 5 will be described with respect to this binary channel width.

Which of the N-channel transistors 50 to 53 connected to the operating fuse element 54 and the ground fuse element 55 in FIG. 5 is turned on or off is determined by trimming the fuse elements 54 and 55. be able to. The fuse element 5 which is a means for adjusting the amount of current
In trimming 4 and 55, the current amount of the current source 12 is adjusted by cutting by a general laser trimming method or the like. In addition, the adjustment of the current amount adjusting means
For example, it can be included in the replacement process of the redundant memory.

For example, if a chip having a remarkably poor charge retention characteristic is found in a pause time test or the like of a semiconductor circuit, the refresh period needs to be shortened. This may be set based on the pause time tREF, when the current Ia is large. For example, a current flowing when the N-channel transistor 50 is turned on is represented by Iu.
The ground-side fuse element 55 connected to the N-channel transistor 53 is disconnected, and the N-channel transistors 50 to 5 are disconnected.
By cutting the second operation side fuse element 54, a relatively large current Ia = 8Iu can be obtained.

As described above, the trimming is performed so that only the N-channel transistor 50 is turned on so as to minimize the current Ia (Ia = Iu). Case (Ia = Iu + 2Iu + 4Iu + 8Iu)
= 15Iu).

In the above description, the number of N-channel transistors to be connected has been described as four. However, if it is desired to perform adjustment over a wider range, the number may be increased. In that case, it is necessary to increase the number of fuse elements 54 and 55 as well. Conversely, if the range to be adjusted may be narrow, it may be two or three.

With this configuration, a semiconductor chip having poor charge retention characteristics can be relieved. In addition, a DRAM chip having good charge retention characteristics does not perform unnecessary refresh operation, and a DRAM chip with low power consumption can be provided.

[0041]

As described above, according to the present invention, the logic circuit for detecting the amount of charge stored in the capacitance element, the output current increases when the ambient temperature increases, and decreases when the ambient temperature decreases. With such a current source, the refresh cycle can be shortened when the ambient temperature increases, and the refresh cycle can be extended when the ambient temperature decreases.

Further, by using the adjusting means capable of adjusting the amount of current flowing from the current source by trimming the fuse element, it is possible to relieve a memory element having a poor charge retention characteristic and reduce the current consumption of a normal memory element. be able to.

Further, since the gate width of the transistor group that determines the amount of current flowing from the current source is of a binary configuration, the amount of current flowing from the current source can be finely adjusted in a wide range.

As described above, the refresh cycle can be reliably compensated for the change in the ambient temperature, the stability of the refresh cycle can be improved, and the increase in current consumption due to the shortening of the refresh cycle can be suppressed. In addition, the circuit area can be reduced as a whole.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a refresh timer according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a refresh timer according to the embodiment;

FIG. 3 is a circuit diagram showing a configuration of a current source in the refresh timer of the embodiment.

FIG. 4 is a time chart showing the operation of the refresh timer according to the embodiment;

FIG. 5 is a circuit diagram showing a configuration of a refresh cycle adjusting circuit for realizing the refresh cycle adjusting method according to the embodiment of the present invention;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Refresh timer 11 Detection circuit 12 Current source 20, 21 P-channel transistor 22 N-channel transistor 23 NAND element 24, 25, 26 Inverter 27 Delay element 28 Capacitance element 31, 35 P-channel transistor 32, 33, 34 Nodes 36, 37, 39 N-channel transistor 38 Resistance element 50, 51, 52, 53 N-channel transistor 54 Operation side fuse element 55 Ground side fuse element Ia, Iu Current RCLK Refresh request signal VG Voltage waveform at gate of transistor 21 VD Voltage at drain of transistor 21 Waveform

Claims (8)

[Claims] 1. A refresh timer for obtaining a predetermined refresh cycle when refreshing a memory element, comprising: a capacitive element having one end connected to a ground electrode having a ground potential; A current source connected between the ground electrodes, a charging circuit for charging the capacitive element in response to a refresh request signal at the time of refreshing the memory element, and a voltage level of the capacitive element attains a predetermined potential. A refresh circuit comprising: a logic circuit section for generating the refresh request signal in a case where the current source has a characteristic that an amount of current flowing from the current source increases in proportion to an increase in ambient temperature. 2. A current source comprising: a first P-channel transistor having a source connected to a power supply and a gate and a drain connected to a first node; and a drain connected to a second node and a gate connected to the first node. A second P-channel transistor connected to a node and having a source connected to the power supply via a resistance element, a source connected to the first node, a gate connected to the second node, and a drain connected to a ground electrode; A first N-channel transistor connected, a second N-channel transistor having a source and a gate connected to the second node, and a drain connected to the ground electrode;
2. The refresh timer according to claim 1, wherein a third N-channel transistor has a gate connected to the second node, a source connected to the ground electrode, and a drain serving as an output node. 3. The refresh timer according to claim 1, wherein the current source is provided with adjusting means for adjusting the amount of current flowing through the current source. 4. The refresh timer according to claim 1, wherein the current source is provided with an adjusting means comprising a transistor and a fuse element for adjusting an amount of current flowing through the current source. 5. A current source comprising: a first P-channel transistor having a source connected to a power supply and a gate and a drain connected to a first node; and a drain connected to a second node and a gate connected to the first node. A second P-channel transistor connected to a node and having a source connected to the power supply via a resistance element, a source connected to the first node, a gate connected to the second node, and a drain connected to a ground electrode; A first N-channel transistor connected, a second N-channel transistor having a source and a gate connected to the second node, and a drain connected to the ground electrode;
A gate is connected to the second node through a plurality of first fuse elements that can be trimmed, and a gate is connected to the ground electrode through a plurality of second fuse elements that can be trimmed, and a source is connected. Adjusting means comprising a plurality of third N-channel transistors connected to the ground electrode and having a drain serving as an output node, and the amount of current flowing from the current source is adjusted by trimming the fuse element with the adjusting means. The refresh timer according to claim 1, wherein: 6. A method for manufacturing a semiconductor memory device including a refresh timer provided with an adjusting means according to claim 3, 4 or 5, wherein the fuse element of the adjusting means is cut by laser irradiation. Adjusting the refresh cycle of the refresh timer. 7. A method for manufacturing a semiconductor memory device including a refresh timer provided with the adjusting means according to claim 3, 4, and 5, wherein said adjusting means for adjusting a refresh cycle of said refresh timer. The refresh cycle is adjusted in a redundant memory replacement process. 8. A plurality of third N-channel transistors, the channel width of which is twice the channel width of one transistor, the other transistor is twice as wide as the channel width of one transistor, and the other one transistor is 6. The refresh timer according to claim 5, wherein the refresh timer is sequentially configured to have a width twice as large as that of the third N-channel transistor, and the channel width of the plurality of third N-channel transistors is configured to be a binary configuration.