JP2000150536A - Field effect transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To extend the impedance-variable function of an FET, and at the same time to miniaturize a semiconductor circuit of a semiconductor phase shifter and a semiconductor amplifier and the like and to increase functions. SOLUTION: A field effect transistor is provided with a waveguide finger 16 where one end is connected to either a drain or source electrode by bridging, and the other end is connected to the other electrode in a structure being connected or extended by bridging as in the above one end, and a gate electrode finger 11 that is divided into two portions between a drain electrode finger 9 that is adjacent to the waveguide finger 16 or a source electrode finger 10, thus applying a bias independently of the divided gate electrode finger 11.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor (hereinafter referred to as an FET) having an extended impedance variable function.
Or a semiconductor circuit such as a semiconductor phase shifter or a semiconductor amplifier using the FET as a circuit element.

[0002]

2. Description of the Related Art FETs and semiconductor circuits using the same are widely used in various devices such as a microwave band and a millimeter wave band, and are applied to mobile communication, on-vehicle, satellite communication, and the like. ing. FIG. 28 shows an example of a metal pattern structure of a semiconductor circuit called a switched line type phase shifter, which is configured using a conventional FET. The configuration of FIG.
Band 5 bit monolithic GaAs FET phase shifter ”, Iyama et al.
pp1-143.

The phase shifter shown in FIG.
It comprises an output line 2, two SPDT switches 3 and 4, a reference transmission line 5, and a delay transmission line 6, and has a function of realizing two phase states. Input side SP
The DT switch 3 includes two FETs Q1 and Q2 and two resonance inductor lines 7 connected between the drain and the source. The input line 1 is connected to either the reference transmission line 5 or the delay transmission line 6. Means for selectively connecting to On the other hand, the output side SPDT switch 4
Are the two FEs in the same manner as the SPDT switch 3.
TQ3 and Q4 and two resonance inductor lines 7 connected between the drain and the source.
This is a means for selectively connecting the output line 2 to either the reference transmission line 5 or the delay transmission line 6. FE above
A bias is applied to each of TQ1 to Q4 from the outside via a gate bias terminal 8, but a bias circuit and the like for this are omitted in the drawing.

The structure of the above FET will be described in more detail. Since the four FETs have the same structure, an example of the electrode structure of the FET Q1 is shown in FIG. 29 here. The drain electrode fingers 9 and the source electrode fingers 10 are formed in a cross shape with fingers, and the gate electrode fingers 11 are arranged between the drain electrode fingers 9 and the source electrode fingers 10. The gate electrode fingers 11 are connected to each other by a gate connection wiring 12, are led out, and are connected to the gate bias terminal 11. Further, competition with the gate connection wiring 12
In order to avoid interference, the source electrode fingers 10 are drawn out through the air bridge 13.

Next, the operation of the conventional semiconductor phase shifter will be described. First, in a passing state in which 0 V is applied to the gates (G) of the FETs Q1 and Q3 and a pinch-off voltage is applied to the gates (G) of the FETs Q2 and Q4, the drains (D) and the sources (S) of the FETs Q1 and Q3 As shown in FIG. 30A, a low impedance (ON state) represented by an equivalent resistor 14 is provided between the drains (D) and the sources (S) of the FETs Q2 and Q4. As shown in FIG. 30B, the capacitive high impedance (OFF state) represented by the equivalent capacitance 15 is obtained. In the ON state, the drain electrode (D)
And the source electrode (S) have the same potential on one surface and have a low resistance, and the effect of the resonance inductor line 7 remains. On the other hand, in the OFF state, the FET Q
At a frequency at which the capacitances represented by 2 and Q4 and the resonance inductor line 7 connected to each FET resonate in parallel, the state between the drain electrode (D) and the source electrode (S) is cut off. Therefore, the connection between the input line 1 and the delay transmission line 6 and the connection between the delay transmission line 6 and the output line 2 are cut off. On the other hand, since the FETs Q1 and Q3 are conducting, the light enters from the input line 1. The signal is transmitted to the reference transmission line 5
And appears on the output line 2.

Then, the bias applied to each FET is reversed. In this case, on the contrary, the connection between the input line 1 and the reference transmission line 5 and the connection between the reference transmission line 5 and the output line 2 are cut off. At this time, FET Q
Since signals 2 and Q4 have low impedance, a signal incident from the input line 1 passes through the delay transmission line 6 and appears on the output line 2. The electrical length of the delay transmission line 6 is longer than that of the reference transmission line 5, and therefore, when the SPDT switches 3 and 4 are both switched to the delay transmission line 6 compared to when they are switched to the reference transmission line 5 side. Has a longer propagation delay in the phase shifter. As described above, by changing the bias voltage applied to the four FETs, the passing terminals of the SPDT switches 3 and 4 are switched, and by switching the signal propagation path, the delay phase is changed to operate as a phase shifter. .

[0007]

As in the prior art described above, in a configuration in which a line such as a resonance inductor line, a reference transmission line, and a delay transmission line is combined with an FET to perform a phase control action, the line structure Therefore, a substrate area corresponding to the area occupied by the wiring pattern is required, and there is a problem that the circuit scale and the device become large. Also, since the structure is such that the inductor line is provided outside the FET, radio waves are likely to leak due to the coupling between the adjacent inductor lines, and there is an electrical problem that the switch action and the phase shifter performance are deteriorated due to the interference. there were. These problems have become more prominent in a multi-bit phase shifter or the like that needs to realize a large number of phase states.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems. The present invention expands the variable impedance function of an FET, and uses such a semiconductor circuit such as a semiconductor phase shifter or a semiconductor amplifier. The purpose of this is to reduce the size and increase the functionality of the product.

[0009]

An FET according to the first invention
Is connected at one end to one of the drain electrode and the source electrode by a wiring method that does not cause competition or contact with the gate wiring, and the other end is bridged or extended similarly to the one end. Having a waveguide finger connected to the other electrode in the structure described above, and a gate electrode finger divided into two in the length direction between the waveguide finger and an adjacent drain electrode finger or source electrode finger. And the bias is applied independently to the divided gate electrode fingers.

In the FET according to the second aspect of the present invention, the waveguide finger is divided into two in the length direction to form a stub, and the length of the divided waveguide finger is:
It is characterized in that the divided gate electrode fingers provided adjacent thereto are formed so as to have substantially the same length.

Further, the FET according to the third invention has a plurality of waveguide fingers, and the lengths of the divided gate electrode fingers provided adjacent to the respective waveguide fingers are different from each other. It is characterized by.

Further, the FET according to the fourth aspect of the present invention comprises
The FET according to the third aspect is characterized in that the FETs are connected in series such that the drain electrode or the source electrode is electrically connected to each other.

The FET according to the fifth aspect of the present invention extends from one of the drain electrode and the source electrode and is bridged to the other by a wiring method that does not cause competition or contact with the gate wiring. It has two waveguide fingers, and a gate electrode finger is provided between the waveguide fingers, and the width of the other waveguide fingers is wider than the width of the center waveguide finger. I do.

The FET according to the sixth aspect of the present invention extends from one of the drain electrode and the source electrode and is connected to the other by a wiring method that does not cause competition or contact with the gate wiring. And a gate electrode finger is provided between the waveguide fingers, and the center waveguide finger is divided into two to form a stub shape. The width of the finger is wider than the width of the other waveguide finger.

Further, in the FET according to the seventh aspect of the invention, an electrode finger of the same type as the finger is provided so as to be in parallel with the drain electrode finger or the source electrode finger arranged at the outermost position. A gate electrode finger is provided between the electrode finger or the source electrode finger.

Further, in the semiconductor circuit according to the eighth invention, the plurality of FETs according to the first to seventh inventions are connected via a line having a length of １ ／ wavelength at a substantially required frequency. Features.

A semiconductor circuit according to a ninth aspect of the present invention is characterized in that gate electrode fingers of a plurality of FETs according to the first to seventh aspects of the present invention have a shape connected to each other.

A semiconductor circuit according to a tenth aspect of the present invention comprises:
The invention is characterized in that a drain electrode or a source electrode of the first to seventh FETs according to the present invention is connected to each of two output terminals of the hybrid coupler to which power is distributed.

Further, a semiconductor circuit according to an eleventh aspect of the present invention comprises:
The line switching type semiconductor phase shifter is characterized in that the FET according to the present invention is provided in the reference phase transmission line and the delay phase transmission line.

Further, a semiconductor circuit according to a twelfth aspect of the present invention comprises:
According to a seventh aspect of the present invention, two FETs are connected to each other by connecting their drain or source electrode fingers.

Further, a semiconductor circuit according to a thirteenth aspect of the present invention comprises:
It is characterized in that the FET according to the present invention is used for a part of a matching circuit.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. The same reference numerals are given to the same or corresponding components as those in the conventional example shown in FIGS. 28 and 29, and the description will be omitted.

Embodiment 1 FIG. 1 is an FET configuration diagram showing a first embodiment of the present invention according to the first invention. In the FET shown in this figure, a first waveguide finger 16 is disposed at the center thereof, and both ends thereof are respectively connected to a drain electrode (D) and a source electrode via an air bridge 13 so as not to compete with the gate connection wiring 12. (S). A source electrode (S) is provided between the first waveguide finger 16 and the source electrode finger 10 adjacent thereto.
A first adjacent gate electrode finger 17 is provided on the side, and a second adjacent gate electrode finger 18 is provided on the drain electrode (D) side. The first gate bias terminal 19 and the second gate bias It is electrically connected to the terminals 20 respectively.

FIG. 2A shows an equivalent circuit in a state where 0 [V] is applied to all the gates of the FET shown in FIG. In this case, since the gate electrode finger 11 and the channel immediately below the first and second adjacent gate electrode fingers 17 and 18 become conductive, the drain electrode finger 9, the source electrode finger 10, and the first waveguide finger 16 Have the same potential. Therefore, the portion provided with these fingers acts as a one-sided conductor, and in this case, it is represented by an equivalent resistance 14-1 having a small resistance. As a result, the FET functions as a transmission path as a whole, and a state is established between the drain electrode (D) and the source electrode (S) of the FET.

On the other hand, FIG. 2B shows an equivalent circuit in which a bias voltage equivalent to a pinch-off voltage is applied to all the gates of the FET shown in FIG. Gate electrode finger 11 and first and second adjacent gate electrode fingers 17, 1
Since the channel immediately below 8 is cut off, the drain electrode finger 9, the source electrode finger 10, and the first waveguide finger 16 function as independent circuit elements. At this time, a space between the drain electrode finger 9 and the source electrode finger 10 is represented by an equivalent capacitance 15 as in the case of the conventional FET shown in FIG. Further, the first waveguide finger 16 is formed of an independent waveguide conductor 21-1.
It is expressed as As a result, at a frequency lower than the parallel resonance frequency of the inductance and the capacitance of the waveguide conductor, the circuit exhibits inductive reactance. Also, at frequencies higher than the parallel resonance frequency, the circuit will exhibit capacitive reactance.

Further, FIG. 2 shows an equivalent circuit in which 0 [V] is applied to the first gate bias terminal 19 and a bias voltage equivalent to a pinch-off voltage is applied to the second gate bias terminal 20 of the FET shown in FIG. It is shown in (c). In this case, since only the channel immediately below the gate electrode finger 11 and the first adjacent gate electrode finger 17 becomes conductive, the first adjacent one of the drain electrode finger 9, the source electrode finger 10, and the first waveguide finger 16 is formed. Only the portion along the gate electrode finger 17 has the same potential.
Therefore, unlike the case shown in FIG. 2A, only the portion where these fingers are provided acts as a one-sided conductor, and only this portion is a low-resistance transmission line represented by an equivalent resistance 14-2. Function as On the other hand, since the channel immediately below the second adjacent gate electrode finger 18 is cut off, the portion of the first waveguide finger 16 along the second adjacent gate electrode finger 18 functions as an independent circuit element, and It is represented as a conductor 21-2. However, the length is shorter than the entire length of the first waveguide finger 16. Here, since both ends of the independent waveguide conductor are excited in substantially the same phase, this portion is equivalent to FIG.
As shown in (d), it is equivalently displayed as an open-end stub 22. Therefore, when the electrical length of this portion is shorter than １ ／ wavelength, a capacitive susceptance is loaded, and beyond this, an inductive susceptance is loaded up to １ ／ wavelength.

As described above, the FET of this embodiment
By changing the bias applied to the gate bias terminal, the impedance presented can be changed to three types. Therefore, three types of different passing phases can be obtained, and by using these as phase control elements, a small phase shifter can be realized. Here, since the waveguide finger, which is a determining factor of the impedance, is formed in the FET, the pattern is not occupied by the outside of the FET. In addition, this FET configuration prevents the coupling between the waveguide fingers that are the line elements, so that the FE
Leakage and coupling of radio waves when a plurality of Ts are used can be reduced. Further, F which sets all applied biases to 0 [V]
In the ON state of the ET, the line element becomes a part of the conductive portion (drain-source transmission line) of the FET and does not become a stub serving as a reflection source, so that good reflection characteristics can be realized in this state. In addition, since the susceptance can be loaded not only according to the length of the waveguide finger but also according to the length of the first and second adjacent gate electrode fingers, the size of the FET, the drain electrode finger and the source electrode finger can be reduced. Impedance can be set independently of shape, number, etc.
There is an advantage that circuit characteristics that meet the required performance can be realized.
In particular, by making the length of the second adjacent gate electrode finger very short, a very small susceptance can be loaded, which is effective for realizing a phase shifter with a small phase shift amount.

In the present invention, since the drain and the source constituting the FET have an electrically equivalent function, even if the drain and the source in the above configuration and description are reversed, the same effect as in the above description can be obtained. Can be Similarly, it is clear that the same effect as described above can be obtained even if the drain electrode finger and the source electrode finger are reversed.

Embodiment 2 FIG. 3 is an FET configuration diagram showing a second embodiment of the present invention according to the first invention. In the first embodiment, the gate electrode finger 11 has a different length from the first and second adjacent gate electrode fingers 17 and 18. However, in this embodiment, the gate electrode finger 11 is also divided, and the portion on the drain electrode (D) side is controlled simultaneously with the second adjacent gate electrode finger 18, and the portion on the source electrode (S) side is divided into the first electrode. It is configured to control simultaneously with the adjacent gate electrode finger 17. In this case, when the same bias is applied to all the gates, the same as in the first embodiment, FIG.
2A and 2B are realized. Further, a bias voltage equivalent to the pinch-off voltage is applied to the first gate bias terminal 19, and the second gate bias terminal 20
In a state where 0 [V] is applied to the circuit, the equivalent circuit shown in FIG. In this case, the equivalent resistance 14-1 is formed on the drain (D) side, and the independent waveguide conductor 1 is formed.
The parallel circuit of 2-1 and the equivalent capacitance 15-1 is a source (S)
Formed on the side. On the other hand, by reversing the applied bias,
When 0 [V] is applied to the first gate bias terminal 19, the second
When a bias voltage equivalent to a pinch-off voltage is applied to the gate bias terminal 20, an equivalent circuit shown in FIG. 4B is realized. In this case, the equivalent resistance 14-2 is formed on the source (S) side, and the independent waveguide conductor 21-2 is formed.
Is formed on the drain (D) side. Therefore, by appropriately selecting the lengths of the first and second adjacent gate electrode fingers 17 and 18, four different passing phases can be obtained.

Embodiment 3 FIG. 5 is an FET configuration diagram showing a third embodiment of the present invention according to the second invention. The waveguide finger is divided into two in the longitudinal direction to form a stub shape to form the first divided waveguide finger 23 and the second divided waveguide finger 24, and the length of the divided waveguide finger is set. And the lengths of the divided first adjacent gate electrode 17 and second adjacent gate electrode 18 provided adjacent thereto are made substantially equal. As a result, since the open-end stub 22 can be realized together with the equivalent resistor 14 in the FET as in the equivalent circuit shown in FIG. 6, a relatively large capacitive susceptance can be easily realized.

Embodiment 4 FIG. FIG. 7 is an FET configuration diagram showing a fourth embodiment of the present invention according to the second invention. The third embodiment is characterized in that a third gate bias terminal 25 for independently controlling the first adjacent gate electrode finger 17 is provided, as compared with the third embodiment. Thereby, as shown in FIG. 8, in addition to the case of Embodiment 3,
Further, there is an advantage that different susceptances can be loaded. Here, in order to avoid congestion of the gate connection wiring, a case where the fourth gate bias terminal 26 is provided separately is particularly shown.

Embodiment 5 FIG. 9 is an FET configuration diagram showing a fifth embodiment of the present invention according to the third invention. As compared with the first and second embodiments, a second waveguide finger 27 is further provided, and a second adjacent gate electrode finger 18 having a divided structure provided adjacent to each waveguide finger. And third adjacent gate electrode fingers 28 have different lengths, and second and third gate bias terminals 2 for individually controlling them.
0 and 25 are provided. As described above, since there are a plurality of controllable waveguide fingers, a larger number of impedance states can be realized as compared with the first and second embodiments without increasing the FET size. Although the case where the number of waveguide fingers is two is shown here, the invention is not limited to this, and a greater number of waveguide fingers may be provided together with a greater number of drain electrode fingers and source electrode fingers.

Embodiment 6 FIG. FIG. 10 is an FET configuration diagram showing a sixth embodiment of the present invention according to the fourth invention. Compared with the case of the fifth embodiment, the fourth gate bias terminal 26 is further provided to enable individual bias application to the fourth adjacent gate electrode finger 29, and the number of independently controllable waveguide fingers is increased. It is. Thereby, a larger number of phase states can be realized without increasing the size of the FET.

Embodiment 7 FIG. 11 is an FET configuration diagram showing a seventh embodiment of the present invention according to the fourth invention. Here, as an example, two FETs Q1 and Q2 according to the present invention according to the fourth embodiment are used, and their source electrodes S
1 and the drain electrode D1 are connected in series such that they are electrically connected to each other. Since the configuration is such that more controllable electrode fingers can be provided in a small area, more impedance states can be realized. In addition, since periodic impedance discontinuity can be realized,
Frequency response characteristics according to the shape can be realized. In the above example, the case where the FET according to the fourth embodiment is used has been described. However, the invention is not limited to this, and any of the FETs according to the first to sixth embodiments may be used.

Embodiment 8 FIG. FIG. 12 is an FET configuration diagram showing an eighth embodiment of the present invention according to the fifth invention. The third waveguide finger 30 extended from the drain electrode (D) and connected to the source electrode (S) and the third waveguide finger 30 extended from the source electrode (S) to prevent competition or contact with the gate wiring. Fourth waveguide finger 31 bridge-connected to drain electrode (D) via air bridge 13
And a fifth waveguide finger 3 provided between the two waveguide fingers and having both ends connected to a drain electrode and a source electrode via an air bridge 13 or directly.
2 and three fifth waveguide fingers, and a fifth adjacent gate electrode finger 33 is provided between the waveguide fingers to apply a bias from the second gate bias terminal 20. Further, the central fifth waveguide finger 3
The width of the other waveguide finger is wider than the width of the second waveguide finger. In this configuration, since the conductor portion between the drain and source electrodes that does not exhibit the reactance characteristics is wide, the resistance between them is low. Therefore, an FET having a small passage loss is realized.

Embodiment 9 FIG. 13 is an FET configuration diagram showing a ninth embodiment of the present invention according to the fifth invention. The length of the fifth adjacent gate electrode finger 33 is shorter than that of the eighth embodiment. As a result, by changing the applied bias, two different loading susceptances with small parasitic resistance can be realized.

Embodiment 10 FIG. FIG. 14 is an FET configuration diagram showing a tenth embodiment according to the sixth invention. A sixth waveguide finger 34 extending from the drain electrode (D) and connected to the source electrode (S) via the air bridge 13 and a drain electrode (D) extending from the source electrode and via the air bridge 13 ) And a third waveguide finger 35 provided between the two waveguide fingers and having one end electrically connected to the drain electrode and the source electrode via the air bridge 13. Fourth divided waveguide fingers 36 and 37 are provided, and a gate electrode finger is provided between the waveguide fingers.
The bias is applied independently from the first and second gate bias terminals 19 and 20. Further, the width of the central waveguide finger is made wider than the width of the other waveguide fingers. With this configuration, since the stub can be configured by a wide strip conductor, a relatively large capacitive susceptance can be realized.

Embodiment 11 FIG. FIG. 15 is an FET configuration diagram showing an eleventh embodiment of the present invention according to the seventh invention. Inside, a first waveguide finger 16 is provided, and further, an external electrode finger 39 of the same kind as the above-mentioned finger is provided so as to be in parallel with the outermost source electrode finger 38 arranged at the outermost position, and An external gate electrode finger 40 is provided between the plurality of source electrode fingers. In this configuration, in accordance with the bias applied from the first and second gate bias terminals 19 and 20, the conventional capacitor including the equivalent capacitance 15-1 shown in FIG. In addition to a similar parallel circuit, as shown in FIG.
The equivalent capacitance 15-2 by the external electrode finger 39 functioning as the open-end stub can also be realized. As a result, since an inverted L-shaped circuit composed of a capacitance and an inductance can be formed by the FET itself, there is an effect that a small filter circuit with small parasitic components can be realized.

Embodiment 12 FIG. FIG. 17 is an FET configuration diagram showing a twelfth embodiment of the present invention according to the seventh invention. Unlike the eleventh embodiment, the inside has an electrode finger structure similar to that of a conventional FET as shown in FIG. 29, for example, and external electrode fingers 39 are formed on the outer periphery by using a folded structure using the air bridge 13. -1,39-
2 and external gate electrode fingers 40-1 and 40-2. External electrode fingers 39-1, 39-
FIG. 18 shows an equivalent circuit when a pinch-off voltage is applied to the first and second gate bias terminals 19 and 20 at a frequency at which the entire length of 2 is longer than １ ／ wavelength. In this case, the equivalent capacitance 15 and the equivalent inductor 4 were difficult to realize with the FET according to the eleventh embodiment.
1 can be newly realized as a high-pass type inverted L circuit.

Embodiment 13 FIG. FIG. 19 is a semiconductor circuit configuration diagram showing the thirteenth embodiment of the present invention according to the eighth invention. Here, two FETs according to the first embodiment of the present invention are used as the plurality of field effect transistors according to the present invention.
Q1 and Q2 are connected via a first line 42 having a length of と wavelength at a substantially required frequency. In this configuration, the effect of the first line 42 can cancel the reflection in the state where the susceptance or the reactance is loaded, and a semiconductor circuit having good reflection characteristics can be realized. The important point here is that in the FET according to the present invention,
In the so-called ON state, the reflection is only due to the resistance component and is extremely small. Therefore, while the two phase states are realized, it is not necessary to consider the adverse effect of reflection on one of the states. For this reason, the configuration shown here realizes a phase control circuit with good reflection in both phase states. In addition, FET
Is not limited to this, and may be another FET according to the present invention.

Embodiment 14 FIG. FIG. 20 is a semiconductor circuit configuration diagram showing a fourteenth embodiment of the present invention according to the ninth invention. Here, FETs Q1 and Q2 according to the first embodiment are used as the plurality of field effect transistors,
Each is connected via the first line 42, and the same kind of gate electrode fingers are electrically connected to each other,
The bias is applied collectively from the first and second gate bias terminals 19 and 20. Since the configuration is such that a plurality of adjacent FETs are integrated, the size of the semiconductor circuit can be further reduced.

Embodiment 15 FIG. FIG. 21 is a semiconductor circuit configuration diagram showing a fifteenth embodiment of the present invention according to the tenth invention. Each of the two output terminals 44 to which the power of the hybrid coupler 43 is distributed has a drain electrode (D) of the FET Q1, Q2 according to the fifth embodiment having the configuration shown in FIG. ), And the source electrode (S) is connected to the via hole 45 to be grounded. Since the reflection on the input side can be reduced by utilizing the power combining characteristic of the hybrid coupler 43, even when a plurality of phase states are realized, a small-sized semiconductor circuit with low reflection without influence between FETs can be realized. . In addition,
Here, the case where a so-called Lange coupler is used as the hybrid coupler 43 is shown, but the present invention is not limited to this, and another hybrid coupler such as a branch line type hybrid, a rat race circuit, or a broadside coupler may be used.

Embodiment 16 FIG. FIG. 22 is a semiconductor circuit configuration diagram showing the sixteenth embodiment according to the eleventh invention. Conventional FET Q having the structure described in the conventional example
In the line switching type semiconductor phase shifter using 1 to Q4, the reference transmission line 5 and the delay transmission line 6 have, for example, a configuration in which the FET according to the third embodiment of the configuration shown in FIG. 5 is provided. I have. Since the FET according to the present invention capable of realizing different phase states is provided in the transmission line in the line switching type phase shifter, it is possible to increase the number of bits of the phase shifter without increasing the area occupied by the pattern. In particular, if a large amount of phase shift is realized by the line switching type semiconductor phase shifter and a small amount of phase shift is realized by the FET according to the present invention, the advantages of each other can be used effectively.

Embodiment 17 FIG. FIG. 23 is a semiconductor circuit configuration diagram showing a seventeenth embodiment of the present invention according to the twelfth invention. Using two FETs Q1 and Q2 according to the seventh embodiment shown in FIG.
Are connected to each other. Utilizing the fact that one FET according to the invention described so far can switch between the passing state and the reactance and susceptance loading states, the two FETs are combined to form an equivalent inductor 41 and an equivalent capacitance as shown in FIG. 15 to form a low-pass circuit of the π type so that impedance matching can be achieved, and a small-sized low-pass filter can be realized. In addition, the switching of the applied amplitude switches the passing amplitude characteristic and the passing phase characteristic. And a semiconductor circuit capable of performing such operations.

Embodiment 18 FIG. FIG. 25 is a semiconductor circuit configuration diagram showing an eighteenth embodiment according to the twelfth invention. 17 according to the twelfth embodiment shown in FIG.
Two FETs Q1 and Q2 are used to connect the drain electrodes (D) of each other. One FE according to the invention
Using the ability to switch between the passing state and the reactance and susceptance loading states at T, a π-type high-pass composed of an equivalent capacitance 15 and an equivalent inductor 41 as shown in FIG. Form a circuit so that impedance matching can be achieved,
In addition to realizing a small high-pass filter, it is possible to realize a semiconductor circuit capable of switching pass amplitude characteristics and pass phase characteristics by switching an applied bias.

Embodiment 19 FIG. FIG. 27 is a semiconductor circuit configuration diagram showing a nineteenth embodiment according to the thirteenth invention. Here, an amplifier is taken as an example, and the case where the FET according to the invention is used as a part of the input matching circuit is shown. Common source amplification FET46
For example, the FET Q1 shown in FIG. 1 according to the first embodiment is connected to the gate through the first and second matching lines 47 and 48 and the matching stub 49 to form an input matching circuit 50. 0 [V] is applied to all gates of the FET Q1.
Is applied, this FET portion is in the same state as the transmission line, and the input signal is transmitted to the amplification FET. On the other hand, when a pinch-off voltage is applied only to the second gate bias terminal 20 in this state, for example, a capacitive stub is formed in this FET portion. Therefore, even when the characteristics of the amplification FETs change due to temperature changes or aging, or even when the characteristics of the amplification FETs vary under manufacturing conditions, the impedance characteristics of the input matching circuit can be changed by electrical means. , Good matching conditions can be maintained. Thus, the FE according to the present invention
By utilizing the fact that the loading reactance or loading susceptance can be switched stepwise within an arbitrary range by T, a function of adjusting and controlling the matching characteristics by electrical means can be provided to the semiconductor circuit. In the above embodiment,
Although the case where one FET according to the present invention is used has been described, the present invention is not limited to this, and a plurality of FETs according to the present invention
Can be used to provide more precise or broader compensation. Further, in the above embodiment, the case where the FET according to the present invention is used for the input matching circuit of the amplifier has been described. However, the present invention is not limited thereto, and an output matching circuit may be used. A device such as a multiplier may be used. Further, it is apparent that the device is effective even when used in a composite semiconductor circuit such as a module or a BFN circuit in which these devices are composited.

[0047]

According to the first aspect of the invention, one end is bridge-connected to one of the drain electrode and the source electrode and the other end is connected by a wiring method that does not cause competition or contact with the gate wiring. It has a waveguide finger connected to the other electrode in a bridging connection or an extended structure in the same manner as the one end, and between the waveguide finger and the adjacent drain electrode finger or source electrode finger. A gate electrode finger divided into two in the length direction, and a means for independently applying a bias to the divided gate electrode finger is provided. By switching the bias applied to the gate bias terminal, F
The impedance exhibited by the ET can be changed to three types. Therefore, three or four different passing phases can be obtained, and a small phase shifter can be realized by using these as phase control elements. Here, since the waveguide finger, which is a determining factor of the impedance, is formed in the FET, the pattern is not occupied by the outside of the FET. In addition, this FET configuration prevents the coupling between the waveguide fingers that are the line elements, so that the FE
Leakage and coupling of radio waves when a plurality of Ts are used can be reduced. Further, F which sets all applied biases to 0 [V]
In the ON state of the ET, the line element becomes a part of the conductive portion (drain-source transmission line) of the FET and does not become a stub serving as a reflection source, so that good reflection characteristics can be realized in this state. In addition, since the susceptance can be loaded not only according to the length of the waveguide finger but also according to the length of the first and second adjacent gate electrode fingers, the size of the FET, the drain electrode finger and the source electrode finger can be reduced. Impedance can be set independently of shape, number, etc.
There is an advantage that circuit characteristics that meet the required performance can be realized.
In particular, by making the length of the second adjacent gate electrode finger very short, a very small susceptance can be loaded, which is effective for realizing a phase shifter with a small phase shift amount.

According to the second aspect of the present invention, the waveguide finger is divided into two in the length direction to have a stub shape.
Further, the length of the divided waveguide finger and the length of the divided gate electrode finger provided adjacent thereto are made substantially equal.
As a result, since an open-end stub can be realized, a relatively large capacitive susceptance can be easily realized.

According to the third aspect of the present invention, as compared with the first aspect of the present invention, a plurality of waveguide fingers are provided, and a plurality of waveguide fingers are provided adjacent to the respective waveguide fingers. The length of each of the gate electrode fingers is different from each other, and second,
A third gate bias terminal is provided. Thus, having a plurality of controllable waveguide fingers, FE
More impedance states can be realized without increasing the T size.

Further, according to the fourth aspect, the first to third aspects are provided.
Since the FET according to any one of the inventions is connected in series such that the drain electrode or the source electrode is electrically connected to each other, more controllable electrode fingers can be provided in a narrow area. , More impedance states are realized. Further, since periodic impedance discontinuity can be realized, frequency response characteristics according to the shape can be realized.

According to the fifth aspect of the present invention, the drain electrode and the source electrode are extended from one of the drain electrodes and the source electrode, and are connected to the other by means of an air bridge or the like so as to prevent competition or contact with the gate wiring. It has three waveguide fingers connected in a short-circuit, and a gate electrode finger is provided between the waveguide fingers. Further, the width of the other waveguide fingers is made wider than the width of the central waveguide finger. It is composed. In this configuration, since the conductor portion between the drain and the source is wide, the resistance therebetween is low. Therefore, an FET having a small passage loss is realized.

According to the sixth aspect of the present invention, the stub-shaped waveguide finger divided into two parts in the middle is formed wider than the other waveguide fingers. And a relatively large capacitive susceptance can be realized.

According to the seventh aspect of the present invention, the external electrode fingers of the same kind as the above-mentioned fingers are provided so as to be in parallel with the drain electrode fingers or the source electrode fingers arranged at the outermost positions. By providing an external gate electrode finger between the drain electrode finger or the source electrode finger and controlling a bias applied to the external gate electrode finger, a capacitive
An inductive susceptance can be loaded, and an inverted-L filter circuit whose transmission characteristics can be switched in the transmission path can be formed in competition with other parts of the FET.

According to the eighth invention, the plurality of field effect transistors according to any one of the first to seventh inventions are connected via a line having a length of 波長 wavelength at a substantially required frequency. Therefore, reflection in a state where susceptance or reactance is loaded can be canceled, and a semiconductor circuit having good reflection characteristics can be realized.

According to the ninth aspect, the gate electrode fingers of the plurality of FETs according to any one of the first to seventh aspects have a shape connected to each other. Therefore, the size of the semiconductor circuit can be further reduced.

According to the tenth aspect, the drain electrode or the source electrode of the FET according to any one of the first to seventh aspects is connected to each of the two output terminals to which the power of the hybrid coupler is distributed. As a result, the reflection on the input side can be reduced by using the power combining characteristics of the hybrid coupler. As a result, even when realizing multiple phase states, there is no influence between FETs and low reflection and small semiconductor circuit. Becomes possible.

According to the eleventh aspect of the present invention, the F-type transmission line according to any one of the first to seventh aspects is provided in the reference phase side transmission line and the delay phase side transmission line of the line switching type semiconductor phase shifter.
Since the ET is provided, the pattern occupation area of the line switching type semiconductor phase shifter is hardly increased.
It is possible to increase the number of bits of the phase shifter.

According to the twelfth aspect, since the two FETs according to the seventh aspect are used and the drain or source electrode fingers are connected to each other, the two FETs are combined. By forming a π-type low-pass or high-pass circuit to achieve impedance matching and realize a small filter, it is also possible to switch the pass amplitude characteristics and pass phase characteristics by switching the applied bias. Semiconductor circuit that can be implemented.

According to the thirteenth aspect, the first to the first aspects
Utilizing the fact that the loaded reactance or loaded susceptance can be switched stepwise within an arbitrary range by using the FET according to any one of the seventh aspect of the invention as a part of a matching circuit, an amplifier, a mixer, or a combination thereof is used. These semiconductor circuits can be provided with a function of adjusting and controlling the matching characteristics of various modules by electrical means.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a first embodiment of an FET according to the present invention.

FIG. 2 is an equivalent circuit diagram showing an operation of the FET according to the first embodiment.

FIG. 3 is a configuration diagram showing a second embodiment of the FET according to the present invention;

FIG. 4 is an equivalent circuit diagram showing an operation of the FET according to the second embodiment.

FIG. 5 is a configuration diagram showing a third embodiment of the FET according to the present invention.

FIG. 6 is an equivalent circuit diagram showing an operation of the FET according to the third embodiment.

FIG. 7 is a configuration diagram showing a fourth embodiment of an FET according to the present invention.

FIG. 8 is an equivalent circuit diagram showing an operation of the FET according to the fourth embodiment.

FIG. 9 is a configuration diagram showing a fifth embodiment of an FET according to the present invention.

FIG. 10 is a configuration diagram showing a sixth embodiment of the FET according to the present invention.

FIG. 11 is a configuration diagram showing a seventh embodiment of an FET according to the present invention.

FIG. 12 is a configuration diagram showing an eighth embodiment of an FET according to the present invention.

FIG. 13 is a configuration diagram showing a ninth embodiment of an FET according to the present invention.

FIG. 14 is a configuration diagram showing a tenth embodiment of an FET according to the present invention.

FIG. 15 is a configuration diagram showing an eleventh embodiment of an FET according to the present invention.

FIG. 16 is an equivalent circuit diagram showing an operation of the FET according to the eleventh embodiment.

FIG. 17 is a configuration diagram showing a twelfth embodiment of an FET according to the present invention.

FIG. 18 is an equivalent circuit diagram showing an operation of the FET according to the twelfth embodiment.

FIG. 19 is a first embodiment of a semiconductor circuit according to the present invention;
FIG.

FIG. 20 is a first embodiment of a semiconductor circuit according to the present invention;
FIG.

FIG. 21 is a first embodiment of a semiconductor circuit according to the present invention;
FIG.

FIG. 22 is a first embodiment of a semiconductor circuit according to the present invention;
FIG.

FIG. 23 is a first embodiment of a semiconductor circuit according to the present invention;
FIG.

FIG. 24 is an equivalent circuit diagram showing an operation of the semiconductor circuit according to the seventeenth embodiment.

FIG. 25 is a first embodiment of a semiconductor circuit according to the present invention;
FIG.

FIG. 26 is an equivalent circuit diagram showing an operation of the semiconductor circuit according to the eighteenth embodiment.

FIG. 27 is a first embodiment of a semiconductor circuit according to the present invention;
FIG.

FIG. 28 is a circuit diagram showing a configuration of a conventional semiconductor phase shifter according to a conventional example.

FIG. 29 is a configuration diagram of a conventional FET in a conventional example.

FIG. 30 is an equivalent circuit diagram showing the operation of a conventional FET.

[Explanation of symbols]

1 input line, 2 output line, 3, 4 conventional SPDT
Switch, 5 reference transmission line, 6 delay transmission line, 7
Inductor line for resonance, 8 Gate bias terminal, 9
Drain electrode finger, 10 Source electrode finger, 1
DESCRIPTION OF SYMBOLS 1 Gate electrode finger, 12 Gate connection wiring, 13
Air bridge, 14 equivalent resistance, 15 equivalent capacitance, 16
First waveguide finger, 17 First adjacent gate electrode finger, 18 Second adjacent gate electrode finger, 19 First
Gate bias terminal, 20 second gate bias terminal,
Reference Signs List 21 independent waveguide conductor, 22 open end stub, 23 first split waveguide finger, 24 second split waveguide finger, 25 third gate bias terminal, 26 fourth gate bias terminal, 27 second waveguide finger, 28 th 3 adjacent gate electrode fingers, 29 fourth adjacent gate electrode fingers, 30 third waveguide fingers, 31 fourth waveguide fingers, 32 fifth waveguide fingers, 33 fifth adjacent gate electrode fingers, 34 sixth waveguide fingers, 35
A seventh waveguide finger, 36 a third split waveguide finger,
37 fourth divided waveguide finger, 38 outermost source electrode finger, 39 external electrode finger, 40 external gate electrode finger, 41 equivalent inductor, 42 first line, 43 hybrid coupler, 44 output terminal of hybrid coupler, 45 via Hall, 46 amplified FE
T, 47 first matching line, 48 second matching line, 4
9 Matching stub, 50 input matching circuit.

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Hiroaki Nakahano 2-3-2 Marunouchi, Chiyoda-ku, Tokyo F-term (reference) 5F102 FA07 GA01 GA18 GB01 GC01 GD01 GS09 GV01

Claims (13)

[Claims] An end is connected to one of a drain electrode and a source electrode by bridging so as not to cause competition or contact with a gate wiring, and the other end is bridged similarly to the one end. Having a waveguide finger connected to the other electrode in a connected or extended structure; and
A gate electrode finger divided into two in the length direction is provided between the waveguide finger and the adjacent drain electrode finger or source electrode finger, and a bias is applied independently to the divided gate electrode finger. A field-effect transistor, comprising: 2. The waveguide finger is divided into two in the length direction to form a stub, and the length of the divided waveguide finger and the divided gate electrode provided adjacent thereto are set. 2. The method according to claim 1, wherein the length of the finger is substantially equal to the length of the finger.
The field-effect transistor according to claim. 3. The semiconductor device according to claim 1, further comprising a plurality of waveguide fingers, wherein the lengths of the divided gate electrode fingers provided adjacent to the respective waveguide fingers are different from each other. The field-effect transistor according to claim. 4. The field effect transistor according to claim 1, wherein a plurality of drain electrodes and source electrodes are electrically connected in cascade. 5. A semiconductor device comprising: three waveguide fingers extending from one of a drain electrode and a source electrode and connected to the other by a wiring method that does not cause competition or contact with a gate wiring; Between the waveguide fingers,
A field effect transistor comprising a gate electrode finger having a configuration capable of applying a bias from the outside, and further having a width of another waveguide finger wider than a width of a center waveguide finger. 6. A waveguide waveguide according to claim 5, wherein the center waveguide finger is divided into two to form a stub, and the width of said waveguide finger is wider than the width of other waveguide fingers. The field-effect transistor according to claim. 7. An electrode finger of the same kind as the finger is provided so as to be in parallel with the drain electrode finger or the source electrode finger disposed at the outermost position.
A field effect transistor, wherein a gate electrode finger is provided between the plurality of drain electrode fingers or source electrode fingers, and a bias is applied to the gate electrode finger. 8. A plurality of field-effect transistors having a configuration according to claim 1 connected via a line having a length of 波長 wavelength at a substantially required frequency. Semiconductor circuit. 9. A semiconductor circuit, wherein the gate electrode fingers of a plurality of field effect transistors having the configuration according to claim 1 are connected to each other. 10. A drain electrode or a source electrode of a field effect transistor having the configuration according to claim 1 connected to each of two output terminals of the hybrid coupler to which power is distributed. A semiconductor circuit, characterized in that: 11. A transmission line according to claim 1, wherein said line switching type semiconductor phase shifter has a reference phase side transmission line and a delay phase side transmission line.
A semiconductor circuit having a configuration provided with the field-effect transistor having the configuration described in any one of the above. 12. A semiconductor circuit comprising two field effect transistors according to claim 7, and connected so that adjacent drain electrodes or source electrodes are common. 13. A semiconductor circuit using the field effect transistor according to claim 1 in a matching circuit.