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JP2000032318A - Image input device - Google Patents

Image input device

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Publication number
JP2000032318A
JP2000032318A JP10208556A JP20855698A JP2000032318A JP 2000032318 A JP2000032318 A JP 2000032318A JP 10208556 A JP10208556 A JP 10208556A JP 20855698 A JP20855698 A JP 20855698A JP 2000032318 A JP2000032318 A JP 2000032318A
Authority
JP
Japan
Prior art keywords
scanning
video signal
thinning
pixel
scan
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10208556A
Other languages
Japanese (ja)
Other versions
JP4049896B2 (en
Inventor
Isao Takayanagi
功 高柳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Olympus Corp
Original Assignee
Olympus Optical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Olympus Optical Co Ltd filed Critical Olympus Optical Co Ltd
Priority to JP20855698A priority Critical patent/JP4049896B2/en
Publication of JP2000032318A publication Critical patent/JP2000032318A/en
Application granted granted Critical
Publication of JP4049896B2 publication Critical patent/JP4049896B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To provide an image input device capable of simultaneously providing entire image information based on thinning scanning and high-resolution partial image information based on full pixel scanning from the same frame. SOLUTION: This image input device is composed of a pixel array 1, vertical and horizontal scanning circuits 2 and 3 a timing pulse generating circuit 4 for driving and controlling the vertical and horizontal scanning circuits so as to scan only the prescribed area of the pixel array in a full pixel scanning mode and to scan remaining areas while thinning them, a first buffer memory 6 for storing a thinning scan video signal separately from thinning scan and full pixel scan mixed video signals read out of the pixel array, a second buffer memory 7 for storing a full pixel scan video signal separately from the thinning scan and full pixel scan mixed video signals, a video synchronizing signal generating circuit 8 for reading the stored thinned video signal synchronously with a video monitor 10, and a CPU 11 for performing focal point discriminating processing or the like while using the full pixel scan video signal.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】この発明は、画像入力装置に
関し、特に間引き走査可能な固体撮像素子を用いた画像
入力装置に関する。
[0001] 1. Field of the Invention [0002] The present invention relates to an image input apparatus, and more particularly to an image input apparatus using a solid-state image sensor capable of thinning-out scanning.

【0002】[0002]

【従来の技術】一般に、固体撮像素子を用いた撮像装置
において、撮影画像の高精細化を図るため固体撮像素子
の多画素化を進めて行くと、全画素を読み出すフレーム
レートが低下してしまう。そこで、画素を間引いて読み
出す間引き読み出しを行ってフレームレートを上げ、画
角合わせなどに用いるようにしており、一方、部分領域
の全画素読み出しを行って焦点調整などに用いるように
している。
2. Description of the Related Art Generally, in an image pickup apparatus using a solid-state image pickup device, when the number of pixels of the solid-state image pickup device is increased in order to increase the definition of a captured image, the frame rate for reading out all pixels is reduced. . Therefore, thinning-out reading is performed by thinning out pixels to increase the frame rate and use it for angle-of-view adjustment or the like. On the other hand, all pixels in a partial area are read out and used for focus adjustment or the like.

【0003】かかる間引き読み出しを行えるようにした
撮像素子を用いた撮像装置として、特開平9−2148
36号公報には、次のような構成のものが開示されてい
る。すなわち、図5に示すように、光電変換面に形成さ
れた全画素のうちの所定の画素のデータを読み出すこと
が可能な撮像素子104 と、該撮像素子104 における全画
素のうち、所定のブロック内の画素を走査するためのブ
ロック走査モードと、全画素について所定の間引き率で
特定の画素を間引いて走査するための間引き走査モード
とを切り換えて前記撮像素子104 を駆動制御することが
可能な駆動部103 と、前記撮像素子104 から間引き走査
モードで読み出されA/D変換部105 でA/D変換され
たデータをスイッチ106 を介して記憶する全体表示メモ
リ107 と、前記撮像素子104 からブロック走査モードで
読み出されA/D変換されたデータをスイッチ106 を介
して記憶する部分拡大表示メモリ108 と、前記2つのメ
モリ107 ,108 に記憶された各データを一つのモニタ11
0 上で別々の画像として表示可能なようにデータ変換し
て出力する表示出力部109 と、入力装置101 からの指示
を受けて各部の制御を行うコントローラ102 とを備え、
コントローラ102 が画角合わせやピント合わせ、すなわ
ち撮影者のモニタリングのための処理を行うように指示
を受けた場合、駆動部103 及びスイッチ106 を制御し
て、撮像素子104 から間引き走査による画像データとブ
ロック走査による画像データを交互に全体表示メモリ10
7 と部分拡大表示メモリ108 に送り出して記憶させ、該
2つのメモリ107 ,108 に記憶された画像データは、水
平1ライン分毎に交互に読み出されて表示出力部109 へ
送出され、標準テレビジョン信号に変換されて一つのモ
ニタ110 の表示画面上に表示されるようになっている。
なお、コントローラ102 が撮影のための処理を行うよう
に指示を受けた場合は、全画素走査で画像データが送り
出され、1画面の画像データがバッファメモリ111 を介
してハードディスク112 に記録保管されるようになって
いる。
An image pickup apparatus using an image pickup device capable of performing such thinning-out reading is disclosed in Japanese Patent Application Laid-Open No. 9-2148.
Japanese Patent Publication No. 36 discloses the following configuration. That is, as shown in FIG. 5, an image sensor 104 capable of reading data of a predetermined pixel among all pixels formed on the photoelectric conversion surface, and a predetermined block among all the pixels in the image sensor 104 It is possible to control the driving of the image sensor 104 by switching between a block scanning mode for scanning pixels within the pixel and a thinning scanning mode for thinning and scanning a specific pixel at a predetermined thinning rate for all pixels. A driving unit 103, an overall display memory 107 for storing data read from the image sensor 104 in the thinning-out scanning mode and A / D converted by the A / D converter 105 via a switch 106; A partially enlarged display memory 108 for storing the data read and A / D converted in the block scanning mode via a switch 106, and each data stored in the two memories 107, 108 One monitor 11
0, a display output unit 109 that converts and outputs data so that it can be displayed as separate images on the display unit, and a controller 102 that controls each unit in response to an instruction from the input device 101,
When the controller 102 is instructed to perform angle of view or focus adjustment, that is, a process for monitoring a photographer, the controller 102 controls the drive unit 103 and the switch 106 so that the image data obtained by the thinning scan from the image sensor 104 is output. Image data by block scanning alternately in the entire display memory 10
7 and the partial enlarged display memory 108 for storage, and the image data stored in the two memories 107, 108 are alternately read out for each horizontal line and sent to the display output unit 109, and are output to the standard television. The signal is converted into a version signal and displayed on the display screen of one monitor 110.
When the controller 102 is instructed to perform processing for photographing, image data is sent out by scanning all pixels, and image data of one screen is recorded and stored on the hard disk 112 via the buffer memory 111. It has become.

【0004】[0004]

【発明が解決しようとする課題】ところで、上記公報開
示の撮像装置においては、画角合わせなどのための間引
き走査による全体画像とピント合わせなどのためのブロ
ック走査による部分精細画像を得る場合に、間引き走査
モードとブロック走査モードを混在させたモードで駆動
走査するものではないので、同一フレームから間引き走
査による全体画像情報とピント合わせ用の高解像情報を
得ることはできない。そのため、従来の上記公報開示の
撮像装置ではピント合わせの処理中は、画角合わせ用の
ビデオ出力が行えないという問題がある。これを改善す
るため、画角合わせ用の間引き画像入力とピント合わせ
用の高精細画像入力とを、フレーム毎交互に読み出すよ
うに構成した場合においても、ピント合わせ用のビデオ
出力の実効的なフレームレートが低下するという問題が
あった。
In the imaging apparatus disclosed in the above publication, when obtaining an entire image by thinning-out scanning for adjusting the angle of view or the like and a partially fine image by block scanning for focusing or the like, Since drive scanning is not performed in a mode in which the thinning scanning mode and the block scanning mode are mixed, it is impossible to obtain the entire image information and the high-resolution information for focusing from the same frame by the thinning scanning. Therefore, the conventional imaging apparatus disclosed in the above-mentioned publication has a problem in that it is not possible to output video for angle-of-view adjustment during focusing processing. In order to improve this, even when the thinned-out image input for angle-of-view adjustment and the high-definition image input for focusing are alternately read out for each frame, the effective frame of the video output for focusing is effective. There was a problem that the rate dropped.

【0005】本発明は、従来の撮像装置における上記問
題点を解消するためになされたもので、同一フレームか
ら間引き走査による全体画像情報と全画素走査による高
解像部分画像情報が得られるようにした画像入力装置を
提供することを目的とする。
SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems in the conventional imaging apparatus, and is intended to obtain the whole image information by thinning-out scanning and the high-resolution partial image information by all-pixel scanning from the same frame. It is an object of the present invention to provide an image input device having the above configuration.

【0006】[0006]

【課題を解決するための手段】上記問題点を解決するた
め、請求項1に係る発明は、複数の画素を2次元状に配
列してなる画素アレイを有し、該画素アレイの画素を間
引いて走査する間引き走査を含む複数の走査モードで走
査できるようにした固体撮像素子を備えた画像入力装置
において、前記固体撮像素子の画素アレイの連続する所
定領域の画素群のみを全画素走査すると共に、画素アレ
イの残りの領域の画素群については間引き走査を行う走
査制御手段と、前記全画素走査領域からの映像信号と間
引き走査領域からの映像信号とを互いに分離する映像信
号分離手段とを備え、前記全画素走査領域からの映像信
号を露出制御又は焦点検出に用いることを特徴とするも
のである。
According to a first aspect of the present invention, there is provided a pixel array having a plurality of pixels arranged two-dimensionally, and the pixels of the pixel array are thinned out. In an image input apparatus provided with a solid-state imaging device capable of performing scanning in a plurality of scanning modes including thinning scanning, scanning is performed on all pixels of only a pixel group in a continuous predetermined region of a pixel array of the solid-state imaging device. A scan control unit that performs a thinning scan for a pixel group in a remaining area of the pixel array, and a video signal separating unit that separates a video signal from the all pixel scan region and a video signal from the thinned scan region from each other. The video signal from the pixel scanning area is used for exposure control or focus detection.

【0007】このような走査制御手段と映像信号分離手
段を設けることにより、画素アレイの特定領域の画素群
については全画素走査が行われ、その他の領域の画素群
については間引き走査が行われるので、間引き走査によ
る映像信号と全画素走査による映像信号とが混在した信
号が得られ、これらの混在した信号は映像信号分離手段
で分離され、同一フレームから間引き走査による全体画
像情報と全画素走査による高解像部分画像情報が得られ
る。
By providing such scanning control means and video signal separating means, all pixel scanning is performed for a pixel group in a specific area of a pixel array, and thinning scanning is performed for a pixel group in another area. A mixed signal of a video signal obtained by thinning scanning and a video signal obtained by scanning all pixels is obtained. These mixed signals are separated by a video signal separating unit, and the whole image information obtained by the thinning scanning and the whole image obtained by scanning all pixels are extracted from the same frame. High resolution partial image information is obtained.

【0008】[0008]

【発明の実施の形態】次に、実施の形態について説明す
る。図1は、本発明に係る画像入力装置の実施の形態を
示すブロック構成図である。図1において、1は光電変
換素子からなる複数の画素を2次元的にm×n配列して
なる画素アレイ、2,3は画素アレイ1を走査して画素
信号を読み出すための垂直走査回路及び水平走査回路で
あり、間引き動作を含む複数の動作モードを有してい
る。4は垂直走査回路2及び水平走査回路3を駆動制御
するためのタイミングパルスを発生するためのタイミン
グパルス発生回路で、これらの構成部材で固体撮像素子
を構成している。5は垂直走査回路2及び水平走査回路
3の走査により読み出された映像信号を増幅すると共に
A/D変換するA/D変換部、6,7はそれぞれ前記タ
イミングパルス発生回路4からの制御信号を受けてA/
D変換されたデジタル映像信号から間引き画像信号を記
憶する第1のバッファメモリ及び自動ピント合わせに必
要な画像のみを記憶する第2のバッファメモリ、8は第
1のバッファメモリ6に記憶された間引き信号をビデオ
モニタ10と同期し読み出すためのビデオ同期信号発生回
路、9は第1のバッファメモリ6に記憶されたデジタル
信号をアナログ信号に変換するためのD/A変換部、11
は自動ピント合わせ処理を行うCPUである。
Next, an embodiment will be described. FIG. 1 is a block diagram showing an embodiment of the image input apparatus according to the present invention. In FIG. 1, reference numeral 1 denotes a pixel array in which a plurality of pixels each formed of a photoelectric conversion element are arranged two-dimensionally in an m × n arrangement; 2, 3 a vertical scanning circuit for scanning the pixel array 1 to read out pixel signals; The horizontal scanning circuit has a plurality of operation modes including a thinning operation. Reference numeral 4 denotes a timing pulse generation circuit for generating a timing pulse for controlling the driving of the vertical scanning circuit 2 and the horizontal scanning circuit 3, and these components constitute a solid-state imaging device. Reference numeral 5 denotes an A / D converter for amplifying and A / D converting the video signal read by the scanning of the vertical scanning circuit 2 and the horizontal scanning circuit 3, and 6, 7 control signals from the timing pulse generation circuit 4, respectively. A /
A first buffer memory for storing a decimated image signal from the D-converted digital video signal and a second buffer memory for storing only an image necessary for automatic focusing, 8 is a decimated memory stored in a first buffer memory 6 A video synchronizing signal generating circuit 9 for synchronizing and reading the signal with the video monitor 10; 9 a D / A converter for converting a digital signal stored in the first buffer memory 6 into an analog signal;
Is a CPU for performing automatic focusing processing.

【0009】間引き走査が可能な走査回路の構成例とし
ては、例えば図2に示すように、D形フリップフロップ
回路(DFF)で構成したシフトレジスタにおいて、D
FFの出力信号を次段のDFFに信号を転送するスイッ
チ21と、該スイッチ21とは制御の論理を逆転させると共
に一段飛ばして次次段のDFFに信号を転送するスイッ
チ22とを各DFF間に設け、これらスイッチ21と22との
制御端子に、タイミング発生回路4からのスキップイネ
ーブル(Skip Enable)信号を入力することで実現でき
る。
As a configuration example of a scanning circuit capable of thinning-out scanning, for example, as shown in FIG. 2, in a shift register composed of a D-type flip-flop circuit (DFF),
A switch 21 for transferring the output signal of the FF to the next-stage DFF, and a switch 22 for inverting the control logic of the switch 21 and transferring the signal to the next-stage DFF by skipping one stage between each DFF. And a skip enable signal from the timing generation circuit 4 is input to the control terminals of the switches 21 and 22.

【0010】図3は図2に示した間引き走査が可能な走
査回路の動作タイミングを示す図であり、CKは走査の
基本クロック、φINは走査の入力信号、φ1〜φ12は
それぞれ走査回路の各段の出力タイミングを示してい
る。Skip Enable がLのとき隣接するDFF間の接続ス
イッチ21がオンし、走査信号はCKの周期に対して一段
づつシフトする。Skip Enable がHとなると、スイッチ
21がオフする一方でスイッチ22がオンし、走査信号は次
次段のDFFに転送され、これが繰り返されることで一
段置きにスキップしながら移動する。したがって、この
ような走査回路を垂直走査回路2及び水平走査回路3に
採用することで、間引き走査が可能な撮像装置の構成が
可能となる。図2に示した走査回路の回路構成は、一画
素飛ばしの間引き走査が可能なものであるが、飛び越し
用のスイッチ22の接続先を変えることで、間引き画素数
は簡単に変更できる。
FIG. 3 is a diagram showing the operation timing of the scanning circuit capable of thinning-out scanning shown in FIG. 2, in which CK is a basic scanning clock, φIN is a scanning input signal, and φ1 to φ12 are scanning circuits. The output timing of the stage is shown. When Skip Enable is L, the connection switch 21 between the adjacent DFFs is turned on, and the scanning signal shifts by one step with respect to the period of CK. When Skip Enable becomes H, switch
While the switch 21 is turned on while the switch 21 is turned off, the scanning signal is transferred to the DFF of the next next stage, and by repeating this, the scanning signal moves while skipping every other stage. Therefore, by adopting such a scanning circuit for the vertical scanning circuit 2 and the horizontal scanning circuit 3, a configuration of an imaging device capable of thinning-out scanning becomes possible. Although the circuit configuration of the scanning circuit shown in FIG. 2 is capable of skipping scanning by skipping one pixel, the number of skipping pixels can be easily changed by changing the connection destination of the jumping switch 22.

【0011】次に、このように構成されている画像入力
装置の動作について、図4のパルスタイミング図を用い
て説明する。説明を簡単にするため、画素アレイ1の第
L行から第M行の間を全画素読み出し、それ以外の領域
では行及び列とも一画素おきに画素を間引いて読み出す
場合を例にとって説明する。図4の動作を説明するため
のパルスタイミング図における各パルス名は、図1に示
したパルス名と一致させている。φXi(φX1 〜φXm)
は行選択パルスを表し、φXi がHのとき画素アレイ1
の第i行の画素のみが選択されることを示す。またSkip
Enable は垂直走査回路2及び水平走査回路3の間引き
走査を制御するパルスであり、Skip Enable にHが出力
されると、垂直走査回路2及び水平走査回路3とも一画
素おきに間引き走査し、Skip Enable がLのときは連続
して画素を走査する。Memory1 Write及びMemory2 Wri
teは、それぞれ間引き画像用の第1のバッファメモリ6
とピント合わせ画像用の第2のバッファメモリ7とに信
号を入力(Write)するタイミングを制御するパルスであ
る。列選択パルスφYj は、行選択パルスφXi がHと
なる期間中に列を走査するが、煩雑化するのを避けるた
め図4では表示を省略している。
Next, the operation of the thus configured image input apparatus will be described with reference to the pulse timing chart of FIG. For simplicity of description, a case will be described as an example in which all pixels are read from the Lth row to the Mth row of the pixel array 1 and pixels are read out every other pixel in every other row and column in other areas. Each pulse name in the pulse timing chart for explaining the operation of FIG. 4 is made to match the pulse name shown in FIG. φXi (φX1 to φXm)
Represents a row selection pulse, and when φXi is H, the pixel array 1
Indicates that only the pixel in the i-th row is selected. Also Skip
Enable is a pulse for controlling thinning-out scanning of the vertical scanning circuit 2 and the horizontal scanning circuit 3. When H is output to Skip Enable, both the vertical scanning circuit 2 and the horizontal scanning circuit 3 perform thinning-out scanning at every other pixel, and skip. When Enable is L, pixels are continuously scanned. Memory1 Write and Memory2 Wri
te is a first buffer memory 6 for each thinned image.
And a pulse for controlling the timing of inputting (writing) a signal to the second buffer memory 7 for focusing images. The column selection pulse φYj scans the column during the period when the row selection pulse φXi is at H, but is not shown in FIG. 4 to avoid complication.

【0012】次に、動作の詳細を図4に示すタイミング
に添って説明する。時刻t0 〜t3間からなる1フレー
ム期間において、第1行から第L−1行の画素を走査す
る期間である時刻t0 〜t1 の間、Skip Enable にはH
が出力され、垂直走査回路2及び水平走査回路3とも間
引き走査が行われ、行及び列とも1画素おきに間引きな
がら読み出されると共に、この期間はMemory1 Writeの
みがHとなり、A/D変換部5から出力されるデジタル
映像信号は、間引き画像用の第1のバッファメモリ6に
のみ書き込まれる。
Next, the details of the operation will be described with reference to the timing shown in FIG. In one frame period from time t 0 to t 3 , Skip Enable is set to H during time t 0 to t 1 , which is a period for scanning the pixels from the first row to the L-1st row.
Is output, thinning-out scanning is performed on both the vertical scanning circuit 2 and the horizontal scanning circuit 3, and both rows and columns are read out while thinning every other pixel. During this period, only Memory1 Write becomes H, and the A / D converter 5 Is written only in the first buffer memory 6 for the thinned image.

【0013】次に、第L行から第M行までを走査する期
間である時刻t1 〜t2 間は、SkipEnable にはLが出
力され、垂直走査回路2及び水平走査回路3とも全画素
を走査する。この期間はMemory2 WriteにHが出力さ
れ、ピント合わせ画像用の第2のバッファメモリ7に映
像信号が書き込まれる。一方、間引き走査に対応する位
置の画素の信号がA/D変換部5から出力されるタイミ
ングに同期してMemory1WriteがHとなり、間引き画像
用の第1のバッファメモリ6には、間引き走査に対応す
る位置の画素の信号のみが書き込まれる。
Next, during a period from time t 1 to time t 2, which is a period for scanning from the L-th row to the M-th row, L is output to SkipEnable, and both the vertical scanning circuit 2 and the horizontal scanning circuit 3 use all pixels. Scan. During this period, H is output to Memory2 Write, and the video signal is written to the second buffer memory 7 for the focused image. On the other hand, Memory1Write becomes H in synchronization with the timing at which the signal of the pixel at the position corresponding to the thinning scan is output from the A / D conversion unit 5, and the first buffer memory 6 for the thinned image is compatible with the thinning scan. Only the signal of the pixel at the corresponding position is written.

【0014】時刻t2 〜t3 間は再びSkip Enable がH
となり、第M+1行から第m行までを行及び列とも間引
き走査すると共に、Memory1 WriteがHとなることで、
A/D変換部5から出力されるデジタル映像信号は間引
き画像用の第1のバッファメモリ6にのみ書き込まれ
る。
Between times t 2 and t 3, Skip Enable is set to H again.
By performing thinning-out scanning on both the row and the column from the (M + 1) th row to the (m) th row and setting Memory1 Write to H,
The digital video signal output from the A / D converter 5 is written only in the first buffer memory 6 for the thinned image.

【0015】このように1フレームを走査することによ
り、間引き画像用の第1のバッファメモリ6には全画像
領域の間引き信号が、ピント合わせ画像用の第2のバッ
ファメモリ7には全画素を走査した領域の画像が記憶さ
れる。第2のバッファメモリ7に記録されたピント合わ
せ用の映像情報は、ピント合わせ処理(AF制御)を行
うCPU11に転送され、ピント状態が判定されると共に
光学系へフィードバックされる。
By scanning one frame in this manner, the thinning signal of the entire image area is stored in the first buffer memory 6 for the thinned image, and all the pixels are stored in the second buffer memory 7 for the focused image. An image of the scanned area is stored. The video information for focusing recorded in the second buffer memory 7 is transferred to the CPU 11 for performing the focusing process (AF control), and the focus state is determined and fed back to the optical system.

【0016】一方、第1のバッファメモリ6に記録され
た間引き映像信号は、ビデオ同期信号発生回路8から入
力されるビデオ同期信号に合わせて読み出され、D/A
変換部9でアナログ変換された後、ビデオモニタ10に動
画として表示される。この際、ビデオ出力のフレームレ
ートと撮像素子からの読み出しのフレームレートとは一
致させる必要があるのに対して、撮像素子からの読み出
す画素数の方がビデオ出力の画素数よりも多いため、同
一のデータレートで駆動すると撮像素子からの読み出し
期間が長くなってしまうという問題がある。この時間差
がビデオ規格の垂直帰線期間内で吸収できれば支障がな
いが、それを越える場合には両者のデータレートに若干
の差を持たせることで解決できる。
On the other hand, the thinned-out video signal recorded in the first buffer memory 6 is read out in accordance with the video synchronization signal input from the video synchronization signal generation circuit 8, and the D / A
After the analog conversion by the conversion unit 9, the image is displayed as a moving image on the video monitor 10. At this time, the frame rate of the video output and the frame rate of the reading from the image sensor need to be matched, but the number of pixels read from the image sensor is larger than the number of pixels of the video output. There is a problem that the driving period at the data rate described above increases the readout period from the image sensor. If this time difference can be absorbed within the vertical retrace period of the video standard, there is no problem. However, if the time difference is exceeded, it can be solved by providing a slight difference between the two data rates.

【0017】このように画素アレイの一部のみ全画素走
査し、それ以外の領域は間引き走査すると共に、出力さ
れる映像信号を複数のバッファメモリを介して間引き画
像と全画素走査した領域の画像とに分離し、間引き画像
をビデオ同期信号に合わせて出力し、全画素走査した領
域の画像をピント合わせ処理に利用することで、画像入
力装置を高精細化した場合においてもフレームレートを
落とさずに、画角合わせとピント合わせ用の情報を同時
に得ることができる。
As described above, only a part of the pixel array is scanned with all pixels, and other areas are scanned with thinning, and the output video signal is subjected to a thinned image and an image of the area obtained by scanning all pixels through a plurality of buffer memories. The thinned image is output in accordance with the video synchronization signal, and the image of the area scanned by all pixels is used for focusing processing, so that the frame rate does not decrease even if the image input device is made high definition. In addition, information for angle of view alignment and information for focusing can be obtained at the same time.

【0018】本実施の形態では、全画素読み出す領域を
第L行から第M行の全画素として説明したが、Skip Ena
ble のタイミングを変更することで、列方向にも全画素
読み出す領域を任意に設定できる。また、間引きに関し
ても一画素飛ばしに限定するものではなく、走査回路の
簡単な変更により3画素、4画素飛ばしといった間引き
走査にも対応できる。更に補足すると、本実施の形態で
は画像の一部領域を全画素読み出した映像情報をピント
合わせに用いる場合について説明したが、CPUの処理
内容に追加することで局所露光時間制御や局所ホワイト
バランス処理などにも有効に利用できる。
In this embodiment, all pixels are read out from all the pixels in the L-th to M-th rows.
By changing the timing of ble, it is possible to arbitrarily set the area for reading out all pixels in the column direction. Further, the thinning-out is not limited to skipping by one pixel, and can be adapted to skipping by 3 pixels or 4 pixels by simply changing the scanning circuit. In addition, in this embodiment, a case has been described in which video information obtained by reading all pixels of a partial area of an image is used for focusing. However, local exposure time control and local white balance processing can be performed by adding the information to the processing contents of the CPU. It can also be used effectively.

【0019】[0019]

【発明の効果】以上、実施の形態に基づいて説明したよ
うに、本発明によれば、固体撮像素子の画素アレイの連
続する所定領域の画素群のみを全画素走査すると共に、
画素アレイの残りの領域の画素群については間引き走査
を行う走査制御手段と、全画素走査領域からの映像信号
と間引き走査領域からの映像信号とを互いに分離する映
像信号分離手段とを備えているので、画素アレイの特定
領域の画素群については全画素走査が行われ、その他の
領域の画素群については間引き走査が行われて、間引き
走査による映像信号と全画素走査による映像信号とが混
在した信号が得られ、これらの混在した信号は映像信号
分離手段で分離され、同一フレームから間引き走査によ
る全体画像情報と全画素走査による高解像部分画像情報
とを同時に得ることができる。
As described above, according to the present invention, according to the present invention, all pixels are scanned only in a pixel group in a predetermined continuous area of a pixel array of a solid-state imaging device.
Scanning control means for performing thinning scanning for the pixel group in the remaining area of the pixel array, and video signal separating means for separating video signals from all pixel scanning areas and video signals from the thinning scanning area from each other. Therefore, all pixel scanning is performed for a pixel group in a specific area of the pixel array, and thinning scanning is performed for pixel groups in other areas, and a video signal by thinning scanning and a video signal by all pixel scanning are mixed. Signals are obtained, and these mixed signals are separated by the video signal separating means, so that the whole image information by thinning scanning and the high-resolution partial image information by all pixel scanning can be simultaneously obtained from the same frame.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明に係る画像入力装置の実施の形態を示す
概略ブロック構成図である。
FIG. 1 is a schematic block diagram showing an embodiment of an image input device according to the present invention.

【図2】図1に示した実施の形態における間引き走査が
可能な走査回路の構成例を示すブロック構成図である。
FIG. 2 is a block diagram showing a configuration example of a scanning circuit capable of thinning scanning in the embodiment shown in FIG. 1;

【図3】図2に示した間引き走査が可能な走査回路の動
作を説明するためのタイミング図である。
FIG. 3 is a timing chart for explaining the operation of the scanning circuit capable of thinning-out scanning shown in FIG. 2;

【図4】図1に示した実施の形態の動作を説明するため
のタイミング図である。
FIG. 4 is a timing chart for explaining the operation of the embodiment shown in FIG. 1;

【図5】従来の画像入力装置の構成例を示すブロック構
成図である。
FIG. 5 is a block diagram showing a configuration example of a conventional image input device.

【符号の説明】[Explanation of symbols]

1 画素アレイ 2 垂直走査回路 3 水平走査回路 4 タイミングパルス発生回路 5 A/D変換部 6 第1のバッファメモリ 7 第2のバッファメモリ 8 ビデオ同期信号発生回路 9 D/A変換部 10 ビデオモニタ 11 CPU 21,22 スイッチ Reference Signs List 1 pixel array 2 vertical scanning circuit 3 horizontal scanning circuit 4 timing pulse generation circuit 5 A / D conversion unit 6 first buffer memory 7 second buffer memory 8 video synchronization signal generation circuit 9 D / A conversion unit 10 video monitor 11 CPU 21, 22 switch

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 複数の画素を2次元状に配列してなる画
素アレイを有し、該画素アレイの画素を間引いて走査す
る間引き走査を含む複数の走査モードで走査できるよう
にした固体撮像素子を備えた画像入力装置において、前
記固体撮像素子の画素アレイの連続する所定領域の画素
群のみを全画素走査すると共に、画素アレイの残りの領
域の画素群については間引き走査を行う走査制御手段
と、前記全画素走査領域からの映像信号と間引き走査領
域からの映像信号とを互いに分離する映像信号分離手段
とを備え、前記全画素走査領域からの映像信号を露出制
御又は焦点検出に用いることを特徴とする画像入力装
置。
1. A solid-state imaging device having a pixel array in which a plurality of pixels are arranged two-dimensionally, and capable of scanning in a plurality of scanning modes including a thinning scan for thinning out and scanning the pixels of the pixel array. A scanning control unit that performs all-pixel scanning only on a pixel group in a continuous predetermined area of the pixel array of the solid-state imaging device, and performs thinning scanning on a pixel group in the remaining area of the pixel array. Video signal separating means for separating a video signal from the all-pixel scanning area and a video signal from the thinning-out scanning area from each other, and using the video signal from the all-pixel scanning area for exposure control or focus detection. Characteristic image input device.
【請求項2】 前記走査制御手段の走査制御により画素
アレイから出力された映像信号を記憶する複数のフレー
ムバッファメモリと、該複数のフレームバッファメモリ
にそれぞれ全画素走査領域に対応する全画素走査映像信
号と間引き走査領域に対応する間引き走査映像信号とを
分離し記憶するメモリ制御手段と、前記全画素走査映像
信号を間引き処理し前記間引き走査映像信号と合成して
画素アレイ全領域の合成間引き走査映像信号を形成する
間引き走査映像信号合成手段とを備え、該間引き走査映
像信号合成手段から出力される合成間引き走査映像信号
をビデオ信号として出力するように構成したことを特徴
とする請求項1に係る画像入力装置。
2. A plurality of frame buffer memories for storing video signals output from a pixel array under scanning control of the scanning control means, and all-pixel scanning images respectively corresponding to all-pixel scanning areas in the plurality of frame buffer memories. Memory control means for separating and storing a signal and a thinned-scanning video signal corresponding to the thinned-scanning area; 2. A thinning-out scanning video signal synthesizing means for forming a video signal, wherein the synthesized thinning-out scanning video signal output from the thinning-out scanning video signal synthesizing means is output as a video signal. Such an image input device.
【請求項3】 前記固体撮像素子はタイミング発生回路
を備え、該タイミング発生回路は、前記メモリ制御手段
における映像信号分離動作のためのタイミングパルス及
び前記間引き走査映像信号合成手段における映像信号合
成動作のためのタイミングパルスを供給するように構成
されていることを特徴とする請求項2に係る画像入力装
置。
3. The solid-state imaging device includes a timing generation circuit, the timing generation circuit comprising a timing pulse for a video signal separation operation in the memory control means and a video signal synthesis operation in the thinned-scanning video signal synthesis means. 3. An image input device according to claim 2, wherein the image input device is configured to supply a timing pulse for the operation.
JP20855698A 1998-07-09 1998-07-09 Image input device Expired - Fee Related JP4049896B2 (en)

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