JP2000012784A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device equipped with a satisfactory and thin capacitor insulating film. SOLUTION: A P--type well region 2 is formed inside an N-type semiconductor substrate 1 on the main surface side, a high-concentration P-type diffused region 3 is formed inside the P--type well region 2 on the main surface side, and a P+-type high concentration region 4 is formed apart from the P-type diffused region 3 which surrounds the periphery of the P--type well region 2 in a plan view. A low resistance polysilicon film 6 is formed on the P-type diffused region 3 through the intermediary of a thin capacitor insulating film 5 of thermal oxide film. The capacitor insulating film 5 is formed at the same time, when the gate oxide film of a CMOS is formed on the same N-type semiconductor substrate 1. A second wiring 11 of aluminum is connected electrically to the P+-type high concentration region 4. A first wiring 10 of aluminum is formed on the polysilicon film 6 through the intermediary of an interlayer insulating film 7. A region 6a, where a contact 18 of the first wiring 10 is prohibited from forming, is provided to the main surface of the polysilicon film 6.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device, and more particularly to a capacitor (capacitor) formed on a semiconductor substrate.

[0002]

2. Description of the Related Art Conventionally, a semiconductor device having the structure shown in FIG. 7 has been known as this type of semiconductor device. The semiconductor device shown in FIG. 7, p on the main surface of the n-type semiconductor substrate 1 made of n-type silicon substrate ^- form the well region 2 is formed, p ^- p on the main surface of the form well region 2 ^- form than the well region 2 is high-concentration p-type diffusion region 3 is formed, apart from the p-type diffusion region on the main surface of the n-type semiconductor substrate 1 p ^- forms well region 2
The p ^{+ -type} high-concentration region 4 surrounding the outer peripheral portion in the planar shape of the p ⁻ -type well region 2 is formed. In addition,
The p ^{+ -type} high concentration region 4 is formed at a higher concentration than the p-type diffusion region 3. A low-resistance polysilicon film 6 is formed on the p-type diffusion region 3 via a thin capacitive insulating film 5 made of a thermal oxide film, and a first wiring 10 made of, for example, aluminum is formed on the polysilicon film 6. It is electrically connected. The capacitor insulating film 5 is formed simultaneously with a CMOS gate oxide film (thermal oxide film) (not shown) formed on the same n-type semiconductor substrate 1. That is, the capacitance insulating film 5 is formed to be as thin as the gate oxide film. Further, a second wiring 11 made of, for example, aluminum is electrically connected to the p ^{+ -type} high-concentration region 4. Here, the first wiring 10 is electrically connected to the polysilicon film 6 through a contact hole 8 formed in the interlayer insulating film 7, and the second wiring 11 is p ⁺ through a contact hole 9 formed in the interlayer insulating film 7. It is electrically connected to the high-concentration region 4. Note that a protective film 12 made of an insulating oxide film is formed on each of the wirings 10 and 11 and on the interlayer insulating film 7.

The first wiring 10 is formed so as to cover the main surface of the polysilicon film 6 except for the outer peripheral portion of the main surface of the polysilicon film 6. The contact portion 18 using the contact hole 8 for electrically connecting the polysilicon film 6 and the first wiring 10 has a plane size sufficiently smaller than the plane size of the polysilicon film 6, and As shown in FIG. 7A, a large number (81 locations in the illustrated example) covers almost the entire main surface of the silicon film 6.
Is formed. Note that a contact hole 9 for electrically connecting the p ^{+ -type} high-concentration region 4 and the second wiring 11 is formed.
A large number of contact portions 19 are formed.

In the semiconductor device having the structure shown in FIG. 7, the first wiring 10 and the polysilicon film 6 are located between the first wiring 10 and the second wiring 11 as shown in FIG. Contact resistance R _C1 of the polysilicon film 6 and resistance R _{PS of the} polysilicon film 6;
The capacitor C formed by the capacitive insulating film 5, the resistance _{RD of the} diffusion layer including the p-type diffusion region 3, the p ⁻ -type well region 2 and the p ^{+ -type} high-concentration region 4, the second wiring 11 and the p ^{+ -type} A series circuit with the contact resistance _RC2 and the concentration region 4 is formed.

Hereinafter, a method of manufacturing the semiconductor device shown in FIG. 7 will be described with reference to FIG.

First, a field oxide film 21 is formed on the main surface of an n-type semiconductor substrate 1 (see FIG. 9A).

[0007] Next, a first photoresist layer (not shown) is formed by coating on the field oxide film 21, p ^- first photoresist openings for forming the shape-well region 2 by photolithography Then, the field oxide film 21 is etched using hydrofluoric acid or the like using the first photoresist layer as a mask, thereby forming n
The main surface of the semiconductor substrate 1 is exposed. Thereafter, the first photoresist layer is removed to form a thin oxide film 22 for ion implantation protection on the n-type semiconductor substrate 1, and a p-type impurity such as boron is removed from the thin oxide film 22 using the field oxide film 21 as a mask. Implanted into the n-type semiconductor substrate 1 through
Oxidation drive (perform drive-in)
^The- well region 2 is formed (see FIG. 9B).

Next, after removing the field oxide film 21 and the oxide film 22 with hydrofluoric acid or the like, the pad oxide film 2 is removed.
3, a silicon nitride film 24 is deposited on the pad oxide film 23 by a low pressure CVD method or the like, and a second photoresist layer (not shown) is formed on the silicon nitride film 24 by coating. LOC leaving 24 partially
An opening for performing an OS is provided in the second photoresist layer by a photolithography technique, an unnecessary portion of the silicon nitride film 24 is etched using the second photoresist layer as a mask, and then the second photoresist layer is removed. Remove. Thereafter, a so-called LOCOS oxide film 13 is formed on a portion of the n-type semiconductor substrate 1 which is not covered with the silicon nitride film 24 (see FIG. 9C).

Next, the silicon nitride film 24 is removed using phosphoric acid or the like. Subsequently, a third photoresist layer (not shown) is formed on the main surface side of the n-type semiconductor substrate 1 by coating.
An opening for forming the p-type diffusion region 3 is provided in the third photoresist layer by a photolithography technique, and a p-type impurity such as boron is ion-implanted through the pad oxide film 23 using the third photoresist layer as a mask. A diffusion region 3 is formed. Next, the exposed pad oxide film 23, that is, the pad oxide film 23 on the p-type diffusion region 3 is removed,
Subsequently, after removing the third photoresist layer, a capacitive insulating film 5 made of a thermal oxide film is formed on an exposed portion of the main surface of the n-type semiconductor substrate 1. That is, the capacitance insulating film 5 is formed on the main surface of the p-type diffusion region 3. Here, the capacitor insulating film 5 is a CMOS formed on the same n-type semiconductor substrate 1.
Is formed simultaneously with a gate oxide film made of a thermal oxide film. That is, the capacitor insulating film 5 is formed of the same thickness as the gate oxide film, and is a high-quality thin oxide film having a low trap density at the interface. After the capacitance insulating film 5 is formed, a polysilicon film 6 is deposited on the main surface side of the n-type semiconductor substrate 1 by a low pressure CVD method or the like. The resistance of the polysilicon film 6 is reduced by injecting a fourth photoresist layer (not shown) onto the polysilicon film 6, and an opening for patterning the polysilicon film 6 is formed by photolithography. The fourth photoresist layer is provided by a lithography technique, and the polysilicon film 6 is etched by a dry etching technique using the fourth photoresist layer as a mask. After that, the fourth photoresist layer is removed, and subsequently, a fifth photoresist layer (not shown) is applied and formed on the main surface side of the n-type semiconductor substrate 1 to form the p ^{+ -type} high concentration region 4. Is formed in the fifth photoresist layer by a photolithography technique, and a p-type impurity such as boron is implanted with an ion implantation device or the like using the fifth photoresist layer as a mask. In this ion implantation step, the PM formed on the same n-type semiconductor substrate 1 is
It also serves as an ion implantation step for forming a source region and a drain region of the OS. After performing the ion implantation, the fifth photoresist layer is removed, and the previously implanted p
Drive process for diffusing the GaN-type impurities (FIG. 9)
(D)).

Next, an interlayer insulating film 7 is formed on the main surface side of the n-type semiconductor substrate 1 by a normal pressure CVD method or the like, a sixth photoresist layer (not shown) is applied and formed, and then a contact hole is formed. Openings for forming 8 and 9 are provided in the sixth photoresist layer by a photolithography technique, and the interlayer insulating film 7 is etched using hydrofluoric acid or the like using the sixth photoresist layer as a mask to form contact holes. 8 and 9 are formed. Thereafter, an aluminum film is deposited on the interlayer insulating film 7 and in the contact holes 8 and 9 so that the contact holes 8 and 9 are buried by sputtering or the like, and then a seventh photoresist layer (not shown) is applied. An opening for patterning the aluminum film is formed in the seventh photoresist layer by a photolithography technique, and an unnecessary portion of the aluminum film is removed (processed) by dry etching using the seventh photoresist layer as a mask. Thus, a first wiring 10 and a second wiring 11 are formed. Thereafter, the seventh photoresist layer is removed, and then the atmospheric pressure C
A protective film 12 is formed on the main surface side of the n-type semiconductor substrate 1 by a VD method or the like (see FIG. 9E). Finally, the protective film 12 in the electrode section is etched.

[0011]

In the above conventional example, the aluminum film is processed by dry etching when forming the wirings 10 and 11.
Depending on the state of the plasma, electric charges are charged up to the wirings 10 and 11 and the wirings 10 and 11 and the n-type semiconductor substrate 1 are charged.
And a high voltage may be generated. On the other hand, in the above conventional example, a large number of contact portions 18 are provided between the first wiring 10 and the polysilicon film 6 and the contact resistance R _C1 between the first wiring 10 and the polysilicon film 6 is small. Since a high voltage is applied between the silicon film 6 and the n-type semiconductor substrate 1, there is a problem that a so-called charging damage occurs in which a dielectric breakdown of the capacitive insulating film 5 occurs.
When the dielectric breakdown of the capacitive insulating film 5 occurs, a current leaks, and the capacitor does not function as a capacitor.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device having a high-quality thin capacitive insulating film.

[0013]

According to a first aspect of the present invention, in order to achieve the above object, a well region of a second conductivity type is formed on a main surface side in a semiconductor substrate of a first conductivity type. A diffusion region of a second conductivity type having a higher concentration than the well region is formed on the main surface side of the region, and the outer peripheral portion of the planar shape of the well region is separated from the diffusion region and continuous with the well region. A high-concentration region of the second conductivity type is formed, a capacitor insulating film made of a thin oxide film is formed on the diffusion region, a low-resistance polysilicon film is formed on the capacitor insulating film, and processed by dry etching. A first wiring which is electrically connected to the polysilicon film through a plurality of contact holes formed in the interlayer insulating film, and a contact hole formed by dry etching and formed in the interlayer insulating film; The high concentration region to a semiconductor device and a second wiring which is electrically connected through,
A region for inhibiting formation of a contact portion with a first wiring is provided on a main surface of the polysilicon film, and a contact portion with the first wiring is formed on a main surface of the polysilicon film. Is provided, the contact resistance between the first wiring and the polysilicon film is increased, and each wiring is formed at the time of dry etching for processing the first wiring and the second wiring. Even when the charge is charged up, the voltage applied between the polysilicon film and the semiconductor substrate can be reduced, the stress applied to the capacitor insulating film can be reduced, and the dielectric breakdown of the capacitor insulating film can be reduced. Thus, a capacitor insulating film made of a high-quality thin oxide film can be employed as a component of the capacitor with high yield.

According to a second aspect of the present invention, a well region of the second conductivity type is formed on the main surface side in the semiconductor substrate of the first conductivity type.
A diffusion region of a second conductivity type having a higher concentration than that of the well region is formed on the main surface side in the well region, and is separated from the diffusion region and is continuous with the well region and has an outer periphery in a planar shape of the well region. A high-concentration region of the second conductivity type surrounding the portion, a capacitor insulating film made of a thin oxide film on the diffusion region, a low-resistance polysilicon film on the capacitor insulating film, and dry etching And a second wiring processed by dry etching and electrically connected to the polysilicon film, and a second wiring processed by dry etching and electrically connected to the high concentration region. A hole for increasing the resistance of the polysilicon film is provided in the polysilicon film, so that the resistance of the polysilicon film can be increased as compared with the related art. The voltage applied between the polysilicon film and the semiconductor substrate can be reduced even when charges are charged up in each wiring during dry etching for processing the first wiring and the second wiring, The stress applied to the capacitor insulating film can be reduced to prevent dielectric breakdown of the capacitor insulating film, and a capacitor insulating film made of a high quality thin oxide film can be employed as a component of the capacitor with a high yield.

According to a third aspect of the present invention, in the first or second aspect of the present invention, an insulating film adjacent to the capacitive insulating film and having a thickness greater than that of the capacitive insulating film is provided. A step extending from the portion formed on the capacitive insulating film to the insulating film and having a reduced thickness; wherein the polysilicon film is provided with the first wiring in a region extended on the insulating film; Since the contact portion is provided, the resistance of the polysilicon film increases due to the provision of the step portion, and electric charge is applied to each wire during dry etching for processing the first wiring and the second wiring. Even in the case of charge-up, the voltage applied between the polysilicon film and the semiconductor substrate can be reduced, the stress applied to the capacitor insulating film can be reduced, and the dielectric breakdown of the capacitor insulating film can be reduced. Sealed, it can be employed with high yield capacity insulating film made of high-quality thin oxide film as a component of a capacitor.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (Embodiment 1) The basic configuration of this embodiment is substantially the same as the conventional configuration, and a first wiring is formed on the main surface of a polysilicon film 6 as shown in FIG. It is characterized in that a region 6a for inhibiting the formation of a contact portion 18 between the gate electrode 10 and the polysilicon film 6 is provided. That is, in the present embodiment, in the planar shape of the polysilicon film 6, FIG.
The portion excluding the portion on the right side of (a) is a region 6a where the formation of the contact portion 18 is prohibited, and the planar size of the first wiring 10 above the polysilicon film 6 is made smaller than that of the conventional example to make the contact hole 18a. Of the first wiring 10
The contact resistance R _C1 (see FIG. 2) between the gate electrode and the polysilicon film 6 is increased as compared with the conventional configuration. Then
In the present embodiment, the region 6 a where the formation of the contact portion 18 with the first wiring 10 is prohibited on the main surface of the polysilicon film 6.
Is provided, the contact resistance between the first wiring 10 and the polysilicon film 6 is increased, and electric charges are charged to the wirings 10 and 11 during the dry etching for processing the first wiring 10 and the second wiring 11. The voltage applied between the polysilicon film 6 and the n-type semiconductor substrate 1 when it is raised can be reduced, the stress applied to the capacitive insulating film 5 can be reduced, and the dielectric breakdown of the capacitive insulating film 5 is prevented. As a result, the capacitor insulating film 5 made of a high-quality thin oxide film can be employed with high yield as a component of the capacitor.

In short, in this embodiment, the capacitance insulating film 5
The dielectric breakdown of the capacitive insulating film 5 can be prevented without changing the thickness and plane size of the polysilicon film 6, the plane size of the polysilicon film 6, the conditions of ion implantation, the chip size, and the like from the conventional configuration.

In the cross-sectional structure shown in FIG. 1B and the equivalent circuit shown in FIG. 2, the same components as those in the conventional configuration are denoted by the same reference numerals, and description thereof is omitted.

(Embodiment 2) The basic configuration of this embodiment is substantially the same as that of Embodiment 1, and as shown in FIG.
A feature is that a plurality of holes 16 are provided in the polysilicon film 6 by etching a part of the polysilicon film 6. The holes 16 may be formed when etching for the conventional patterning of the polysilicon film 6 is performed. This hole 16 is filled with the interlayer insulating film 7.

In this embodiment, the resistance R _PS of the polysilicon film 6 (see FIG. 4) can be increased as compared with the first embodiment and the conventional structure.
The voltage applied between the polysilicon film 6 and the n-type semiconductor substrate 1 when the electric charges are charged up in the respective wirings 10 and 11 during dry etching for processing the 0 and the second wirings 11 is reduced as compared with the first embodiment. The stress applied to the capacitor insulating film 5 can be further reduced than in the first embodiment, and the dielectric breakdown of the capacitor insulating film 5 can be more reliably prevented, and the capacitor insulating film 5 made of a high-quality thin oxide film can be used. Can be employed with high yield as a component of the capacitor.

In short, in this embodiment, the capacitance insulating film 5
Without changing the film thickness, plane size, conditions of ion implantation into the polysilicon film 6, chip size, etc., only a simple change of the glass mask (reticle) for patterning the polysilicon film 6 allows the capacitance insulation. The dielectric breakdown of the film 5 can be prevented.

In the cross-sectional structure shown in FIG. 3B and the equivalent circuit in FIG. 4, the same components as those in the conventional configuration are denoted by the same reference numerals, and description thereof is omitted.

(Embodiment 3) The basic configuration of this embodiment is substantially the same as that of Embodiment 1, and as shown in FIG. 5, a part of the polysilicon film 6 is formed by the p-type diffusion of the n-type semiconductor substrate 1. The difference is that a portion extending from the peripheral portion of the region 3 to the peripheral portion of the p ^{+ -type} high-concentration region 4 extends to a relatively thick oxide film 33 (insulating film) formed on the main surface. Here, the polysilicon film 6 has a step portion extending from a portion formed on the capacitance insulating film 5 to a position above the oxide film 33 and having a small thickness.
In the polysilicon film 6, a contact portion 18 with the first wiring 10 is provided in a region extending on the oxide film 33.
In this embodiment, the LOCOS oxide film 13 as described in the conventional configuration (FIG. 7) is not provided. Also, the oxide film 33 is formed by replacing the oxide film 33 with the n-type semiconductor substrate 1 instead of the step of forming the LOCOS oxide film 13 described in the conventional configuration.
May be formed on the entire surface on the main surface side and patterned using a photolithography technique and an anisotropic dry etching technique. In the present embodiment, since the side edge of the oxide film 33 and the main surface of the capacitor insulating film 5 are substantially orthogonal to each other by employing anisotropic dry etching for patterning the oxide film 33, After patterning the polysilicon film 6, when the polysilicon film 6 is deposited, the film thickness becomes thin at the step connecting the portion formed on the capacitance insulating film 5 and the portion formed on the oxide film 33.

In the present embodiment, however, the resistance R _PS of the polysilicon film 6 can be increased as compared with the conventional structure because the thickness of the polysilicon film 6 is reduced at the above-mentioned step portion. 1st wiring 10 and 2nd wiring 11
The voltage applied between the polysilicon film 6 and the n-type semiconductor substrate 1 when electric charges are charged up in the wirings 10 and 11 at the time of dry etching for processing is reduced as compared with the first embodiment. The stress applied to the film 5 can be further reduced than in the first embodiment, and the dielectric breakdown of the capacitor insulating film 5 can be more reliably prevented. The yield of the capacitor insulating film 5 made of a high-quality thin oxide film as a component of the capacitor is improved. Can be adopted well.

In the cross-sectional structure shown in FIG. 5B and the equivalent circuit in FIG. 6, the same components as those in the conventional configuration are denoted by the same reference numerals, and description thereof will be omitted. In the structure of the present embodiment, the hole 1 described in the second embodiment is formed in the polysilicon film 6.
6 may be provided.

[0026]

According to the first aspect of the present invention, a well region of the second conductivity type is formed on the main surface side of the first conductivity type semiconductor substrate, and the well region of the second conductivity type is formed closer to the main surface side than the well region. A high-concentration second-conductivity-type diffusion region is formed, and a second-conductivity-type high-concentration region surrounding the outer periphery of the well region in a planar shape is formed continuously with the well region apart from the diffusion region. A plurality of contact holes formed on the diffusion region, a capacitance insulating film made of a thin oxide film, a low-resistance polysilicon film formed on the capacitance insulating film, processed by dry etching, and formed in the interlayer insulating film; A first electrode electrically connected to the polysilicon film through
And a second wiring which is processed by dry etching and is electrically connected to the high-concentration region through a contact hole formed in the interlayer insulating film, wherein a main wiring of the polysilicon film is provided. Since a region is provided on the surface to prohibit formation of a contact portion with the first wiring,
The contact resistance between the first wiring and the polysilicon film becomes large, and even if the charge is charged up in each wiring at the time of dry etching for processing the first wiring and the second wiring, the polysilicon is formed. The voltage applied between the silicon film and the semiconductor substrate can be reduced,
It is possible to reduce the stress applied to the capacitive insulating film, prevent the dielectric breakdown of the capacitive insulating film, and have an effect that a capacitive insulating film made of a high-quality thin oxide film can be employed as a component of the capacitor with high yield. .

According to a second aspect of the present invention, a well region of the second conductivity type is formed on the main surface side in the semiconductor substrate of the first conductivity type.
A diffusion region of a second conductivity type having a higher concentration than that of the well region is formed on the main surface side in the well region, and is separated from the diffusion region and is continuous with the well region and has an outer periphery in a planar shape of the well region. A high-concentration region of the second conductivity type surrounding the portion, a capacitor insulating film made of a thin oxide film on the diffusion region, a low-resistance polysilicon film on the capacitor insulating film, and dry etching And a second wiring processed by dry etching and electrically connected to the polysilicon film, and a second wiring processed by dry etching and electrically connected to the high concentration region. Since the polysilicon film is provided with a hole for increasing the resistance of the polysilicon film, the resistance of the polysilicon film can be increased as compared with the prior art.
The voltage applied between the polysilicon film and the semiconductor substrate can be reduced even when charges are charged up in the respective wirings during dry etching for processing the wirings and the second wirings. This has the effect that stress applied to the film can be reduced, dielectric breakdown of the capacitor insulating film is prevented, and a capacitor insulating film made of a high-quality thin oxide film can be employed as a component of the capacitor with high yield.

According to a third aspect of the present invention, in the first or second aspect of the present invention, the semiconductor device further comprises an insulating film adjacent to the capacitive insulating film and having a thickness greater than that of the capacitive insulating film. A step portion extending from the portion formed on the capacitive insulating film to the insulating film and having a reduced thickness; and the polysilicon film is provided in a region extending on the insulating film with a first wiring. Since the contact portion is provided, the resistance of the polysilicon film is increased due to the provision of the step portion, and electric charges are charged to each wire during dry etching for processing the first wire and the second wire. The voltage applied between the polysilicon film and the semiconductor substrate when it is raised can be reduced, stress on the capacitor insulating film can be reduced, and dielectric breakdown of the capacitor insulating film can be prevented. There is an effect that a good yield can be employed as a component of a capacitor from consisting capacitor insulating film thin oxide film such.

[Brief description of the drawings]

FIGS. 1A and 1B show a first embodiment, wherein FIG. 1A is an explanatory diagram of a planar layout, and FIG. 1B is a cross-sectional view taken along line EE ′ of FIG.

FIG. 2 is an equivalent circuit diagram of the above.

3A and 3B show a second embodiment, in which FIG. 3A is an explanatory diagram of a planar layout, and FIG. 3B is a sectional view taken along line EE ′ of FIG. 3A.

FIG. 4 is an equivalent circuit diagram of the above.

5A and 5B show a third embodiment, in which FIG. 5A is an explanatory diagram of a planar layout, and FIG. 5B is a cross-sectional view taken along line EE ′ of FIG.

FIG. 6 is an equivalent circuit diagram of the above.

7A and 7B show a conventional example, in which FIG. 7A is an explanatory view of a planar layout, and FIG. 7B is a sectional view taken along line EE ′ of FIG.

FIG. 8 is an equivalent circuit diagram of the above.

FIG. 9 is an explanatory diagram of the manufacturing method of the above.

[Explanation of symbols]

1 n-type semiconductor substrate 2 p ^- forms well region 3 p-type diffusion region 4 p ⁺ type high concentration region 5 capacitive insulating film 6 a polysilicon film 7 interlayer insulating film 8 contact holes 9 a contact hole 10 first wiring 11 second Wiring 13 LOCOS oxide film 18 Contact part

Claims (3)

[Claims] 1. A well region of a second conductivity type is formed on a main surface side in a semiconductor substrate of a first conductivity type, and a second conductivity type having a higher concentration than the well region is formed on a main surface side in the well region. A high concentration region of a second conductivity type surrounding the outer peripheral portion of the well region in a planar shape is formed continuously with the well region apart from the diffusion region, and a thin region is formed on the diffusion region. A capacitor insulating film made of an oxide film is formed, a low-resistance polysilicon film is formed on the capacitor insulating film, and the polysilicon film is processed by dry etching and electrically connected to the polysilicon film through a plurality of contact holes formed in the interlayer insulating film. A first wiring which is electrically connected and a second wiring which is processed by dry etching and is electrically connected to the high-concentration region through a contact hole formed in the interlayer insulating film. The semiconductor device according to claim 1, wherein a region for inhibiting formation of a contact portion with a first wiring is provided on a main surface of the polysilicon film. 2. A second conductivity type well region is formed on a main surface side in a semiconductor substrate of a first conductivity type, and a second conductivity type having a higher concentration than the well region is formed on a main surface side in the well region. A high concentration region of a second conductivity type surrounding the outer peripheral portion of the well region in a planar shape is formed continuously with the well region apart from the diffusion region, and a thin region is formed on the diffusion region. A first wiring which is formed by forming a capacitor insulating film made of an oxide film, forming a low-resistance polysilicon film on the capacitor insulating film, processing by dry etching, and being electrically connected to the polysilicon film; A second wiring processed by dry etching and electrically connected to the high-concentration region,
A semiconductor device, wherein a hole for increasing the resistance of the polysilicon film is provided in the polysilicon film. 3. An insulating film adjacent to the capacitive insulating film and having a thickness greater than that of the capacitive insulating film, wherein the polysilicon film extends from a portion formed on the capacitive insulating film to over the insulating film. The polysilicon film is provided in a region extending on the insulating film.
3. The semiconductor device according to claim 1, wherein a contact portion with the wiring is provided.