JP2000091550A - Solid image pickup device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make feasible high sensitizing a solid image pickup device by decreasing the charge accumulation capacity of a photodiode. SOLUTION: Multiple picture elements containing the second conductivity type photodetecters 12 formed in the first conductivity type semiconductor substrate 11 and amplifier circuits electrically connecting to the photodetectors 12 are arranged in this solid image pickup device. In such a constitution, the first conductivity type diffused regions 13 in lower impurity concentration than that of the semiconductor substrate 11 are formed in the semiconductor substrate 11 connecting to at least a part of the bottom face of the photodetectors 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a MOS solid-state imaging device using a MOS (metal oxide semiconductor) transistor for reading out a signal, and a method of manufacturing the same.

[0002]

2. Description of the Related Art Solid-state imaging devices are roughly classified into two types according to a signal reading method. CCD (charge coupled device) that sequentially transfers signal charges
And a MOS type in which a signal is read out pixel by pixel using a readout circuit including a MOS transistor formed in each pixel. In recent years, MOS type solid-state imaging devices, especially CMOS
A so-called CMOS solid-state imaging device in which a pixel portion and a peripheral circuit are integrated by a (complementary MOS) process has advantages of low voltage and low power consumption, and has the advantage that the peripheral circuit can be integrated into one chip. It is attracting attention as an image input element of a portable device such as a camera.

FIG. 4 shows the structure of a conventional MOS type solid-state imaging device. Each pixel of the solid-state imaging device includes a light receiving unit and an amplifier circuit for amplifying and outputting an electric signal generated in the light receiving unit. The light receiving section 42 is a p-type semiconductor substrate 4
1 is an n-type diffusion region formed therein and forms a photodiode by bonding with a substrate. The electron-hole pairs generated by the incident light are
The electrons are separated by a depletion layer formed at the pn junction between the electrons, and the electrons are accumulated in the light receiving section 42. The potential change of the light receiving section 42 caused by the charge accumulation is amplified and output by the amplifier circuit.

[0004]

As the number of pixels and the size of the solid-state imaging device increase, the sensitivity of the device has to be improved. In order to improve the sensitivity of the solid-state imaging device, the area of the light receiving unit may be increased to increase the amount of incident light that is photoelectrically converted. However, when the area of the light receiving section is increased, the junction area between the light receiving section and the substrate increases, so that the charge storage capacity of the photodiode increases. When the charge storage capacity increases, the conversion rate when converting charges into a voltage decreases, and as a result, there is a problem that a sufficient improvement in sensitivity of the solid-state imaging device cannot be realized.

An object of the present invention is to provide a high-sensitivity solid-state imaging device and a method of manufacturing the same.

[0006]

In order to achieve the above object, a first solid-state imaging device according to the present invention comprises: a second conductive type light receiving portion formed in a first conductive type semiconductor substrate; A solid-state imaging device in which a plurality of pixels including an amplifier circuit electrically connected to a portion are arranged, wherein a width of a depletion layer formed at a junction between the light receiving portion and the semiconductor substrate is larger than a width of the semiconductor substrate surface. A region in the semiconductor substrate including at least a part of the bottom surface of the light receiving unit is larger than a region in contact with the light receiving unit.

According to such a configuration, the charge storage capacity of the photodiode can be reduced by expanding the depletion layer at the junction between the light receiving portion and the substrate in the region inside the semiconductor substrate. Therefore, according to this solid-state imaging device, a charge / voltage conversion can be performed with a small capacitance, so that a high conversion rate can be obtained and the sensitivity can be improved. Further, since the depletion layer is expanded in the depth direction of the semiconductor substrate, the spectral sensitivity on the long wavelength side can be improved. Further, in the region on the surface of the semiconductor substrate, the width of the depletion layer at the junction between the light receiving portion and the substrate is narrow, so that an increase in dark current can be suppressed.

In the first solid-state imaging device, the width of the depletion layer is 1.5 to 10 times that of a region in contact with the semiconductor surface in a region in the semiconductor substrate including at least a part of a bottom surface of the light receiving section. Preferably it is twice. According to this preferred example, it is possible to reliably achieve both high sensitivity of the solid-state imaging device and suppression of dark current.

In order to achieve the above object, a second solid-state imaging device according to the present invention includes a light-receiving portion of a second conductivity type formed in a semiconductor substrate of a first conductivity type, and electrically connected to the light-receiving portion. A solid-state imaging device in which a plurality of pixels including an amplifier circuit are arranged, wherein a first conductivity type having an impurity concentration lower than that of the semiconductor substrate is provided in a region in the semiconductor substrate that is in contact with at least a part of a bottom surface of the light receiving unit. Or a diffusion region of the second conductivity type having an impurity concentration lower than that of the light receiving portion is formed.

According to such a configuration, the junction capacitance of the pn junction formed between the light receiving portion and the semiconductor substrate, that is, the charge storage capacitance of the photodiode can be reduced. Therefore, according to this solid-state imaging device, a charge / voltage conversion can be performed with a small capacitance, so that a high conversion rate can be obtained and the sensitivity can be improved. Further, the depletion layer formed at the junction between the light receiving portion and the semiconductor substrate can be expanded in the depth direction of the semiconductor substrate, so that the spectral sensitivity on the long wavelength side can be improved.

In the second solid-state imaging device, it is preferable that the diffusion region is formed so as to avoid a region on the surface of the semiconductor substrate which is in contact with the light receiving section. According to this preferred example, it is possible to avoid an increase in the depletion layer formed at the junction between the light receiving portion and the semiconductor substrate on the surface of the semiconductor substrate, and thus it is possible to suppress an increase in dark current.

Further, in the second solid-state imaging device, the width of the diffusion region is one of the width of the light receiving portion.
Preferably it is 0 to 100%. This is because it becomes easy to form the diffusion region so as to avoid the region on the surface of the semiconductor substrate.

According to a third aspect of the present invention, there is provided a solid-state imaging device according to the present invention, wherein a light receiving unit of a second conductivity type and a charge discharging unit formed in a semiconductor substrate of a first conductivity type; A solid-state imaging device in which a plurality of pixels including a gate electrode formed on the semiconductor substrate via an insulating film between the charge discharging unit and an amplifier circuit electrically connected to the light receiving unit are arranged. A first conductive layer having an impurity concentration higher than that of the semiconductor substrate so as to include a region located below the gate electrode in the semiconductor substrate and to avoid a region in contact with at least a part of the bottom surface of the light receiving unit. A mold diffusion region is formed.

With such a configuration, the charge storage capacity of the photodiode can be reduced, and a high-sensitivity solid-state imaging device can be obtained. In addition, a depletion layer formed at a junction between the light receiving unit and the semiconductor substrate is expanded in a depth direction of the semiconductor substrate,
The spectral sensitivity on the long wavelength side can be improved. Also,
This solid-state imaging device can be manufactured by a conventional CMOS process if a mask for forming a p-type well (a diffusion region of the first conductivity type) is a pattern avoiding a part of the region under the light receiving portion. is there.

In the third solid-state imaging device, it is preferable that the diffusion region is formed so as to include a region on the surface of the semiconductor substrate which is in contact with the light receiving section. This is because a depletion layer formed at a junction between the light receiving unit and the semiconductor substrate can be prevented from increasing on the surface of the semiconductor substrate, and an increase in dark current can be suppressed.

In the third solid-state imaging device, the diffusion region is a region that is in contact with a bottom surface of the light receiving unit and avoids a region having a width of 10 to 100% of a formation width of the light receiving unit. It is preferable that it is formed as follows. This is because the diffusion region can be easily formed so as to include the region on the surface of the semiconductor substrate that is in contact with the light receiving portion.

To achieve the above object, a first method for manufacturing a solid-state imaging device according to the present invention comprises a second conductive type light receiving portion formed in a first conductive type semiconductor substrate; A method for manufacturing a solid-state imaging device in which a plurality of pixels including an electrically connected amplifier circuit are arranged, wherein the step of forming the light receiving unit and the region in the semiconductor substrate contacting at least a part of the bottom surface of the light receiving unit Forming a first conductivity type diffusion region having a lower impurity concentration than the semiconductor substrate or a second conductivity type diffusion region having a lower impurity concentration than the light receiving portion.

According to such a manufacturing method, the junction capacitance of the pn junction formed between the light receiving section and the semiconductor substrate, that is, the charge storage capacity of the photodiode is reduced, and a high-sensitivity solid-state imaging device is manufactured. can do. In addition, a depletion layer formed at the junction between the light receiving section and the semiconductor substrate is expanded in the depth direction of the semiconductor substrate, so that a solid-state imaging device having excellent spectral sensitivity on the long wavelength side can be obtained.

In the first manufacturing method, it is preferable that the diffusion region is formed so as to avoid a region on the surface of the semiconductor substrate which is in contact with the light receiving portion. This is because an increase in dark current can be suppressed.

In the first manufacturing method, the formation width of the diffusion region may be set to 10 to 1 times the formation width of the light receiving portion.
It is preferably set to 00%. This is because it becomes easy to form the diffusion region so as not to contact the surface of the semiconductor substrate.

In order to achieve the above object, a second method of manufacturing a solid-state imaging device according to the present invention includes a method of manufacturing a solid-state imaging device, comprising: a light-receiving section of a second conductivity type formed in a semiconductor substrate of a first conductivity type;
A solid body in which a plurality of pixels including a gate electrode formed on the semiconductor substrate between the light receiving unit and the charge discharging unit via an insulating film, and an amplifier circuit electrically connected to the light receiving unit are arranged. A method of manufacturing an imaging device, comprising: a step of forming the gate electrode; a step of forming the light receiving unit and the charge discharging unit; and a region located below the gate electrode in the semiconductor substrate. And forming a first conductivity type diffusion region having a higher impurity concentration than the semiconductor substrate so as to avoid a region in contact with at least a part of the bottom surface of the light receiving unit.

With such a structure, the junction capacitance of the pn junction formed between the light receiving portion and the semiconductor substrate can be improved.
That is, the charge storage capacity of the photodiode is reduced,
A high-sensitivity solid-state imaging device can be manufactured. Also,
The depletion layer formed at the junction between the light receiving portion and the semiconductor substrate is expanded in the depth direction of the semiconductor substrate, so that a solid-state imaging device having excellent spectral sensitivity on the long wavelength side can be obtained. Further, this manufacturing method can be carried out by the same operation as a conventional CMOS process, provided that the mask for forming the p-type well (the diffusion region of the first conductivity type) is a pattern avoiding a part of the region under the light receiving portion. .

In the second manufacturing method, it is preferable that the diffusion region is formed so as to include a region on the surface of the semiconductor substrate which is in contact with the light receiving portion. This is because an increase in dark current can be suppressed.

[0024] In the second manufacturing method, the diffusion region may be a region in contact with a bottom surface of the light receiving unit,
It is preferable to form so as to avoid a region having a width of 10 to 100% of the light receiving portion formation width. This is because the diffusion region can be easily formed so as to include the region on the surface of the semiconductor substrate that is in contact with the light receiving portion.

[0025]

(First Embodiment) FIG. 1 is a sectional view showing an example of the structure of a pixel portion of a solid-state imaging device according to the present invention. This solid-state imaging device employs a method of amplifying and outputting the voltage of the light receiving unit, and each pixel includes a light receiving unit and three transistors for amplifier, reset, and selection. The reset transistor is a transistor having a light receiving section as a source, and a charge discharging section as a drain thereof is electrically connected to a power supply voltage. The amplifier transistor has a gate electrically connected to the light receiving section, a drain electrically connected to the power supply voltage, and a source electrically connected to the drain of the selection transistor. The source of the selection transistor is connected to the output line.

To briefly explain the role of each transistor, the amplifier transistor forms a source follower amplifier circuit with a load transistor (not shown) provided in another region, and amplifies the voltage of the light receiving section. Out of the output line. The selection transistor is a switch for extracting the output of the amplifier transistor, and has a function of selecting a pixel from which a signal is read. Further, the reset transistor has a function of discharging the signal charges held by the light receiving unit to the charge discharging unit at regular time intervals.

Hereinafter, the structure of the area around the light receiving section shown in the sectional view of FIG. 1 will be described in detail. A light receiving portion 12 and a charge discharging portion 14 are formed in the semiconductor substrate 11 in this region, and a reset transistor for a reset transistor is formed on the semiconductor substrate 11 between the light receiving portion 12 and the charge discharging portion 14 via an insulating film 15. A gate electrode 16 is formed. Although not shown, an interlayer insulating film, a metal light-shielding film having an opening on the light-receiving portion,
A surface protection film and the like are formed.

The semiconductor substrate 11 is not particularly limited as long as it is a p-type semiconductor substrate having an impurity concentration in a range capable of obtaining a threshold voltage required for an nMOS such as a reset transistor. However, if the impurity concentration of the p-type semiconductor substrate 11 is low, the width of the depletion layer 17 formed at the junction with the light receiving unit 12 increases in a region in contact with the surface of the semiconductor substrate, which may cause an increase in dark current. There is. Therefore, the impurity concentration of the p-type semiconductor substrate 11 is 1.5 × 10
¹⁵ cm ^-3 or more (specific resistance 10 Ω · cm or less), and 3 ×
About 10 ¹⁵ -5 × 10 ¹⁵ cm ^-3 (specific resistance 3-5 Ω · cm
Degree).

As the p-type semiconductor substrate 11, a semiconductor substrate having a p-type well formed in a surface layer can be used. The impurity concentration of the p-type well is not particularly limited as long as the threshold voltage required for the nMOS can be obtained. From the viewpoint of reducing dark current, the impurity concentration is 1 × 10 ¹⁷ cm ⁻³ or more, and more preferably 1.5 × 10 ¹⁷ cm ⁻³ or more. It is preferably from × 10 ^{17 to} 3 × 10 ¹⁷ cm ⁻³ . The semiconductor substrate used at this time is
The conductivity type and impurity concentration are not particularly limited as long as a p-type well can be formed.

The light receiving section 12 is an n-type impurity diffusion region formed in the p-type semiconductor substrate 11, and forms a photodiode by a pn junction with the semiconductor substrate 11.
The impurity concentration of the light receiving section 12 is not particularly limited as long as it can perform photoelectric conversion and can be electrically connected to an amplifier circuit, but is preferably 10 ²⁰ cm ⁻³ or more. The diffusion depth of the light receiving section 12 is 0.2 to 0.4 μm.
The degree is appropriate.

In the solid-state imaging device according to the present embodiment, a p ⁻ type diffusion region 13 is formed in a region in contact with at least a part of the bottom surface of the light receiving section 12 in the p type semiconductor substrate 11. By providing this p ⁻ -type diffusion region 13, the width of the depletion layer at the pn junction between the light-receiving portion and the substrate is increased to reduce the charge storage capacitance of the photodiode, thereby realizing high sensitivity of the solid-state imaging device. be able to. Further, p ^- -type diffusion impurity concentration in the region 13 and the light receiving unit 12 and p ^- the junction area between the diffusion regions 13, it is possible to adjust the standard sensitivity by adjusting the charge storage capacity of the photodiode.

The impurity concentration of p ⁻ type diffusion region 13 is not particularly limited as long as it is lower than that of p type semiconductor substrate 11 (or p type well).
× 10 ¹⁵ cm ^-3 or less, more preferably 4 × 10 ^{14 to} 6 ×
It is about 10 ¹⁴ cm ^-3 . As the impurity concentration of the p ⁻ type diffusion region 13 is reduced, the charge storage capacity of the photodiode can be reduced.

With such an impurity concentration,
The junction capacitance per unit area at the junction between the light receiving unit 12 and the p ⁻ type diffusion region 13 is smaller than the junction between the light receiving unit 12 and the p-type semiconductor substrate 11. In other words, the width of the depletion layer formed at the junction between the light receiving section 12 and the p ⁻ -type diffusion region 13 is larger than the junction between the light receiving section 12 and the p-type semiconductor substrate 11. The width of the depletion layer (a in FIG. 1) at the junction between the light receiving section 12 and the p ⁻ type diffusion region 13 is 0.6 to 2.0.
It is preferably about 0 μm, and more preferably about 1.2 to 1.8 μm. On the other hand, the depletion layer width (b in FIG. 1) at the junction between the light receiving unit 12 and the p-type semiconductor substrate 11 is 0.2 to 1.
Suitably, it is about 0 μm.

The larger the junction area between the light receiving section 12 and the p ⁻ type diffusion region 13, the more the charge storage capacity of the photodiode can be reduced. However, on the surface of the semiconductor substrate, an increase in dark current may be caused.
It is preferable that no junction is formed with the p ⁻ type diffusion region 13. Therefore, it is preferable that the p ⁻ -type diffusion region 13 be buried under the light receiving portion, avoiding the region on the surface of the semiconductor substrate in contact with the light receiving portion 12. Therefore, p ^-
It is preferable that the forming width c of the mold diffusion region 13 is equal to or smaller than the forming width d of the light receiving unit 12, specifically, 10 to 100% of the forming width of the light receiving unit, and more preferably 40 to 100%.
Preferably it is 80%. Also, in terms of the formation area, 10 to 100% of the formation area of the light receiving section 12, and more preferably 2%
Preferably it is 0-65%.

The diffusion depth of the p ⁻ type diffusion region 13 is
About 0.8 to 2.0 μm is appropriate.

Next, an example of a method for manufacturing the solid-state imaging device according to the present embodiment will be described.

First, the p-type silicon substrate 1 is thermally oxidized.
An insulating film is formed on 1. A polysilicon film is deposited on the insulating film by a low pressure CVD method. The gate electrode 16 is formed by removing a part of the polysilicon film by etching.

Next, a resist is formed so as to cover a part of the semiconductor substrate 11 and the gate electrode 16, and an n-type impurity is applied to an appropriate region in the semiconductor substrate 11 within a range where the conductivity type of the semiconductor substrate is not reversed. P ^- diffusion region 1 by ion implantation
Form 3 In this ion implantation, for example, phosphorus is used as an n-type impurity, the acceleration voltage is set to 50 to 800 keV,
The dose is set at 1 × 10 ¹¹ to 1 × 10 ¹³ cm ⁻² .

After removing the resist, an n-type impurity is ion-implanted using the gate electrode 16 as a mask to form the light receiving section 12 and the charge discharging section 14, thereby forming a reset transistor. At this time, the light receiving section 12 is formed such that at least a part of the bottom surface is in contact with the p ⁻ type diffusion region. Also, preferably, the light receiving unit 12 is a p ^- diffusion region 1
The size is adjusted to be equal to or larger than 3, and the p ⁻ diffusion region 13 is embedded in the semiconductor substrate 11 by the light receiving unit 12. This ion implantation, for example,
Using arsenic as an n-type impurity, an acceleration voltage of 40 ke
V and the dose amount are set to 5 × 10 ¹⁵ cm ⁻² .

Further, an interlayer insulating film, a metal wiring, and the like are formed, and the light receiving portion and the charge discharging portion are electrically connected to an amplifier transistor and the like formed in another region of the semiconductor substrate as shown in FIG. Is done. Although not particularly limited, a silicon oxide film formed by a low pressure CVD method is used as the interlayer insulating film, and an aluminum film is used as the metal wiring. Further, a metal light-shielding film, a surface protection film, and the like having an opening in a portion corresponding to an upper part of the light receiving unit are appropriately formed. An aluminum film can be used as the metal light shielding film, and a silicon nitride film formed by a plasma CVD method can be used as the surface protection film.

The film forming method such as thermal oxidation or CVD method and the etching method used in the above-mentioned manufacturing method may be basically performed according to a conventional method.

(Second Embodiment) FIG. 2 is a sectional view showing another example of the solid-state imaging device of the present invention. The structure of each pixel of this solid-state imaging device is the same as that of the first embodiment, except for the structure of the area around the light receiving section shown as a cross-sectional view in FIG. Hereinafter, the area around the light receiving unit will be described in detail. In this region, a light receiving portion 22 and a charge discharging portion 24 are formed in a semiconductor substrate 21, and a reset transistor is formed on the semiconductor substrate 21 between the light receiving portion 22 and the charge discharging portion 24 via an insulating film 25. A gate electrode 26 is formed. Although not shown, the semiconductor substrate 21
Above this, an interlayer insulating film, a metal light shielding film having an opening on the light receiving portion, a surface protection film, and the like are further formed.

As the semiconductor substrate 21, as in the first embodiment, a p-type semiconductor substrate or a semiconductor substrate having a p-type well formed thereon can be used. The light receiving section 22
Is preferably an n-type diffusion region having an impurity concentration of 1 × 10 ²⁰ cm ⁻³ or more and a diffusion depth of about 0.2 to 0.4 μm, as in the first embodiment.

In this embodiment, the p-type semiconductor substrate 2
An n ⁻ -type diffusion region 23 is formed in a region in contact with at least a part of the bottom surface of the light receiving unit 22 in 1. The n ⁻ type diffusion region 23 forms a photodiode together with the light receiving unit 22 by a pn junction with the semiconductor substrate 21.
By providing the n ⁻ -type diffusion region 23, the width of the depletion layer of the pn junction between the light receiving portion and the substrate is increased, the charge storage capacity of the photodiode is reduced, and high sensitivity of the solid-state imaging device is realized. I have. Further, n ^- type impurity concentration in the diffusion region 23 and the n ^- by the junction area between the diffusion region 23 and the semiconductor substrate 21, by appropriately adjusting the charge storage capacity of the photo diode, can adjust the standard sensitivity.

The impurity concentration of the n ⁻ -type diffusion region 23 is not particularly limited as long as it is lower than the impurity concentration of the light receiving section 22, but is preferably 1 × 10 ¹⁶ cm ⁻³ or less, and more preferably 5 × 10 ¹⁶ cm ⁻³ or less. ^{It is 15} to 8 × 10 ¹⁵ cm ⁻³ . In addition,
As the impurity concentration of the n ⁻ type diffusion region 23 is lower, the charge storage capacity of the photodiode can be reduced.

With such an impurity concentration,
The junction capacitance per unit area at the junction between the n ⁻ type diffusion region 23 and the semiconductor substrate 21 is smaller than the junction between the light receiving unit 22 and the semiconductor substrate 21. In other words, n ^-
The width of the depletion layer formed at the junction between the mold diffusion region 23 and the semiconductor substrate 21 is larger than the junction between the light receiving unit 22 and the semiconductor substrate 21. N ^- type diffusion region 23 and semiconductor substrate 2
The width of the depletion layer (a in FIG. 2) at the junction with No. 1 is 0.8 to
It is preferably about 2.5 μm, more preferably about 1.2 to 2.0 μm. On the other hand, the depletion layer width (b in FIG. 2) at the junction between the light receiving unit 22 and the semiconductor substrate 21 is 0.2 to 0.2.
Suitably, it is about 1.0 μm.

As the junction area between the n ⁻ type diffusion region 23 and the semiconductor substrate 21 increases, the charge storage capacity of the photodiode can be reduced. However, on the surface of the semiconductor substrate, it is preferable that the junction between the light receiving portion 22 and the n ⁻ -type diffusion region 23 is not formed because there is a possibility that the dark current increases. Therefore, the n ⁻ type diffusion region 23 is
It is preferable that the entirety of the semiconductor substrate is buried under the light receiving section 22, avoiding a region on the surface of the semiconductor substrate in contact with 2. Therefore, the formation width e of the n ⁻ type diffusion region 23 is
2 is preferably equal to or smaller than the formation width d.
%, More preferably 40 to 80%. Also,
In terms of the formation area, 10 to 10 of the formation area of the light receiving portion 22
It is preferably 0%, more preferably 20 to 65%.

The diffusion depth of the n ⁻ type diffusion region 23 is
About 0.8 to 2.0 μm is appropriate.

The solid-state imaging device according to the present embodiment is similar to the solid-state imaging device according to the first embodiment except that a step of forming an n ⁻ type diffusion region is performed instead of a step of forming a p ⁻ type diffusion region. It can be manufactured in the same manner as the manufacturing method described.

After a resist is formed on the semiconductor substrate 21 on which the insulating film 25 and the gate electrode 26 are formed, an n-type impurity is ion-implanted to form an n ⁻ -type diffusion region 23 in an appropriate region in the semiconductor substrate 21. I do. This ion implantation is performed, for example, by using phosphorus as an n-type impurity and increasing the acceleration voltage to 50.
Up to 800 keV and dose amount of 1 × 10 ¹² to 1 × 10 ¹⁵ c
implemented as m- ² .

After the resist is removed, an n-type impurity is ion-implanted using the gate electrode 26 as a mask to form the light receiving section 22 and the charge discharging section 24. At this time, the light receiving unit 22
Is formed such that at least a part of its bottom surface is in contact with n ⁻ type diffusion region 23. Preferably, the light receiving unit 2
2 the n ^- is adjusted so that diffusion region 23 equal to or greater than the size, n ^- -type diffusion region 23 is embedded in the semiconductor substrate 21 by the light-receiving unit 22. In this ion implantation, for example, arsenic is used as an n-type impurity, the acceleration voltage is 40 keV, and the dose is 5 × 10 ¹⁵ cm.
Implemented as ^-2 .

Further, an interlayer insulating film, a metal wiring, a metal light-shielding film having an opening in a portion above the light-receiving portion, a surface protective film, and the like are appropriately formed, and a solid-state imaging device is obtained.

The film formation method such as thermal oxidation or CVD method and the etching method used in the above manufacturing method may be basically performed according to a conventional method.

(Third Embodiment) A solid-state imaging device according to this embodiment includes a pixel portion and peripheral circuits (for example, a scanning circuit for selecting a pixel, a timing generation circuit, a noise cancellation circuit, etc.) formed by a CMOS process. C integrated using
This is a MOS type solid-state imaging device. The present solid-state imaging device has an nMOS and a pMOS in the same semiconductor substrate.
A p-type well is formed in a region where a type well and an nMOS are formed.

FIG. 3 is a sectional view showing the structure of the pixel portion of the solid-state imaging device according to this embodiment. Each pixel includes a light receiving section and three transistors for amplifier, reset, and selection, as in the first embodiment. The connection between these members and the function of each member are as described in the first embodiment.

Hereinafter, the structure of the region around the light receiving portion, which is shown in a sectional view in FIG. 3, will be described in detail. In the semiconductor substrate 31 in this region, a p-type well 33 for forming an nMOS reset transistor is formed. The light receiving section 32 and the charge discharging section 34 are formed in the semiconductor substrate 31.
The gate electrode 36 of the reset transistor is formed on the semiconductor substrate 31 between the gate electrode and the semiconductor substrate 31 with an insulating film 35 interposed therebetween.

The semiconductor substrate 31 is not particularly limited as long as it is a p-type semiconductor substrate having an impurity concentration in a range where a p-type well and an n-type well can be formed. Preferably, the impurity concentration is 2 × 10 ¹⁵ cm ⁻³ or less (specific resistance is 5Ω).
Cm or more), more preferably an impurity concentration of 1 × 10 ¹⁵
~ 1.5 × 10 ¹⁵ cm ^-3 (resistivity is 10-15Ω ·
cm) (p ^- type semiconductor substrate).

The light receiving portion 32 is an n-type impurity diffusion region formed in the p ⁻ type semiconductor substrate 31.
A photodiode is formed by a pn junction with the above.
The impurity concentration of the light receiving section 32 is not particularly limited as long as it can perform photoelectric conversion and can be electrically connected to an amplifier circuit, but is preferably 1 × 10 ²⁰ cm ⁻³ or more. The diffusion depth of the light receiving section 32 is 0.2 to 0.4.
About μm is appropriate.

At least below the gate electrode 36
The surface layer of the semiconductor substrate 31 including the region
A p-type well 33 is formed. of the p-type well 33
The impurity concentration is p^-From the impurity concentration of the semiconductor substrate 31
Required for nMOS such as reset transistors
Is particularly limited as long as the threshold voltage can be obtained.
Not. However, the impurity concentration of the p-type well 33 is low.
If too long, bonding with the light receiving portion 32 on the surface of the semiconductor substrate
The width of the depletion layer formed in the part increases, increasing the dark current
May be caused. Therefore, impurities in the p-type well 33
The concentration is 1 × 10 ¹⁷cm^-3Above, furthermore 1.5 × 10¹⁷~
3 × 10¹⁷cm^-3It is preferable to set the degree. Also, p
The diffusion depth of the mold well 33 is suitably about 1.0 μm.
You.

The p-type well 33 is formed so as to avoid a region in contact with at least a part of the bottom surface of the light receiving section 32. That is, at least a part of the bottom of the light receiving unit 32 is in contact with the p ⁻ -type region having a lower impurity concentration than the p-type well 33. As described above, by adjusting the impurity concentration of the semiconductor substrate at the junction with the light receiving section 32 to be low in some regions, the width of the depletion layer at the pn junction between the light receiving section and the substrate is increased, and , The charge storage capacity of the solid-state imaging device can be improved. Further, the substrate region where the p-type well 33 is not formed (hereinafter, referred to as “p ⁻ -type region”) and the light receiving unit 3
The standard sensitivity can be adjusted by appropriately adjusting the charge storage capacity of the photodiode depending on the junction area with the photodiode 2.

The junction capacitance per unit area at the junction between the light receiving section 32 and the p ⁻ -type region 31 is smaller than that at the junction between the light receiving section 32 and the p-type well 33. In other words,
The width of the depletion layer formed at the junction between the light receiving part 32 and the p-type region 31 is larger than the junction between the light receiving part 32 and the p-type well 33. The width of the depletion layer (a in FIG. 3) at the junction between the light receiving portion 32 and the p ⁻ -type region 31 is preferably about 1.0 to 3.0 μm, and more preferably about 1.5 to 2.0 μm. On the other hand, it is appropriate that the depletion layer width (b in FIG. 3) at the junction between the light receiving section 32 and the p-type well 33 is about 0.2 to 0.5 μm.

The larger the junction area between the light receiving portion 32 and the p ⁻ type region 31, the more the charge storage capacity of the photodiode can be reduced. However, on the surface of the semiconductor substrate,
Since the dark current may increase, the light receiving unit 32 and p
^- It is preferable that the junction between the type region 31 is not formed.
Therefore, it is preferable that the p-type well 33 be formed so as to include at least a region in contact with the light receiving section 32 on the surface of the semiconductor substrate. In this case, the width f of the portion of the bottom surface of the light receiving section 32 that is in contact with the p ⁻ -type region is 10 to 1 times the forming width d of the light receiving section 32.
The size is preferably set to 00%, more preferably 40 to 80%. The area of the bottom surface of the light receiving unit 32 that is in contact with the p ⁻ type region is 10 to 100% of the bottom surface of the light receiving unit 32, and more preferably 20%.
Preferably it is ~ 65%.

Next, an example of a method for manufacturing the solid-state imaging device according to the present embodiment will be described.

First, a p-type impurity is ion-implanted into the p ⁻ -type silicon substrate 31 to form a p-type well 33. The ion implantation is performed so as to avoid at least a part of a region to be the light receiving unit 32. In this ion implantation, for example, an acceleration voltage of 4
The operation is performed at 00 keV, a dose of 4 × 10 ¹² cm ⁻² , and boron at an acceleration voltage of 50 keV and a dose of 5 × 10 ¹² cm ⁻² .

Next, after an insulating film is formed on the p-type silicon substrate 31 by thermal oxidation, a polysilicon film is deposited by a low pressure CVD method, and a part thereof is removed by etching to form a gate electrode 36. Next, n-type impurities are ion-implanted using the gate electrode 36 as a mask to form the light receiving section 32 and the charge discharging section 34. At this time,
The light receiving portion 32 is formed so that at least a part of the bottom surface thereof is in contact with a region (p ⁻ -type region 31) in the semiconductor substrate where the p-type well 33 is not formed. Preferably, light receiving section 32 is formed so as to be in contact with p-type well 33 on the surface of the semiconductor substrate. This ion implantation
For example, by using arsenic as an n-type impurity,
The operation is performed at 0 keV and a dose of 5 × 10 ¹⁵ cm ⁻² .

Further, an interlayer insulating film, a metal wiring and the like are formed, and the light receiving portion and the charge discharging portion are electrically connected to an amplifier transistor and the like formed in another region of the semiconductor substrate as shown in FIG. Is done. Further, a metal light-shielding film, a surface protection film, and the like having an opening in a portion corresponding to an upper part of the light receiving unit are appropriately formed.

The film forming method such as thermal oxidation or CVD method and the etching method used in the above manufacturing method may be basically performed according to a conventional method.

[0068]

(Example 1) A solid-state imaging device having a structure similar to that of FIG. 1 was manufactured. Impurity concentration 5 × as semiconductor substrate
Using a p-type silicon substrate of 10 ¹⁵ cm ^-3 (specific resistance 3 Ω · cm), a silicon oxide film was formed on the p-type silicon substrate by thermal oxidation. Decompression CV on silicon oxide film
After depositing a polysilicon film by the method D, the polysilicon film was patterned by etching to form a gate electrode.
Next, the acceleration voltage was set to 600 keV and the dose was set to 2 × 10 ¹¹
Phosphorus ions were implanted at a density of cm ⁻² to form a p ⁻ type diffusion region. The impurity concentration of the formed p ⁻ type diffusion region is 2 ×
It was 10 ¹⁵ cm ^-3 . Next, using the gate electrode as a mask, the acceleration voltage is 40 keV and the dose is 5 × 10 ¹⁵ cm.
^{As -2} , arsenic was ion-implanted to form a light receiving portion and a charge discharging portion. The area of the formed light receiving portion was 60 μm ² , and the impurity concentration was 2 × 10 ²⁰ cm ⁻³ . As shown in FIG. 1, the light receiving section and the charge discharging section were electrically connected to an amplifier transistor, a selection transistor, and a power supply voltage formed in another region of the semiconductor substrate to obtain a solid-state imaging device.

In the above manufacturing method, the bonding area between the light receiving portion and the p ⁻ type diffusion region is set to 30% of the light receiving portion area (sample No.
1) and 60% (sample No. 2) were adjusted to produce two types of solid-state imaging devices. When the depletion layer width of these solid-state imaging devices was examined, it was found that the distance between the light receiving section and the substrate (about 1.6 μm) between the light receiving section and the p ⁻ -type diffusion region (a in FIG. ) Was about 0.8 μm.

For each solid-state imaging device, the photodiode capacity and the incident light amount of 10 lux (color temperature 32
00K), the sample N
o. 1, the photodiode capacity is 16.8 fF,
The output voltage was 100 mV. In No. 2, the photodiode capacitance was 9.6 fF and the output voltage was 160 mV. Note that the output voltage was measured with the capacitance of the amplifier transistor being 2 fF and the power supply voltage being 5.0 V.

Example 2 A solid-state imaging device having the same structure as that of FIG. 2 was manufactured in the same manner as in Example 1 except that an n ⁻ type diffusion region was formed instead of the p ⁻ type diffusion region. . The formation of the n ^- type diffusion region is performed by increasing the acceleration voltage to 600 ke.
V was performed by ion implantation of phosphorus at a dose of 1 × 10 ¹² cm ⁻² . The impurity concentration of the formed n ⁻ -type diffusion region was 1 × 10 ¹⁶ cm ⁻³ .

The junction area between the light receiving portion and the n ⁻ -type diffusion region was adjusted to 30% (sample No. 3) and 60% (sample No. 4) of the light receiving portion area, and two types of solid-state imaging devices were manufactured. .
When the depletion layer width of these solid-state imaging devices was examined, it was found that the light receiving portion (n ⁺ type diffusion region) on the substrate surface was approximately 2.0 μm between the n ⁻ type diffusion region and the substrate (a in FIG.
It was about 0.8 μm between the substrates (b in FIG. 2).

For each solid-state image pickup device, the photodiode capacity and the incident light amount 10 lux (color temperature 32
00K), the sample N
o. In Sample No. 3, the photodiode capacity was 15 fF and the output voltage was 110 mV. In No. 4, the photodiode capacity was 9 fF and the output voltage was 170 mV.
Note that the output voltage is determined by the capacitance of the amplifier transistor being 2f.
F, the power supply voltage was measured at 5.0 V.

(Embodiment 3) A solid structure having the same structure as that of FIG.
A body imaging device was manufactured. Impurity concentration as semiconductor substrate
1.5 × 10^Fifteencm^-3(Specific resistance 10Ω · cm)
A recon substrate was used. Acceleration on this p-type silicon substrate
400 keV voltage, dose 4 × 10¹²cm ^-2As e
Ion is ion-implanted, and the acceleration voltage is 50 keV,
5 × 10 ¹²cm^-2Implanted boron as
A p-type well was formed. The impurity concentration of the p-type well is 2 ×
10¹⁷cm^-3Met. As shown in FIG.
Avoid at least part of the bottom surface of the light-receiving part formed later.
It was formed as follows. Next, thermal oxidation on the p-type silicon substrate
To form a silicon oxide film on the silicon oxide film
After depositing a polysilicon film by low pressure CVD,
This is patterned by etching to form the gate electrode.
Done. Using the gate electrode as a mask, an acceleration voltage of 40 k
eV, dose amount 5 × 10^Fifteencm^-2Arsenic ion as
Injection was performed to form a light receiving portion and a charge discharging portion. Formed
The area of the light receiving part is 60 μm^TwoAnd the impurity concentration is 2 ×
10²⁰cm^-3Met. The light receiving unit and the charge discharging unit
Is formed in another region of the semiconductor substrate as shown in FIG.
Amplifier transistor and selection transistor,
It was electrically connected to the source voltage to obtain a solid-state imaging device.

In the above manufacturing method, the area of the portion of the bottom surface of the light receiving portion that is not in contact with the p-type well, that is, the junction area between the light receiving portion and the p ⁻ -type region is 60% of the area of the light receiving portion.
(Sample No. 5) and 80% (Sample No. 6) were adjusted to produce two types of solid-state imaging devices. These solid-state imaging device, the light receiving unit - were studied depletion width formed between the substrates, the light receiving portion -p in the substrate ^- inter type region (Fig. 3
A) was about 1.2 μm, and between the light receiving portion and the p-type well on the substrate surface (b in FIG. 3) was about 0.2 μm.

For each solid-state imaging device, the photodiode capacity and the incident light amount of 10 lux (color temperature 32
00K), the sample N
o. In Sample No. 5, the photodiode capacity was 20 fF and the output voltage was 95 mV. In No. 6, the photodiode capacity was 10 fF and the output voltage was 155 mV.
Note that the output voltage is determined by the capacitance of the amplifier transistor being 2f.
F, the power supply voltage was measured at 5.0 V.

(Comparative Example) A solid-state imaging device having a structure similar to that of FIG. 4 was obtained in the same manner as in Example 1 except that no p ⁻ type diffusion region was formed. When the width of the depletion layer formed between the light receiving portion and the substrate was examined, it was about 1.0 μm both inside the substrate and on the substrate surface. The photodiode capacity and the incident light amount of 10 lux (color temperature 320
When the output voltage with respect to 0K) was evaluated, the photodiode capacitance was 25 fF and the output voltage was 70 mV. Note that the output voltage is determined by the capacitance of the amplifier transistor being 2f.
F, the power supply voltage was measured at 5.0 V.

[0078]

As described above, according to the first solid-state imaging device of the present invention, the light receiving unit of the second conductivity type formed in the semiconductor substrate of the first conductivity type, and the light receiving unit is electrically connected to the light receiving unit. A plurality of pixels including an amplifier circuit that is electrically connected, and a width of a depletion layer formed at a junction between the light receiving unit and the semiconductor substrate is smaller than that of a region in contact with the semiconductor substrate surface. Is large in a region in the semiconductor substrate including at least a portion of the solid-state imaging device, so that a solid-state imaging device with high sensitivity and suppressed dark current can be provided.

According to the second solid-state imaging device of the present invention, the light-receiving portion of the second conductivity type formed in the semiconductor substrate of the first conductivity type and the amplifier circuit electrically connected to the light-receiving portion are provided. A plurality of pixels including the first conductive type diffusion region having a lower impurity concentration than the semiconductor substrate, or a region having an impurity concentration lower than the semiconductor substrate, By forming the diffusion region of the second conductivity type having a low concentration, a high-sensitivity solid-state imaging device can be obtained.

Further, according to the third solid-state imaging device of the present invention, the light receiving unit and the charge discharging unit of the second conductivity type formed in the semiconductor substrate of the first conductivity type; A plurality of pixels including a gate electrode formed on the semiconductor substrate with an insulating film between the unit and an amplifier circuit electrically connected to the light receiving unit; and the gate in the semiconductor substrate. By including a region located below the electrode, and so as to avoid a region in contact with at least a part of the bottom surface of the light receiving unit, by forming a diffusion region of the first conductivity type having a higher impurity concentration than the semiconductor substrate, A high-sensitivity solid-state imaging device can be obtained.

A first manufacturing method according to the present invention is directed to a method for manufacturing a semiconductor device, comprising: a pixel including a light-receiving portion of a second conductivity type formed in a semiconductor substrate of a first conductivity type; and an amplifier circuit electrically connected to the light-receiving portion. A method for manufacturing a plurality of arranged solid-state imaging devices, wherein the step of forming the light receiving unit and a region in the semiconductor substrate that contacts at least a part of the bottom surface of the light receiving unit have a lower impurity concentration than the semiconductor substrate. Forming a diffusion region of the first conductivity type or a diffusion region of the second conductivity type having an impurity concentration lower than that of the light receiving unit, whereby a high-sensitivity solid-state imaging device can be manufactured.

Further, the second manufacturing method of the present invention is characterized in that a light-receiving portion of the second conductivity type and a charge discharging portion formed in the semiconductor substrate of the first conductivity type, and the light-receiving portion and the charge discharging portion A method for manufacturing a solid-state imaging device in which a plurality of pixels including a gate electrode formed on a semiconductor substrate therebetween via an insulating film and an amplifier circuit electrically connected to the light receiving unit are arranged. A step of forming a gate electrode, a step of forming the light receiving portion and the charge discharging portion, and a region in the semiconductor substrate located below the gate electrode, and at least a part of a bottom surface of the light receiving portion Forming a diffusion region of the first conductivity type having a higher impurity concentration than the semiconductor substrate so as to avoid a region in contact with the semiconductor substrate, whereby a high-sensitivity solid-state imaging device can be manufactured.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a structure of one pixel of a solid-state imaging device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a structure of one pixel of a solid-state imaging device according to a second embodiment of the present invention.

FIG. 3 is a cross-sectional view illustrating a structure of one pixel of a solid-state imaging device according to a third embodiment of the present invention.

FIG. 4 is a cross-sectional view illustrating a structure of one pixel of a conventional solid-state imaging device.

[Explanation of symbols]

11, 21, 41 p-type semiconductor substrate 31 p ^- type semiconductor substrate 12, 22, 32, 42 light receiving portion 13 p ^- type diffusion region 23 n ^- type diffusion region 33 p-type well 14, 24, 34, 44 charge discharging portion 15, 25, 35, 45 Insulating film 16, 26, 36, 46 Gate electrode 17, 27, 37, 47 Depletion layer

Claims (14)

[Claims] 1. A solid-state imaging device in which a plurality of pixels including a light receiving unit of a second conductivity type formed in a semiconductor substrate of a first conductivity type and an amplifier circuit electrically connected to the light receiving unit are arranged. A width of a depletion layer formed at a junction between the light receiving unit and the semiconductor substrate is larger in a region in the semiconductor substrate including at least a part of a bottom surface of the light receiving unit than in a region in contact with a surface of the semiconductor substrate. A solid-state imaging device characterized by being large. 2. The semiconductor device according to claim 1, wherein a width of the depletion layer is 1.5 to 10 times a region in the semiconductor substrate including at least a part of the bottom surface of the light receiving portion, in a region in contact with the semiconductor surface. Solid-state imaging device. 3. A solid-state imaging device in which a plurality of pixels including a light receiving portion of a second conductivity type formed in a semiconductor substrate of a first conductivity type and an amplifier circuit electrically connected to the light receiving portion are arranged. A first conductive type diffusion region having an impurity concentration lower than that of the semiconductor substrate, or a first conductive type diffusion region having an impurity concentration lower than that of the semiconductor substrate, in a region in the semiconductor substrate contacting at least a part of a bottom surface of the light receiving portion. A solid-state imaging device comprising a diffusion region of two conductivity type. 4. The solid-state imaging device according to claim 3, wherein the diffusion region is formed so as to avoid a region on a surface of the semiconductor substrate that is in contact with the light receiving unit. 5. The solid-state imaging device according to claim 4, wherein the width of the diffusion region is 10% to 100% of the width of the light receiving unit. 6. A light receiving unit and a charge discharging unit of a second conductivity type formed in a semiconductor substrate of a first conductivity type, and an insulating film on the semiconductor substrate between the light receiving unit and the charge discharging unit. A solid-state imaging device in which a plurality of pixels including a gate electrode formed through a gate and an amplifier circuit electrically connected to the light receiving unit are arranged, wherein the solid-state imaging device is located in the semiconductor substrate below the gate electrode. A first conductivity type diffusion region having a higher impurity concentration than the semiconductor substrate is formed so as to include a region and avoid a region in contact with at least a part of the bottom surface of the light receiving unit. apparatus. 7. The solid-state imaging device according to claim 6, wherein the diffusion region is formed to include a region on the surface of the semiconductor substrate that is in contact with the light receiving unit. 8. The light-receiving portion is in contact with a bottom surface of the light-receiving portion, and the diffusion region is 10% to 100% of a formation width of the light-receiving portion.
The solid-state imaging device according to claim 7, wherein the solid-state imaging device is formed so as to avoid a region having a width. 9. A solid-state imaging device in which a plurality of pixels including a light receiving portion of a second conductivity type formed in a semiconductor substrate of a first conductivity type and an amplifier circuit electrically connected to the light receiving portion are arranged. A manufacturing method, wherein the step of forming the light receiving portion, and a first conductive type diffusion region having a lower impurity concentration than the semiconductor substrate, in a region in the semiconductor substrate contacting at least a part of a bottom surface of the light receiving portion; And forming a second conductivity type diffusion region having an impurity concentration lower than that of the light receiving portion. 10. The method of manufacturing a solid-state imaging device according to claim 9, wherein the diffusion region is formed so as to avoid a region on the surface of the semiconductor substrate that is in contact with the light receiving section. 11. The method for manufacturing a solid-state imaging device according to claim 10, wherein a formation width of the diffusion region is set to 10% to 100% of a formation width of the light receiving unit. 12. A light receiving unit and a charge discharging unit of a second conductivity type formed in a semiconductor substrate of a first conductivity type, and an insulating film on the semiconductor substrate between the light receiving unit and the charge discharging unit. A method of manufacturing a solid-state imaging device in which a plurality of pixels including a gate electrode formed through a light source and an amplifier circuit electrically connected to the light receiving unit are arranged, wherein the step of forming the gate electrode includes the steps of: Forming a portion and the charge discharging portion, including, in the semiconductor substrate, a region located below the gate electrode, and avoiding a region in contact with at least a part of the bottom surface of the light receiving portion. Forming a diffusion region of the first conductivity type having a higher impurity concentration than the substrate. 13. The method for manufacturing a solid-state imaging device according to claim 12, wherein the diffusion region is formed so as to include a region on the surface of the semiconductor substrate that is in contact with the light receiving section. 14. The light-receiving portion, wherein the diffusion region is in contact with the bottom surface of the light-receiving portion and has a width of 10 to 100 times the width of the light-receiving portion.
14. The device according to claim 13, wherein the region is formed so as to avoid a region having a width of 0.1%.
3. The solid-state imaging device according to item 1.