JP2000077642A - Solid-state image pickup element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve yield by allowing a control gate to supply a constant voltage to an amplifier from a control region so that the amplifier comes non- operation for a raw with the control gate in conductive state and to make the amplifier into operation through capacitive coupling between the control gate and the amplifier for a raw with the control gate in cut-off state. SOLUTION: A control region 4 is connected by control region wirings 24a-c for each raw, and the wirings is connected for all common connections, which is connected to a voltage VG. A control gate 5 is connected to control gate wiring 21a-c for each raw, and driven for each raw by pulses ϕRG1-3 transmitted from a vertical scan circuit 7. A transfer gate 3 and the control gate 5 constituting each pixel are P-channel type. Thus, related to ϕTG1-3 and ϕRG1-3, the corresponding transfer gate 3 or control gate 5 comes conductive when these pulses are at low level while coming to be cut-off state at high level. Other gate is N-channel type and comes to be conductive state when a corresponding pulse is high level. While being cut-off state at low level.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device, and more particularly, to a large number of pixels each having an amplifier for outputting a signal corresponding to incident light and a controller for controlling the amplifier. The present invention relates to an amplification type solid-state imaging device.

[0002]

2. Description of the Related Art Conventionally, an amplification type solid-state imaging device has been proposed which amplifies a signal generated in each pixel in response to incident light inside the pixel and then outputs the amplified signal. FIG. 19 is a circuit diagram showing a main configuration of a conventional solid-state imaging device. A conventional solid-state imaging device includes a plurality of pixels Px arranged in a two-dimensional matrix.
1-1 to Px3-4 and each pixel Px1-1 to Px3-4
And a pixel Px1-1 for driving each pixel Px1-1
To Px3-4 are connected for each column.
2d, a horizontal signal line 27, and a horizontal scanning circuit 8.

Each pixel includes a photodiode 1 that generates and accumulates a charge corresponding to incident light, and a junction field-effect transistor (hereinafter, referred to as “hereafter”) that outputs a signal corresponding to the charge from a source (S) by a source follower operation. JFET)
2, a transfer gate 3 for transferring the charge from the photodiode 1 to the JFET 2, a control region 4 for controlling the JFET 2, and a control gate 5.

The source (S) of each JFET 2 is connected to the vertical signal lines 22a to 22d for each column, and the drain (D) of each JFET 2 is commonly connected to a drain power supply VD for all pixels. The transfer gate 3 is connected to the transfer gate wirings 20a to 20c for each row, and is driven for each row by pulses φTG1 to φTG3 sent from the vertical scanning circuit 7.

[0005] The control region 4 includes a control region wiring 24 for each row.
a to 24c, and is driven for each row by pulses φRD1 to φRD3 sent from the vertical scanning circuit 7. The control gates 5 are connected on a row-by-row basis by control gate wirings 21a to 21c, and are further commonly connected by connecting these wirings, and are driven by a drive pulse φRG.

The vertical signal lines 22a to 22d have JFETs
2; constant current sources 26a to 26d serving as loads; reset transistors TRV1 to TRV4 for fixing a vertical signal line to a constant voltage (VRV); and vertical load capacitors Cv1 to Cv4 for limiting the operation band of JFET2. , Column buffer amplifiers 29a to 29d, and clamp capacitors Cc1 to
Cc4 is connected to the clamp transistors TC1 to TC4. The vertical signal lines 22a to 22d are connected to the horizontal signal line 27 via the column selection transistors TH1 to TH4.

[0007] An output buffer amplifier 28 and a reset transistor TRH are connected to the horizontal signal line 27.
FIG. 20 is a pulse timing chart for explaining the operation of the circuit diagram shown in FIG. The operation of the conventional solid-state imaging device will be described with reference to FIG. Since the transfer gate 3 and the control gate 5 constituting each pixel are of a P-channel type (see FIGS. 22 and 23) as will be described later, the conduction (ON) state is established when the pulse applied to these is at a low level. When these pulses are at the high level, they are cut off (off).

In FIG. 20, a period from t11 to t15 corresponds to the readout operation of the pixels in the first row.
Hereinafter, the periods t21 to t25 and t31 to t35 correspond to the second and third rows, respectively. First, the period t
In step 11, φRG is set to low level, and the control gates 5 of all the pixels are turned on. Further, the drive pulse φRD1 is set to a high level (φRD2 and φRD3 are kept at a low level), and a high-level voltage is applied from the control region 4 to the gate region of the JFET2 of the pixel in the first row via the control gate 5. A low-level voltage is supplied to the gate regions of the JFET2 in the second and subsequent rows. That is, a high-level voltage is supplied to the gate region of the JFET 2 in the first row via the control region 4 to bring the JFET 2 into an operating (selected) state. In addition, a low-level voltage is supplied to the gate region of the JFET 2 in the second and subsequent rows via the control region 4 so that the JFET 2 is in a non-operating (non-selected) state.

At the end of the period t11, the drive pulse φRG is set to the high level, and the control gates 5 of all the pixels are set.
Is turned off (off), JFET2 in the first row is in the operating (selected) state, and JFET2 in the second and subsequent rows are in the floating state while maintaining the non-operating (non-selected) state. That is, in the period t11, the row selection operation and the JFET2
Is performed.

In the period t12, the driving pulse φRV
To low level, and reset transistors TRV1 to TRV1
TRV4 is turned off (off), and the first row JFET
2 performs a source follower operation. Therefore, an output (dark output) voltage corresponding to the potential immediately after the initialization of the gate region of JFET2 is supplied from the source (S) of JFET2 to the clamp capacitor Cc1 via the vertical signal lines 22a to 22d and the column buffer amplifiers 29a to 29d. To Cc4 (vertical signal line 2)
2a to 22d sides, hereinafter referred to as input terminals). The drive pulse φC is at a high level, the clamp transistors TC1 to TC4 are in a conductive (on) state, and the other ends of the clamp capacitors Cc1 to Cc4 (on the horizontal signal line 27 side,
Hereinafter referred to as an output terminal) is a ground potential.

At the end of the period t12, the driving pulse φC is set to the low level to set the clamp transistors TC1 to TC1.
When the TC4 is turned off (off), the output terminals of the clamp capacitors Cc1 to Cc4 enter a floating state while the output (dark output) voltage is held in the clamp capacitors Cc1 to Cc4. That is, the clamp operation of the dark output voltage is performed.

In period t13, drive pulse φTG
1 to a low level (the drive pulses φTG2 and φTG3 remain at a high level) to make the transfer gate 3 of the pixel in the first row conductive (on), and the photodiode 1 in the first row
The signal charge generated and stored in step (1) is transferred to the gate region of JFET2. Note that JFET2 after transferring the signal charge
Of the gate region changes by the amount of signal charge / gate capacitance (in this case, rises).

At the end of period t13, drive pulse φTG
When the transfer gate 3 is cut off (turned off) by setting 1 to a high level, the photodiode 1 in the first row starts the next signal charge accumulation operation by photoelectric conversion. In FIG. 20, t
LI indicates the charge accumulation time of the photodiode 1. In the period t14, similarly to the period t12, the drive pulse φRV is set to the low level, the reset transistors TRV1 to TRV4 are turned off (off), and the JFET2 in the first row performs a source follower operation. Next time,
An output (signal output) voltage corresponding to the potential after transferring the signal charge to the gate region of JFET 2 is supplied from the source (S) of JFET 2 via vertical signal lines 22a to 22d and column buffer amplifiers 29a to 29d to clamp capacitor Cc1. ~ Cc
4 is applied to the input terminal.

At this time, the voltage at the output terminals of the clamp capacitors Cc1 to Cc4 is equal to JF after the signal charge transfer in the period t14.
The output (signal output) voltage by the source follower operation of ET2 is a voltage obtained by subtracting the output (dark output) voltage of the JFET 2 by the source follower operation before charge transfer (after the gate region initialization) in the period t12. Period t14
The output (signal output) voltage of the source follower operation of the JFET 2 includes the optical signal component and the noise component, and the output (dark output) voltage of the source follower operation of the JFET 2 during the period t12 includes only the noise component. Have been. Therefore, the voltages at the output terminals of the clamp capacitors Cc1 to Cc4 obtained by subtracting the two (so-called correlated double sampling processing) become output voltages corresponding to only the optical signal components.

As noise components included in both, each J
Fixed pattern noise due to variation in threshold voltage of FET2, JFET from control region 4 through control gate 5
Reset noise generated when the gate region 2 is initialized, 1 / f noise generated when the source follower is operated by the JFET 2 and the constant current sources (26a to 26d), and fixed pattern due to variation in offset voltage of the column buffer amplifiers 29a to 29d. There is noise.

That is, the clamp capacitance C during the period t14
The voltages at the output terminals of c1 to Cc4 become video signals of only the optical signal components from which the noise components have been removed, and the S / N ratio is improved. In the period t15, the driving pulses φH1 to φH4 are sequentially output from the horizontal scanning circuit 8 to transfer the output voltage corresponding to only the optical signal components appearing at the output terminals of the clamp capacitors Cc1 to Cc4 to the horizontal signal line 27. Then, a video signal is output from the output terminal 35 via the output buffer amplifier 28. The horizontal signal line 27 is reset by sequentially outputting the drive pulse φRH.

The reading operation of the first row for the periods t11 to t15 includes the periods t21 to t25 and the period t31.
In the period t35, the same operation is repeated for the second and third rows, respectively. Next, a pixel structure of a conventional solid-state imaging device will be described with reference to the drawings. FIG.
FIG. 1 is a plan view of a pixel of a conventional solid-state imaging device.
FIG. 23 is a sectional view taken along line Xa-Xb in FIG. 21, and FIG.
FIG. 24 is a sectional view taken along line Ya-Yb of FIG.
It is sectional drawing along the c-Yd line.

The pixels of the conventional solid-state imaging device include a photodiode 1, a JFET 2, a transfer gate 3, a control region 4, and a control gate 5. Photodiode 1
Is a P-type semiconductor substrate 10 as shown in FIGS.
It comprises an N-type well region 11, a P-type charge accumulation region 12, and a high-concentration N-type semiconductor region 13 formed thereon. As a result, a buried photodiode having an NPNP type vertical overflow drain structure is formed. That is, embedded photodiodes (N, P,
N) and vertical overflow drain structure (P, N, P)
Are formed. With this structure,
Dark current, afterimages, reset noise, blooming, and smear are suppressed.

The JFET 2 is of an N-channel type, as shown in FIG.
2, as shown in FIG. 23, it is composed of an N-type source region 14, a P-type gate region 15, an N-type drain region 16, and an N-type channel region 17. The N-type source region 14 includes a vertical signal line 22 (vertical signal lines 22a to 22 in FIG. 19) for each column.
(corresponding to d) (see FIGS. 21 and 22). The N-type drain region 16 is continuously formed in a mesh shape so as to surround the periphery of the pixel, and is commonly connected to the drain power supply VD around the pixel region (a region where a plurality of pixels are arranged in a matrix). Connected (see FIG. 19).

As shown in FIG. 23, the transfer gate 3 has an insulating film 3 on the boundary region between the photodiode 1 and the JFET 2.
3 are formed. The P-type charge accumulation region 12 of the photodiode 1 and the P-type gate region 15 of the JFET 2 are used as source or drain regions,
Is formed as a gate electrode. The transfer gate 3, as shown in FIG.
The transfer gate lines 20 (the transfer gate lines 20a to 20
20c).

The P-type control region 4 is formed in the N-type well region 11 as shown in FIGS. 21 and 22, and is connected to the control region wiring 24 (corresponding to the control region wirings 24a to 24c in FIG. 19). Have been. The control region wiring 24 also serves as a light shielding film for shielding the region other than the photodiode 1 from light. The control gate 5, as shown in FIG.
And a P-type control region 4 with an insulating film 33 interposed therebetween. Then, the P-type gate region 1 of JFET2
5 and the P-type control region 4 as source or drain regions,
A P-channel MOS transistor having the control gate 5 as a gate electrode is configured. The control gate 5 is connected to a control gate line 21 (corresponding to the control gate lines 21a to 21c in FIG. 19) as shown in FIG.

As described above, pixels having the photodiode 1, the JFET 2, the transfer gate 3, the control region 4, and the control gate 5 are arranged in a matrix in FIG.
The conventional solid-state imaging device shown in FIG. 24 employs a vertical overflow drain structure and a buried photodiode 1, so that dark current, afterimage, reset noise, blooming, and smear are suppressed. Load capacity Cv
The noise at the time of the amplification operation is suppressed by the narrow-band source follower operation of the JFET 2 with the load of 1 to Cv4.
Further, the output voltage of each source follower operation before and after the signal charge transfer is subtracted (correlated double sampling process) via the clamp capacitors Cc1 to Cc4, thereby fixing the output voltage due to the variation in the threshold voltage of JFET2. Pattern noise, reset noise generated when the gate region of JFET 2 is initialized, 1 / f noise during source follower operation, and fixed pattern noise due to variations in offset voltages of column buffer amplifiers 29a to 29d are suppressed. Therefore, a video signal with high sensitivity and low noise (high S / N ratio) can be obtained.

[0023]

However, the conventional solid-state imaging device has the above-mentioned excellent effects, but has a problem in that the production yield is low.
Further, in the conventional solid-state imaging device, when optical black (optical black portion: a plurality of pixel portions including the light-shielded photodiode 1) is formed, a light-shielding film must be additionally formed, and the number of manufacturing steps is reduced. It has increased. For this reason, there are also problems that the manufacturing cost increases with the increase in the number of manufacturing steps and the yield further decreases.

The present invention has been made in view of the above problems, and has as its object to provide a solid-state imaging device having a high production yield. Further, another object of the present invention is to provide an optical black without increasing the number of manufacturing steps.
An object of the present invention is to provide a solid-state imaging device that can form a solid-state imaging device.

[0025]

The inventor of the present invention has found that the cause of the reduction in the manufacturing yield is a short circuit between wirings for supplying a voltage to the control region (control region wirings). As shown in FIGS. 21 and 22, the control region 4 of each pixel
Are the control region wirings 24 (the control region wirings 24a to 24a to
24c), they are commonly connected in the row direction and are connected to the vertical scanning circuit 7. Each row is driven by pulses φRD1 to φRD3 sent from the vertical scanning circuit 7 (see FIG. 19). The control region wiring 24 also serves as a light-shielding film that shields a region other than the photodiode 1 and is formed in parallel with each other in the row direction at a relatively narrow interval as compared with other intervals.

For this reason, in the step of forming the control region wiring 24 (the step of depositing the wiring metal film and the step of photolithography / etching), if a particle having a size equal to or larger than the wiring interval adheres, the particle passes through the particle. Two adjacent wires were short-circuited, and the manufacturing yield was reduced. The solid-state imaging device according to claim 1, wherein the amplifying unit outputs a signal corresponding to incident light, a control region that controls the amplifying unit, and control that controls an electrical connection state between the amplifying unit and the control region. A solid-state imaging device in which a plurality of pixels each including a gate are arranged, wherein each of the control regions is connected to a power supply in common, the control gate is driven by a pulse voltage for each row, and the control gate is turned on by the pulse voltage. In the row in the state, a constant voltage is supplied to the amplifying unit from the control region, the amplifying unit becomes inactive, and in the row in which the control gate is cut off by the pulse voltage, the amplifying unit is used. And the control region is electrically cut off, and the amplifying unit is activated by capacitive coupling between the control gate and the amplifying unit.

According to this configuration, since the control regions of the respective pixels are connected in common, the problem that the wirings connecting the control regions are short-circuited to each other is eliminated, and the manufacturing yield is accordingly improved. In addition, the wiring connecting the control regions can be used as a light-shielding film for the entire pixel, and optical black (optical black portion) can be formed without increasing the number of manufacturing steps.

Further, according to the first aspect of the present invention, it is possible to select a row using capacitive coupling, thereby reducing the number of drive pulses (input pulses to the image sensor) and simplifying the vertical scanning circuit of the image sensor. It is possible to do. According to a second aspect of the present invention, there is provided the solid-state imaging device according to the first aspect, wherein the MOS transistor has the control gate as a gate electrode and the control region as one of a source and a drain. The amplifying unit is a field-effect transistor, the gate of which is connected to the other of the source and the drain of the MOS transistor, and the source and the drain of the MOS transistor are the source and the drain of the field-effect transistor. And the opposite conductivity type. According to a third aspect of the present invention, there is provided the solid-state imaging device according to the first aspect, wherein the MOS-type transistor includes the control gate as a gate electrode and the control region as one of a source and a drain. The amplifying section is a junction field effect transistor, the gate of which is connected to the other of the source and the drain of the MOS transistor, and the gate of the junction field effect transistor is the source and drain of the MOS transistor. And the same conductivity type.

These claims show the configuration of the present invention more specifically, and claim 2 is that a field-effect transistor is arranged in the amplifying section. According to a third aspect of the present invention, a junction field-effect transistor is disposed in the amplification section. According to a fourth aspect of the present invention, in the solid-state imaging device according to the third aspect, the other of the gate of the junction field-effect transistor and the source or the drain of the MOS transistor is the same semiconductor region. It is characterized by the following.

With this configuration, the wiring and the diffusion region connected to the gate of the junction field effect transistor can be reduced. For this reason, the parasitic capacitance caused by these wirings and diffusion regions is reduced, and the output signal is increased. Further, since the size can be further reduced, the aperture ratio is improved. According to a fifth aspect of the present invention, in the solid-state imaging device according to the first aspect, a MOS transistor is provided in which the control gate is a gate electrode and the control region is one of a source and a drain. The amplifying unit is a bipolar transistor, the base of which is connected to the other of the source and the drain of the MOS transistor;
The base of the bipolar transistor has the same conductivity type as the source and the drain of the MOS transistor.

This claim shows the configuration of the present invention more specifically, wherein a bipolar transistor is arranged in the amplifying section. The solid-state imaging device according to claim 6 is the solid-state imaging device according to claim 5, wherein the other of the base of the bipolar transistor and the source or the drain of the MOS transistor is the same semiconductor region. And With this configuration, the wiring and the diffusion region connected to the base of the bipolar transistor are reduced. For this reason, the parasitic capacitance caused by these wirings and diffusion regions is reduced, and the output signal is increased.
Further, since the size can be further reduced, the aperture ratio is improved.

[0032]

Embodiments of the present invention will be described below with reference to the drawings. In each of the drawings, the same reference numerals indicate the same or corresponding portions, and duplicate description will be omitted. [Embodiment 1] FIG. 1 is a circuit diagram showing a configuration of a solid-state imaging device according to Embodiment 1 of the present invention. The solid-state imaging device according to the first embodiment includes a plurality of pixels Px1-1 to Px3-4 arranged in a two-dimensional matrix and each of the pixels Px1-1 to Px
3-4 for each row, and a pixel Px
Vertical signal line 22 in which 1-1 to Px3-4 are connected for each column
a to 22d, a horizontal signal line 27, and a horizontal scanning circuit 8.

Each pixel, for example, Px1-1, has a photodiode 1 that generates and accumulates a charge corresponding to incident light, and an N-channel type that outputs a signal corresponding to the charge from a source (S) by a source follower operation. , A transfer gate 3 for transferring the charge from the photodiode 1 to the JFET 2, a control region 4 for controlling the JFET 2, and a control gate 5.
It is composed of

The source (S) of each JFET 2 is connected to the vertical signal lines 22a to 22d for each column, and the drain (D) of each JFET 2 is connected to a drain power supply VD common to all pixels. The transfer gate 3 is connected to the transfer gate wirings 20a to 20c for each row, and is driven for each row by pulses φTG1 to φTG3 sent from the vertical scanning circuit 7.

The control area 4 includes control area wirings 24a to 24a.
The connection is made for each row by c, and by connecting these wirings, they are all connected in common and connected to a power supply (voltage VG). The control gate 5 is connected to the control gate lines 21a to 21c for each row, and is driven for each row by pulses φRG1 to φRG3 sent from the vertical scanning circuit 7.

JFETs are connected to the vertical signal lines 22a to 22d.
2; constant current sources 26a to 26d serving as loads; reset transistors TRV1 to TRV4 for fixing a vertical signal line to a constant voltage (VRV); and vertical load capacitors Cv1 to Cv4 for limiting the operation band of JFET2. , Column buffer amplifiers 29a to 29d, and clamp capacitors Cc1 to
Cc4 is connected to the clamp transistors TC1 to TC4. The vertical signal lines 22a to 22d are connected to the horizontal signal line 27 via the column selection transistors TH1 to TH4.

The output buffer amplifier 28 and the horizontal signal line 27 are connected to the horizontal signal line 27 at a constant voltage (here, GND).
Is connected to the reset transistor TRH. FIG. 2 is a pulse timing chart for explaining the operation of the solid-state imaging device according to the first embodiment. The operation of the solid-state imaging device according to the first embodiment shown in FIG. 1 will be described with reference to FIG. As will be described later, the transfer gate 3 and the control gate 5 constituting each pixel are of a P-channel type (see FIGS. 5 and 6). Therefore, φTG1 to φTG
3 and φRG1 to φRG3 correspond to the transfer gate 3 or the control gate 5 when these pulses are at the low level.
Are turned on, and when these pulses are at a high level, they are turned off (off). The other gates are of the N-channel type, and are turned on when the corresponding pulse is at a high level, and are turned off when the corresponding pulse is at a low level.
State.

In FIG. 2, the period from t11 to t15 corresponds to the readout operation of the pixels in the first row. Hereinafter, the periods from t21 to t25 and t31 to t35 correspond to the second row and the third row, respectively. Corresponds to the line. First, period t1
In 1, the control signals φRG1 to φRG3 are at the low level, and the control gates 5 of all the pixels are conductive (ON). Therefore, the gate regions of the JFETs 2 of all the pixels are initialized by applying the voltage VG from the control region 4 via the control gate 5.

At the end of the period t11, the driving pulse φRG1 is set to the high level (the driving pulses φRG2, φRG3
Remains at low level), and the control gate 5 of the first row is turned off (off). When this operation is performed, the potential of the gate region of JFET2 in the first row rises due to capacitive coupling between the control gate 5 and the gate region of JFET2, and VG
+ ΔVG (the amount of change is assumed to be ΔVG). The JFET 2 in the first row has a gate region in a floating state and a gate voltage (accurately, a gate-source voltage).
Rises above the other rows to enter the operating (selected) state.

On the other hand, the control gates 5 in the second and subsequent rows are conducting (on), and the gate region of JFET 2 is
G remains applied. Therefore, JF after the second line
Gate voltage of ET2 (more precisely, gate-source voltage)
Is lower than the gate voltage in the first row. Therefore, the JFETs 2 in the second and subsequent rows remain in a non-operating (non-selected) state.

Here, the row selecting operation in the period t11 will be described in more detail. 3A and 3B are explanatory diagrams of a row selection operation of the solid-state imaging device according to the first embodiment. FIG. 3A is an equivalent circuit diagram of a pixel, and FIG. 3B is a diagram illustrating a voltage applied to a control gate 5 and JFET2.
FIG. 5 is a potential diagram showing a change in a gate voltage of FIG. As shown in the equivalent circuit diagram of FIG. 3A, the pixel of the solid-state imaging device according to the first embodiment includes a photodiode 1, a JFET 2, a transfer gate 3, a control region 4, and a control gate 5. Is applied with a constant voltage (VG). And
A gate region (G) of JFET2 and four adjacent regions (see FIGS. 4 to 7 described later), that is, a source region (S),
CGS, CGD, CG (TG), and CGS are provided between the drain region (D), the transfer gate 3, and the control gate 5, respectively.
There is a capacity of G (RG).

As shown in FIG. 3B, the P-channel type control gate 5 is changed from the conductive (ON) state to the cut-off (OFF) state, that is, the drive pulse φRG is changed from the low level (VRGL) to the high level. In the process of changing to the level (VRGH), the gate region (G) of the JFET 2 becomes electrically floating, and at the same time, the gate voltage increases by ΔVG due to capacitive coupling, and becomes VG + ΔVG. Although the amount of change ΔVG of the voltage is shown as Expression (1) in FIG. 3, the amplitude of the drive pulse φRG (for details, see FIG.
(VRGH-VT value of (b)) and the capacitance ratio CG (RG) /
Determined by the product of CG (total). VT is the threshold voltage of the control gate 5, and CG (total) is the total capacitance of the four capacitance components (formula (2)).

As described above, the value of ΔVG can be appropriately selected according to the equation (1) in FIG. In this way, when the P-channel type control gate 5 changes from the conductive state to the cut-off state, the N-channel type JFET 2
Changes from the non-operation state to the operation state. On the other hand, when the P-channel type control gate 5 continues to be conductive (on), that is, when the drive pulse φRG is at the low level (VRG
If the voltage remains at L), the voltage of the gate region (G) of JFET2 does not change from VG. Therefore, JFET2 remains in the non-selected state.

Therefore, the amplitude of the φRG pulse and the capacitance ratio CG
(RG) / CG (total) (changes depending on the pixel structure and operating point) is appropriately selected, and JFET2
The row selection operation can be performed by setting the amount of change ΔVG of the gate voltage to an appropriate value. In the period t11 of the timing chart of FIG.
Row selection operation. That is, JFE on the first line
In T2, the gate region becomes floating and the gate voltage becomes VG + ΔVG, and the JFETs in the second and subsequent rows
2, the gate voltage is fixed to the power supply voltage VG. Since the source regions (S) of the respective JFETs 2 arranged in the column direction are commonly connected by the vertical signal lines 22a to 22b,
JFET2 in first row with large gate-source voltage
Is in an operation (selected) state, and the JFETs 2 in the second and subsequent rows having a small gate-source voltage are in a non-operation (non-selected) state. In this embodiment, VRGH-VT is set to 7
V and ΔVG were set to 0.7V.

In the period t11, the drive pulse φRV is set to the high level to reset the reset transistors TRV1 to TRV1.
V4 is turned on. As a result, the voltages of the vertical signal lines 22a to 22d are fixed at a constant value (VRV). This is to ensure that the above-described row selection operation is performed, that is, to assist the row selection operation. However, ΔVG
It is not always necessary if J is large and the row selection operation of the JFET is easy. The case where ΔVG is large is expressed by equation (1)
As can be understood from the above, when VRGH-VT is large, or when CG (RG) / CG (total) is large.

Returning to FIG. In the period t12, the drive pulse φRV is set to low level, the reset transistors TRV1 to TRV4 are turned off (off), and the JFET2 in the first row performs a source follower operation. Therefore, an output (dark output) voltage corresponding to the potential immediately after the initialization of the gate region of JFET2 is supplied from the source (S) of JFET2 to the clamp capacitor Cc1 via the vertical signal lines 22a to 22d and the column buffer amplifiers 29a to 29d. ~ C
It is applied to one end of c4 (on the side of the vertical signal lines 22a to 22d, hereinafter referred to as an input end). The drive pulse φC is at a high level, the clamp transistors TC1 to TC4 are in a conductive (on) state, and the other ends of the clamp capacitors Cc1 to Cc4 (the horizontal signal line 27 side, hereinafter referred to as output terminals).
Is the ground potential.

At the end of the period t12, the driving pulse φC is set to the low level to set the clamp transistors TC1 to TC1.
When the TC4 is turned off (off), the output terminals of the clamp capacitors Cc1 to Cc4 enter a floating state while the output (dark output) voltage is held in the clamp capacitors Cc1 to Cc4. That is, the clamp operation of the dark output voltage is performed.

In the period t13, the driving pulse φTG
1 to a low level (the drive pulses φTG2 and φTG3 remain at a high level) to make the transfer gate 3 of the pixel in the first row conductive (on), and the photodiode 1 in the first row
The signal charge generated and stored in step (1) is transferred to the gate region of JFET2. Note that JFET2 after transferring the signal charge
Of the gate region changes by the amount of signal charge / gate capacitance (in this case, rises).

At the end of period t13, drive pulse φTG
When the transfer gate 3 is cut off (turned off) by setting 1 to a high level, the photodiode 1 in the first row starts the next signal charge accumulation operation by photoelectric conversion. In FIG. 2, tL
I indicates the charge storage time of the photodiode 1.
In the period t13, similarly to the period t11, the drive pulse φRV is set to the high level to reset the reset transistor TR.
V1 to TRV4 are turned on (on). This is to ensure that the transfer operation described above is performed, that is, to assist the transfer operation. This makes it easier for the signal charge to be completely transferred from the photodiode 1 to the JFET 2. However, depending on conditions such as the area of the photodiode 1 and the impurity concentration, when complete transfer is performed without using the reset transistors TRV1 to TRV4, these transistors are unnecessary. Therefore, the period t11 and the period t1
3 and the associated reset transistor T
When the operations of RV1 to TRV4 are both unnecessary, the solid-state imaging device according to the first embodiment includes the driving pulse φRV, the reset transistors TRV1 to TRV4, and the power supply shown in the circuit diagram (FIG. 1) and the timing chart (FIG. 2). (VR
V) may be deleted.

In the period t14, similarly to the period t12, the drive pulse φRV is set to the low level, the reset transistors TRV1 to TRV4 are turned off, and the JFET2 in the first row performs a source follower operation. This time, the output (signal output) voltage corresponding to the potential after transferring the signal charge to the gate region of JFET2 is JF
From the source (S) of ET2 to the vertical signal lines 22a to 22d,
The voltage is applied to the input terminals of the clamp capacitors Cc1 to Cc4 via the column buffer amplifiers 29a to 29d.

At this time, the voltages at the output terminals of the clamp capacitors Cc1 to Cc4 are equal to JF after the signal charge transfer in the period t14.
The output (signal output) voltage by the source follower operation of ET2 is a voltage obtained by subtracting the output (dark output) voltage of the JFET 2 by the source follower operation before charge transfer (after the gate region initialization) in the period t12. Period t14
The output (signal output) voltage of the source follower operation of the JFET 2 includes the optical signal component and the noise component, and the output (dark output) voltage of the source follower operation of the JFET 2 during the period t12 includes only the noise component. Have been. Therefore, the voltages at the output terminals of the clamp capacitors Cc1 to Cc4 obtained by subtracting the two (so-called correlated double sampling processing) become output voltages corresponding to only the optical signal components.

As noise components included in both, each J
Fixed pattern noise due to variation in threshold voltage of FET2, JFET from control region 4 through control gate 5
Reset noise generated when the gate region 2 is initialized, 1 / f noise generated when the source follower is operated by the JFET 2 and the constant current sources (26a to 26d), and fixed pattern due to variation in offset voltage of the column buffer amplifiers 29a to 29d. There is noise.

That is, the clamp capacitance C during the period t14
The voltages at the output terminals of c1 to Cc4 become video signals of only the optical signal components from which the noise components have been removed, and the S / N ratio is improved. In the period t15, the driving pulses φH1 to φH4 are sequentially output from the horizontal scanning circuit 8 to transfer the output voltage corresponding to only the optical signal components appearing at the output terminals of the clamp capacitors Cc1 to Cc4 to the horizontal signal line 27. Then, a video signal is output from the output terminal 35 via the output buffer amplifier 28. The horizontal signal line 27 is reset by sequentially outputting the drive pulse φRH. Note that the period t
The source follower operation in 14 continues even in the period t15.

The periods t11 to t14 are performed during the horizontal retrace period. The reading operation of the first row for the periods t11 to t15 is performed in the second row and the third row in the periods t21 to t25 and the periods t31 to t35, respectively.
Repeat for the row, and so on. As described above, the row selection operation of the solid-state imaging device according to the first embodiment can be summarized as follows. 1. The source of the JFET 2 of each pixel is connected to the same constant current source for each column, and operates as a source follower. JFET2
Are the same for each column. 2. On the other hand, among the rows, a row having a large gate-source voltage of JFET2 is selected, and a signal is output from JFET2 of the row. 3. The control gate 5 is connected and operates for each row. In the row where the control gate 5 is turned on, the gate voltage of the JFET 2 becomes VG. In the row where the control gate 5 is turned off, the gate voltage of JFET 2 is VG + Δ due to capacitive coupling.
VG. 4. Therefore, when the source follower operation is performed on the JFET 2, a signal is output from the row in which the control gate 5 is turned off. That is, a row can be selected.

As described above, according to the present invention, not only the yield can be improved, but also the row selection can be performed by skillfully utilizing the capacitive coupling. Therefore, the number of drive pulses (input pulses to the image sensor) is reduced, and the vertical scanning circuit of the image sensor is simplified. Further, the driving timing is simplified, and the operation speed is improved. Further, since the difference between the gate voltage or the base voltage of the selected pixel and the non-selected pixel can be set smaller than before, the transfer characteristics (afterimage characteristics) and the saturated charge amount (overflow characteristics) are improved. Further, the low-level voltage value of the pulse voltage (φRG) of the control gate 5 increases, so that the driving voltage of the device as a whole can be reduced.

Next, the pixel structure of the solid-state imaging device according to the first embodiment will be described. 4 is a plan view of a pixel of the solid-state imaging device according to the present embodiment, FIG. 5 is a cross-sectional view along line X1-X2, FIG. 6 is a cross-sectional view along line Y1-Y2,
FIG. 7 is a sectional view taken along the line Y3-Y4. The pixels of the solid-state imaging device according to the first embodiment are photodiodes 1 and J
It comprises an FET 2, a transfer gate 3, a control region 4, and a control gate 5.

As shown in FIGS. 6 and 7, the photodiode 1 includes an N-type well region 11, a P-type charge accumulation region 12, and a high-concentration N-type semiconductor region 13 formed on a P-type semiconductor substrate 10. Be composed. As a result, a buried photodiode having a vertical overflow drain structure of the NPNP type is formed. That is, a structure in which the embedded photodiode (N, P, N) and the vertical overflow drain structure (P, N, P) are combined is formed.
With this structure, dark current, afterimage, reset noise, blooming, and smear are suppressed.

The JFET 2 is of an N-channel type, as shown in FIG.
As shown in FIG. 6, an N-type source region 14, a P-type gate region 15, an N-type drain region 16, and an N-type channel region 17 are provided.
It is composed of The N-type source region 14 is connected to a vertical signal line 22 (corresponding to the vertical signal lines 22a to 22d in FIG. 1) for each column (see FIGS. 4 and 5). The N-type drain region 16 is continuously formed in a mesh shape so as to surround the periphery of the pixel, and is commonly connected to the drain power supply VD around the pixel region (a region where a plurality of pixels are arranged in a matrix). Connected (see FIG. 1). Transfer gate 3
Is, as shown in FIG. 6, a photodiode 1 and a JFET
2 is formed on the boundary region 2 with an insulating film 33 interposed therebetween.
Then, a P-channel MOS transistor is configured in which the P-type charge storage region 12 of the photodiode 1 and the P-type gate region 15 of the JFET 2 are used as a source or drain region, and the transfer gate 3 is used as a gate electrode. Transfer gate 3
Are connected to the transfer gate wiring 20 (corresponding to the transfer gate wirings 20a to 20c in FIG. 1), as shown in FIG.

The P-type control region 4 is formed in the N-type well region 11 as shown in FIGS.
4 (corresponding to the control area wirings 24a to 24c in FIG. 1). The interval between the control region wirings 24 is the same as in the related art. However, as is clear from FIG. 1, all the control region wirings of the present invention are commonly connected. Therefore, even if particles adhere between the control region wirings, the same voltage is applied to all the control region wirings, so that no defect occurs. Therefore, the yield is improved.

The control region wiring 24 also serves as a light shielding film for shielding the region other than the photodiode 1 from light.
As shown in FIG. 5, the control gate 5 is formed on a boundary region between the JFET 2 and the P-type control region 4 via an insulating film 33. Then, a P-channel MOS transistor having the control gate 5 as a gate electrode, the P-type control region 4 as one of the source and drain regions, and the P-type gate region 15 of the JFET 2 as the other of the source and drain regions is formed. I have. As shown in FIG. 4, the control gate 5 is connected to the control gate line 21 (the control gate line 21a of FIG. 1).
To 21c). Also, as is apparent from FIG. 1, the control gates are connected for each row and are driven for each row. Therefore, the above-described row selection operation can be performed.

The source / drain of the P-channel MOS transistor (that is, the control region 4 and the gate region 15 of the JFET 2) is a P-type semiconductor region. Meanwhile, JFE
The source / drain of T2 is of the opposite conductivity type (ie, N-type semiconductor region). The gate of JFET2 is of the same conductivity type (P-type semiconductor region) as the source and drain of the P-channel MOS transistor. As described above, if the conductivity type of each semiconductor region is selected, the gate voltage of JFET2 is reduced by turning off the control gate, and ΔV
Increase by G. Therefore, the above-described row selection operation can be performed.

The P-type gate region 15 of the JFET 2
And the other of the source and drain regions of the P-channel MOS transistor is the same semiconductor region. By doing so, it is possible to delete unnecessary wirings and diffusion regions. For this reason, not only the parasitic capacitance becomes smaller and the output signal increases, but also miniaturization becomes possible. Finally, the structure of the optical black (optical black portion) will be described with reference to FIG.

FIG. 8 is a partial plan view showing a boundary region between pixels constituting an image pickup section of the solid-state image pickup device of Embodiment 1 and pixels constituting an optical black (optical black portion). Then, as shown in the right end of FIG. 8, the pixels of the optical black (the pixels of the OB section) are
Is shielded by light. That is, in the solid-state imaging device according to the first embodiment, since the control region 4 of each pixel is connected in common, the control region wiring 24 can be provided without newly adding a light shielding film.
Accordingly, the entire pixel including the photodiode 1 can be shielded from light.

As described above, the solid-state imaging device according to the first embodiment employs the vertical type overflow drain structure and the buried photodiode 1, so that the dark current, the afterimage, the reset noise, the blooming, the smearing, and the like. In addition, the noise during the amplification operation is suppressed by the narrow-band source follower operation of the JFET 2 with the vertical load capacitors Cv1 to Cv4 as loads. Further, the output voltage of each source follower operation before and after the signal charge transfer is subtracted (correlated double sampling process) via the clamp capacitors Cc1 to Cc4, thereby fixing the output voltage due to the variation in the threshold voltage of JFET2. Pattern noise, JF
Reset noise generated when the gate region of ET2 is initialized, 1 / f noise during source follower operation, and fixed pattern noise due to variations in offset voltages of the column buffer amplifiers 29a to 29d are suppressed. Therefore, similarly to the conventional solid-state imaging device (FIGS. 19 to 24), a video signal with high sensitivity and low noise (high S / N ratio) can be obtained.

Further, in the solid-state imaging device according to the first embodiment, since the control regions 4 of the respective pixels are commonly connected, problems such as overcurrent caused by short-circuiting of the control region wirings 24 are eliminated, and the manufacturing yield is reduced. improves. In the solid-state imaging device according to the first embodiment, the entire pixel including the photodiode 1 can be shielded from light by the control region wiring 24, and optical black (optical black portion) can be formed without increasing the number of manufacturing steps. .

In this case, the vertical signal lines 22a to 22a
2b, a constant current source was used as a load of the source follower circuit. However, the present invention is not limited to this. For example, a resistor may be used as a load of the source follower circuit. Further, here, the configuration in which the voltage signal is extracted by the source follower operation has been described, but the present invention is not limited to this. The source current and the drain current of the JFET 2 may be taken out as a signal. More specifically, a configuration in which the vertical signal line is connected to a current-voltage conversion circuit (via a column selection transistor) or the like to extract the source current of JFET2, or the source of JFET2 is connected to ground or a current source and the drain of JFET2 is connected Is connected to a vertical signal line to take out a drain current.

Further, the conductivity type of each semiconductor region and the polarity of the driving pulse may be reversed. [Embodiment 2] FIG. 9 is a circuit diagram showing a configuration of a solid-state imaging device according to Embodiment 2 of the present invention. The difference between the solid-state imaging device according to the second embodiment and the solid-state imaging device according to the first embodiment lies in the pixel structure. Same as in the first embodiment. First, the pixel structure of the solid-state imaging device according to the second embodiment will be described with reference to the drawings.

FIG. 10 is a plan view of a pixel of the solid-state imaging device according to the present embodiment, FIG. 11 is a cross-sectional view taken along line X3-X4, FIG. 12 is a cross-sectional view taken along line Y5-Y6,
FIG. 13 is a sectional view taken along the line Y7-Y8. Each pixel includes a photodiode 1, a JFET 2, a transfer gate 3, a control region 4, and two control gates 5, 1
It is composed of two overflow control areas 9 per pixel.

The photodiode 1, the JFET 2, the control region 4, and the overflow control region 9 are formed in the N-type semiconductor layer 101 on the high-concentration N-type semiconductor substrate 100. The transfer gate 3 and the control gate 5 are an N-type semiconductor layer 10
1 is formed via an insulating film 33. As shown in FIGS. 12 and 13, the photodiode 1 includes an N-type semiconductor layer 101 formed on a high-concentration N-type semiconductor substrate 100,
The charge storage region 12 includes a high-concentration N-type semiconductor region 13. Therefore, each pixel of the present embodiment has NP
An N-type buried photodiode is formed.

The JFET 2 is an N-channel type as shown in FIGS. 11 and 12, and has an N-type source region 14, a P-type gate region 15, an N-type drain region 16, and an N-type channel region 17.
N-type semiconductor layer 10 on N-type semiconductor substrate 100 with high concentration
1 formed therein. Therefore, it is possible to supply a drain voltage VD (see FIG. 9) to the drain region 16 of the JFET 2 via the semiconductor substrate 100 by providing a contact around the pixel region (a region where a plurality of pixels are arranged in a matrix). It is.

As shown in FIGS. 10 and 11, two control gates 5 are formed per pixel. Therefore, the control gate 5 is used as the gate electrode, the P-type control region 4 is used as one of the source and drain regions,
A P-channel MOS transistor having the second P-type gate region 15 as the other of the source and drain regions is formed. Each control gate 5 is connected in series in the row direction by a control gate wiring 21 (corresponding to the control gate wirings 21a to 21c in FIG. 9), and is driven for each row.

Since the control gates 5 are formed on both sides of the P-type gate region 15 of the JFET 2, the capacitance CG (RG) (see FIG. 3) between the P-type gate region 15 and the control gate 5 increases. . On the other hand, with the addition of control gate 5, JF
The shape of the N-type drain region 16 of ET2 changes, the contact area between the P-type gate region 15 and the N-type drain region 16 decreases, and the capacitance CGD (see FIG. 3) decreases. That is, the JFET 2 of the solid-state imaging device according to the second embodiment has the capacitance ratio CG (R
G) / CG (total) increases.

When this capacitance ratio increases, ΔVG increases according to equation (1) in FIG. For this reason, the driving of the selected row and the non-selected row is facilitated, and the desired row can be reliably selected. If ΔVG is kept constant, the value of VRGH−VT can be reduced as the above-mentioned capacitance ratio increases. For this reason, if VT is kept at a constant value, the value of VRGH can be set low, so that power consumption can be reduced.

In this embodiment, VRGH-VT could be set to 5V and ΔVG could be set to 1V. As shown in FIGS. 10 and 13, the overflow control area 9 has two pixels per pixel in the boundary area between the photodiode 1 and the control area 4.
The overflow operation of discharging the charges generated in the photodiode 1 excessively to the control region 4 is controlled. That is, the NPN type buried photodiode 1, the overflow control region 9, and the control region 4
A buried photodiode is formed with a horizontal overflow drain structure. Therefore, the control region 4 also has a function as an overflow drain.

The solid-state image pickup device of this embodiment has the pixels arranged in a matrix. The gate region of the JFET 2 and the control region 4 of the pixels arranged in the row direction are connected in series via two control gates 5 per pixel. Therefore, as can be seen from FIG. 9, in a certain pixel, the control region 4 and the control region wirings 24a to 24c (FIG.
0, corresponding to the control region wiring 24 in FIG. 11), the JFET 2 of the above pixel can be controlled from the control region 4 of another pixel even if a failure in the release mode in which connection with the control region wiring 24 is incomplete occurs.

The other configuration is the same as that of the solid-state imaging device of the first embodiment shown in FIGS. Therefore, Embodiment 2
The solid-state imaging device of the third embodiment can improve the production yield similarly to the solid-state imaging device of the first embodiment, and can form optical black without increasing the number of manufacturing steps. Further, in the solid-state imaging device according to the second embodiment, since the JFET 2 can be controlled even when a failure in the release mode in which the connection to the control region 4 is incomplete occurs, the manufacturing yield is further improved.

Since the control gates 5 are formed on both sides of the gate region 15 of the JFET 2, the capacitance ratio CG (R
As G) / CG (total) increases, it becomes easier to select a desired row. Further, since the drain voltage VD can be supplied to the N-type drain region 16 of the JFET 2 via the high-concentration (low-resistance) N-type semiconductor substrate 100, the fluctuation of the drain voltage for each pixel is reduced. , Fixed pattern noise is reduced.

Further, since the P-type charge storage region 12 of the photodiode 1 and the N-type semiconductor substrate 100 of the opposite conductivity type are used, signal charges (holes in this case) generated deep in the photodiode 1 are also reduced. Since the light is accumulated in the photodiode 1, the sensitivity is improved. [Embodiment 3] FIG. 14 is a circuit diagram showing a configuration of a solid-state imaging device according to Embodiment 3 of the present invention. The solid-state imaging device according to the third embodiment includes a bipolar transistor 50 in an amplification unit of each pixel. Further, similarly to the solid-state imaging devices of the first and second embodiments, the control region 4 is connected for each row, driven by a pulse voltage for each row, and the control gates 5 are all connected in common.

FIG. 15 is a plan view of a pixel of the solid-state imaging device according to the present embodiment, FIG. 16 is a cross-sectional view taken along line X5-X6, FIG. 17 is a cross-sectional view taken along line Y9-Y10, FIG. 18 is a cross-sectional view along the line Y11-Y12. The bipolar transistor 50 is an NPN type,
The emitter region 52, the P-type base region 53, the high-concentration N-type semiconductor substrate 100, the N-type semiconductor layer 101, and the N-type semiconductor region 54 are configured as collector regions.

The operation explanatory diagram shown in FIG. 3 (the row selecting operation of the first embodiment) shows that the JFET 2 is connected to the bipolar transistor 5.
0, the gate capacitances CGS, CGD, CG (TG), CG
(RG) to base capacitances CBE, CBC, CB (TG),
CB (RG), gate voltage VG to base voltage VB,
By replacing the drain voltage VD with the collector voltage VC, the row selecting operation of the solid-state imaging device according to the present embodiment can be similarly described.

As shown in FIGS. 15 and 16, two control gates 5 are formed per pixel. Therefore, a P-channel MOS transistor having the control gate 5 as the gate electrode, the P-type control region 4 as one of the source and drain regions, and the P-type base region 53 of the bipolar transistor 50 as the other of the source and drain regions is constructed. Is done. Each control gate 5 is connected in series in the row direction by a control gate line 21 (corresponding to the control gate lines 21a to 21c in FIG. 14), and is driven for each row.

The source and drain of the P-channel MOS transistor (that is, the control region 4 and the base region 53 of the bipolar transistor 50) are P-type semiconductor regions. On the other hand, the emitter region 52 and the collector region 54 of the bipolar transistor 50 are of the opposite conductivity type (N-type semiconductor region). The base region 53 of the bipolar transistor 50 has the same conductivity type (P-type semiconductor region) as the source and drain of the P-channel MOS transistor. Thus, if the conductivity type of each semiconductor region is selected, turning off the control gate increases the base voltage of bipolar transistor 50 by ΔVB. Therefore, the above-described row selection operation can be performed.

The other of the P-type base region 53 of the bipolar transistor 50 and the source or drain region of the P-channel MOS transistor is the same semiconductor region. By doing so, it is possible to delete unnecessary wirings and diffusion regions. For this reason, not only the parasitic capacitance becomes smaller and the output signal increases, but also miniaturization becomes possible.

The other structure is the same as that of the solid-state image sensor of the second embodiment. Therefore, the solid-state imaging device according to the third embodiment has the same characteristics as the solid-state imaging device according to the second embodiment. Further, since the solid-state imaging device according to the third embodiment employs the bipolar transistor 50 in the amplification unit, the structure is simplified and the degree of integration is improved.

[0085]

As described above, in the solid-state imaging device according to the present invention, since the control regions of the respective pixels are connected in common, problems such as overcurrent due to short-circuiting of the wires connecting the control regions to each other are caused. This has the effect of improving the manufacturing yield. Further, in the solid-state imaging device according to the present invention, since the whole pixel can be shielded from light by the wiring connecting the control region, there is also an effect that optical black can be formed without increasing the number of manufacturing steps.

In the solid-state imaging device according to the present invention, since the drain voltage can be supplied via the high-concentration (low-resistance) semiconductor substrate, there is also an effect that fixed pattern noise is reduced. Further, in the solid-state imaging device according to the present invention, since a semiconductor substrate of a conductivity type opposite to that of the photodiode is employed, there is also an effect that sensitivity is improved.

Further, according to the present invention, it is possible to select a row using capacitive coupling, and drive pulses (input pulses to the image pickup device) are reduced, whereby the vertical scanning circuit of the solid-state image pickup device is simplified. There is also an effect that.

[Brief description of the drawings]

FIG. 1 is a circuit diagram illustrating a configuration of a solid-state imaging device according to a first embodiment of the present invention.

FIG. 2 is a pulse timing chart illustrating an operation of the solid-state imaging device according to the first embodiment.

3A and 3B are explanatory diagrams of a row selection operation of the solid-state imaging device according to the first embodiment. FIG. 3A is an equivalent circuit diagram of a pixel, and FIG. FIG.

FIG. 4 is a plan view showing a schematic configuration of a pixel of the solid-state imaging device according to the first embodiment of the present invention.

FIG. 5 is a sectional view taken along line X1-X2 in FIG. 4;

FIG. 6 is a sectional view taken along line Y1-Y2 of FIG.

FIG. 7 is a sectional view taken along line Y3-Y4 of FIG.

FIG. 8 is a partial plan view showing a boundary region between pixels forming an imaging unit of the solid-state imaging device of Embodiment 1 and pixels forming optical black (optical black portion).

FIG. 9 is a circuit diagram illustrating a configuration of a solid-state imaging device according to a second embodiment of the present invention.

FIG. 10 is a pixel plan view of the solid-state imaging device according to Embodiment 2.

FIG. 11 is a sectional view taken along line X3-X4 in FIG. 10;

FIG. 12 is a sectional view taken along line Y5-Y6 of FIG.

FIG. 13 is a sectional view taken along the line Y7-Y8 in FIG.

FIG. 14 is a circuit diagram illustrating a configuration of a solid-state imaging device according to Embodiment 3 of the present invention.

FIG. 15 is a pixel plan view of the solid-state imaging device according to the third embodiment.

FIG. 16 is a sectional view taken along line X5-X6 in FIG.

FIG. 17 is a sectional view taken along the line Y9-Y10 in FIG.

FIG. 18 is a sectional view taken along the line Y11-Y12 in FIG.

FIG. 19 is a circuit diagram illustrating a schematic configuration of a conventional solid-state imaging device.

20 is a pulse timing chart of the circuit diagram shown in FIG.

FIG. 21 is a plan view illustrating a schematic configuration of a pixel of a conventional solid-state imaging device.

FIG. 22 is a sectional view taken along the line Xa-Xb in FIG. 21;

FIG. 23 is a sectional view taken along the line Ya-Yb in FIG. 21;

24 is a sectional view taken along the line Yc-Yd in FIG.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 photodiode 2 JFET 3 transfer gate 4 control region 5 control gate 7 vertical scanning circuit 8 horizontal scanning circuit 9 overflow control region 10 P-type semiconductor substrate 11 N-type well region 12 P-type charge accumulation region 13 High-concentration N-type semiconductor region 14 N-type source region 15 P-type gate region 16 N-type drain region 17 N-type channel region 20, 20a-20c Transfer gate wiring 21, 21a-21c Control gate wiring 22, 22a-22d Vertical signal line 24, 24a-24c Control Area wiring 26a to 26d Constant current source 27 Horizontal signal line 28 Output buffer amplifier 29a to 29d Column buffer amplifier 33 Insulating film 35 Output terminal 50 Bipolar transistor 52 N-type emitter region 53 P-type base region 54 N-type semiconductor region 100 High concentration N-type semiconductor substrate 1 1 N-type semiconductor layer

Claims (6)

[Claims] 1. A pixel comprising: an amplification unit that outputs a signal corresponding to incident light; a control region that controls the amplification unit; and a control gate that controls an electrical connection state between the amplification unit and the control region. A plurality of solid-state imaging devices, wherein each of the control regions is connected to a power supply in common; the control gate is driven by a pulse voltage for each row; and in a row in which the control gate is turned on by the pulse voltage, In the row where a constant voltage is supplied from the control region to the amplifying unit and the amplifying unit is in a non-operation state, and the control gate is cut off by the pulse voltage, the amplifying unit and the control region are electrically connected. A solid-state imaging device, wherein the amplifier is activated by capacitive coupling between the control gate and the amplifier. 2. The solid-state imaging device according to claim 1, wherein a MOS transistor is configured in which the control gate is a gate electrode and the control region is one of a source and a drain. An effect type transistor, the gate of which is connected to the other of the source and the drain of the MOS type transistor, and the source and the drain of the MOS type transistor have a conductivity type opposite to the source and the drain of the field effect type transistor. A solid-state imaging device, comprising: 3. A MOS transistor having the control gate as a gate electrode and the control region as one of a source and a drain, wherein the amplifying unit is a junction field effect transistor, and the gate is the MOS transistor. And the gate of the junction field effect transistor is connected to the other of the source and the drain of the transistor.
2. The solid-state imaging device according to claim 1, wherein the solid-state imaging device has the same conductivity type as a source and a drain of the S-type transistor. 4. The solid-state imaging device according to claim 3, wherein the gate of the junction field effect transistor and the other of the source and the drain of the MOS transistor are the same semiconductor region. 5. A MOS transistor having the control gate as a gate electrode and the control region as one of a source and a drain, wherein the amplifying unit is a bipolar transistor, and the base of the MOS transistor is a MOS transistor. 2. The solid-state imaging device according to claim 1, wherein the base is connected to the other of the source and the drain, and a base of the bipolar transistor has the same conductivity type as a source and a drain of the MOS transistor. 6. The solid-state imaging device according to claim 5, wherein the other of the base of the bipolar transistor and the source or the drain of the MOS transistor is the same semiconductor region.