JP2000076667A - Phase difference detection circuit and its method, phase comparator having the phase difference detection circuit, phase locked loop circuit having the phase difference comparation circuit and optical disk drive servo device using the phase locked loop circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten a processing time with a less memory and simple circuit constitution by calculating a first phase difference from prescribed bits of respective first bits of first and second digital signals and calculating a sine wave component correction value and a cosine wave component correction value from prescribed bit data of respective first bits. SOLUTION: A digital system phase comparator 52 is provided with a digital complex multiplier 521 and a digital phase difference detector 522, and the digital complex multiplier 521 inputs a digital tracking error signal TE shown as a sine wave function sin (α) of a phase angle (α) and a digital cross track signal CTS whose phase advances by 90 deg. for the tracking error signal TE and shown as a cosine wave function cos (α) of the phase angle (α), and calculates the phase differences between the digital input signals and a digital sine wave signal and a digital cosine wave signal from a digital voltage control type oscillator 56.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop having a phase difference detecting circuit used in a phase locked loop, and more particularly to a phase locked loop used in an optical disk drive / servo system (apparatus) for detecting a phase difference. The present invention relates to a phase difference detection circuit and a method thereof, a phase comparator using the phase difference detection circuit, a phase synchronization circuit using the phase comparator, and an optical disk drive / servo apparatus having the phase synchronization circuit.

[0002]

2. Description of the Related Art In an optical disk drive / servo system (apparatus), which will be described in detail later with reference to FIG. 1, a phase difference between a tracking error signal TE and a cross track signal CTS is detected to determine whether to switch a tracking control signal. Phase-locked loop (PLL) 2 to provide signals
6 is used.

[0003] Optical disk drive / servo system (device) 1
Signal processing of 0 has recently tended to be digitized.

[0004]

However, there is a demand for a digital phase locked loop circuit with a reduced memory capacity, a simplified circuit configuration, and a higher processing speed. Circuit not known.

[0005] Such phase locked loop circuits typically include a phase comparator, a loop filter and a voltage controlled oscillator (VCO).
In particular, there is no known phase comparator in which the memory capacity is reduced, the circuit configuration is simplified, and the processing speed is increased. Among the phase comparators, it is desired to shorten the processing time of the phase detector with a small memory capacity and a simple circuit configuration.

An object of the present invention is to provide a phase difference detecting circuit which can reduce the processing time with a small memory capacity, a simple circuit configuration, without lowering the accuracy. Another object of the present invention is to provide a phase difference detection method for realizing the above phase difference detection circuit.

Another object of the present invention is to provide a phase comparator using the above-mentioned phase difference detection circuit. In particular, the present invention provides a small-capacity memory with a simple circuit configuration without deteriorating accuracy. An object of the present invention is to provide a phase comparator capable of reducing time.

It is still another object of the present invention to provide a phase locked loop using the above phase comparator.
An object of the present invention is to provide a phase-locked loop circuit that can reduce the processing time with a small memory capacity, a simple circuit configuration, and without reducing accuracy.

An object of the present invention is to provide an optical disk drive servo system (apparatus) for performing phase synchronization between a tracking error signal and a cross track signal using the phase synchronization circuit. An object of the present invention is to provide an optical disk drive / servo system (apparatus) capable of performing accurate tracking servo control with a small memory capacity and a simple circuit configuration without lowering the accuracy.

[0010]

According to a first aspect of the present invention, a first digital signal of a first bit that changes in a sinusoidal manner as a function of a phase difference (α-β) is provided. A digital phase difference detection circuit for detecting the phase difference from a second digital signal of a first bit that changes in a cosine wave function that is a function of the phase difference substantially orthogonal to the digital signal of 1 of the first bit of the digital signal (hereinafter referred to as first higher-order data) and data of the predetermined bit of the first bit of the second digital signal (hereinafter referred to as first upper data). Phase difference calculating means for calculating a first phase difference (PV) from the second upper data, and a sine wave component gain (Gs) from the first higher data and the second higher data, The calculated sine wave component Sine wave component gain correction value for calculating a sine wave component gain correction value by multiplying the first digital signal by the remaining lower bit data (hereinafter, first lower data) of the first higher data of the first digital signal. Means,
A cosine wave component gain (Gc) is calculated from the first high-order data and the second high-order data, and the calculated lower cosine wave component gain is added to the remaining lower-order data of the first higher-order data of the second digital signal. A cosine wave component gain correction value calculating means for calculating a cosine wave component gain correction value by multiplying bit data (hereinafter, second lower data), the first phase difference, and the sine wave component gain correction value; And an adding means for adding the cosine wave component gain correction value to the phase difference detection circuit.

The phase difference calculating means calculates a first phase angle PV using the first high-order data and the second high-order data as functions (parameters), and the sine wave component gain correction value calculating means calculates the first high-order data. The sine gain Gs is calculated using the first higher-order data and the second lower-order data as a function (parameter) to calculate a sine gain correction value. The cosine-wave component gain correction value calculation means calculates a sine gain correction value. The cosine gain Gc calculated using the upper data and the second upper data as functions (parameters) is multiplied by the second lower data to calculate a cosine gain correction value. Is generated (detected). The first phase angle PV is not a first digital signal of all bits, but a first digital signal of only upper bits.
Is calculated not from the second digital signal of all bits but from the second upper data of only upper bits, but the accuracy is not sufficient. This lack of accuracy is corrected with a sine gain correction value and a cosine gain correction value. As a result, when the phase difference is calculated using the first digital signal of all bits and the second digital signal of all bits, a phase difference with the same accuracy can be detected.

Preferably, the phase difference calculating means includes first table means which can read the first phase difference using the first higher-order data and the second upper-order data as addresses, and the sine wave The component gain correction value calculation means includes: a second table means capable of reading the sine wave component gain (Gs) using the first higher-order data and the second higher-order data as addresses; and reading the sine wave component gain (Gs) from the second table. First multiplication means for multiplying the obtained sine wave component gain by the first lower-order data, wherein the cosine wave component gain correction value calculation means calculates the cosine wave component gain (Gc) by the first higher-order data. Third table means capable of reading data and the second upper data as addresses, and adding the second lower data to a cosine wave component gain read from the third table. Jill and a second multiplication means.

The phase difference calculating means reads out the first phase difference from the first table means by a table look-up method. The sine wave component gain correction value calculation means reads the sine wave component gain from the second table means by a table lookup method. The cosine wave component gain correction value calculating means reads out the cosine wave component gain from the third table means by a table lookup method. Therefore, the first
, The sine wave component gain and the cosine wave component gain can be calculated in a short time. In addition, since the first to third table means can be integrated using a ROM or the like, the circuit configuration is simple. Furthermore, considering the memory capacity,
For example, the first digital signal is 10 bits,
Assuming that the second digital signal is also 10 bits and a table is created that can directly calculate an 8-bit phase difference using these two 10-bit signals as parameters, the memory of such a table indicates like,
Dividing into three tables reduces the overall memory capacity.

[0014] More preferably, the addition means includes first addition means for adding the sine wave component gain correction value and the cosine wave component gain correction value, and an addition result of the first addition means and the second addition means. There is provided a digit matching unit for performing digit matching with the phase difference of 1, and a second adding unit for adding the result of the digit matching and the first phase difference. That is, digit alignment is performed as necessary.

According to a second aspect of the present invention, a first digital signal of a first bit, which changes in a sine wave shape and is a function of the phase difference, and the phase difference substantially orthogonal to the first digital signal. And a second digital signal of a first bit that changes in a cosine wave shape as a function of: a phase difference detection method for detecting the phase difference, wherein the first bit of the first digital signal includes A first phase difference between data of a predetermined bit (hereinafter, first upper data) and data of the predetermined bit (hereinafter, second upper data) of the first bit of the second digital signal; (PV)
And calculates a sine wave component gain (Gs) from the first higher-order data and the second higher-order data, and adds the first higher-order data of the first digital signal to the calculated sine wave component gain. Is multiplied by the remaining lower bit data (hereinafter, first lower data) to calculate a sine wave component gain correction value, and obtain a cosine wave component gain (Gc) from the first higher data and the second higher data. Is calculated by multiplying the calculated cosine wave component gain by the data of the remaining lower bits of the first upper data of the second digital signal (hereinafter, second lower data) to obtain a cosine wave component gain correction value. And calculating the first phase difference as the phase difference;
A phase difference detection method is provided that adds the sine wave component gain correction value and the cosine wave component gain correction value.

According to a third aspect of the present invention, a first sinusoidal digital signal of a first bit which varies sinusoidally and has a first phase (α) as a function, and the first digital signal is A first comparison target signal having a first bit of a second sinusoidal digital signal that changes in a cosine waveform having a function of the first phase in a substantially orthogonal relationship, and a second phase (β) as a function The second digital signal of the first bit which changes in a sine wave shape and the first bit of the first bit which changes in a cosine wave function as a function of the second phase which is substantially orthogonal to the second sine wave digital signal. 2 and a second comparison signal having a cosine wave digital signal having a phase difference (α−
β) for detecting β), wherein the phase comparator comprises:
It has a complex multiplier and a phase detector. The complex multiplier includes the first sinusoidal digital signal and the first
A first comparison target signal including a cosine wave digital signal, a second sine wave digital signal, and a second
And a second comparison target signal including a cosine wave digital signal of the first bit, and a first bit of a first bit that changes in a sine wave shape having a function of a phase difference between the first phase and the second phase. A first digital complex signal and a first digital complex signal of a first bit that changes in a cosine wave function that is a function of the phase difference and that is substantially orthogonal to the first digital complex signal are generated. The phase detector has the configuration of the above-described phase difference detection circuit of the present invention and performs the above-described operation.

Preferably, the complex operation in the complex multiplier is defined by the following equation: sin (α-β) = sin (α) × cos (β) -co
s (α) × sin (β) cos (α−β) = cos (α) × cos (β) + si
n (α) × sin (β) where sin (α) is the first sine wave digital signal, cos (α) is the first cosine wave digital signal, and sin (β) is the A second sine wave digital signal, and cos (β) is the second cosine wave digital signal.

More preferably, the complex multiplier has a function of sin (α) × c for all of the first sine wave digital signal and the second cosine wave digital signal.
os (β) is stored in advance in the first table means and the first cosine-wave digital signal and the second sine-wave digital signal are cos (α) × sin ( β), the second table means storing the result of pre-computation, and cos (α) × cos (β) for all of the first cosine wave digital signal and the second cosine wave digital signal. Third table means storing a result of previously calculating the first sinusoidal digital signal and the second
For all sinusoidal digital signals of
A fourth table means for storing a result of previously calculating (α) × sin (β); a first subtraction means; and a second addition means, wherein the first table means When the first sine-wave digital signal is applied as a first address and the second cosine-wave digital signal is applied as an outer two address, the corresponding sin ( α) × cos (β), and the second table means applies the first digital cosine waveform signal as a first address and the second digital sine wave signal as a second address. Then, the result of the corresponding cos (α) × sin (β) stored in the memory specified by these addresses is output, and the third table means converts the first cosine-wave digital signal to First And when the second cosine wave digital signal is applied as a second address, a corresponding cos (α) × cos (β) result stored in a memory defined by these addresses is output. The fourth table means, when the first sine wave digital signal is applied as a first address and the second sine wave digital signal is applied as a second address, stores in a memory defined by these addresses. The stored but corresponding sin (α) × sin (β) result is output,
The subtraction means calculates sin (α-β) by subtracting the result output from the second table means from the result output from the first table means, and the second addition means The result output from the third table means and the result output from the fourth table means are added to calculate cos (α-β).

In the phase comparator of the present invention, in addition to the above-described phase difference detection circuit, the complex multiplier can quickly obtain a complex operation result by a table lookup system. Further, the circuit configuration is simple because of the table system.

According to a fourth aspect of the present invention, there is provided a digital phase comparing means, and a digital voltage control type oscillating means for applying an oscillation signal corresponding to a phase difference from the phase comparator to the phase comparing means. A phase locked loop is provided. The digital phase comparator has the digital complex multiplier and the digital phase detector. Preferably, the voltage-controlled oscillator uses a phase difference from the phase comparator as an address, and forms a sine wave having a function of a corresponding second phase (β) stored in a memory defined by the address. The first digital signal having a first bit that changes and the first digital signal that changes in a cosine waveform having a function of the second phase that is substantially orthogonal to the second sine wave digital signal.
First table means for outputting said second cosine wave digital signal of bits.

In the above-mentioned phase locked loop circuit, in addition to the above-described phase detector, complex multiplier, and phase comparator having these complex multiplier and phase detector, a voltage controlled oscillator (VCO) is also used in a table lookup system. Therefore, a predetermined oscillation signal can be generated quickly and the circuit configuration is simple.

According to a fifth aspect of the present invention, an optical disk drive servo system for detecting the phase relationship between a tracking error signal (TE) and a cross track signal (CTS) orthogonal to the tracking error signal. An optical disk drive servo having a digital phase locked loop used in the optical disk drive is provided. The digital phase-locked loop includes a digital phase comparator and a digital voltage controlled oscillator for applying an oscillation signal corresponding to a phase difference from the digital phase comparator to the digital phase comparator. The digital phase comparator has a complex multiplier and a phase detector. Preferably, the digital voltage controlled oscillator uses the phase difference from the phase comparator as an address and forms a sinusoidal waveform having a function of a corresponding second phase (β) stored in a memory defined by the address. The second cosine of the first bit changing in a cosine wave function as a function of the second phase of the changing first bit and the second phase in a substantially orthogonal relationship with the second sine wave digital signal. And a first table means for outputting a wave-like digital signal. As described above, the phase locked loop is constituted by a digital circuit including a table, has a simple circuit configuration, and has a short processing time.

[0023]

Embodiments of the present invention will be described. FIG. 1 shows a general optical disk drive servo using a phase difference detection circuit of the present invention, a phase comparator having the phase difference detection circuit, and a phase locked loop (PLL) using the phase locked loop. It is a schematic structure figure of a system (device). The optical disk drive / servo system illustrated in FIG. 1 particularly shows an outline of a tracking control system.
The tracking control controls the positioning of the light beam from the optical pickup at a predetermined track position on the optical disc 12. As the servo control of the optical disk drive / servo system, besides the tracking control, focus control for positioning the optical pickup at a predetermined position with respect to the surface of the optical disk 12 is typical. An example of the control will be described. The illustrated optical disk drive / servo system particularly illustrates a part of a reproduction system for reading data recorded on the optical disk 12.

Optical disk drive / servo system 1 illustrated
0 has an optical disk 12 on which data is recorded, a spindle motor 14 for rotating the optical disk 12, an optical pickup, and a servo control unit.

The optical pickup includes an optical detector 16 and
A semiconductor laser 18, a half mirror 19, a tracking coil 20, and an objective lens (not shown) are mounted.

The servo control unit of the optical disk drive / servo system 10 includes a first A / D converter 22 for converting the analog (voltage) tracking error signal TE calculated by the optical detector 16 into a digital format, and an optical detector 16.
Analogue (voltage) cross track calculated by
A second A / that converts signal CTS to digital form
It has a D converter 24. The servo control unit of the optical disk drive / servo system 10 includes a phase locked loop (PLL) 26,
It has a traverse counter 28 that counts a synchronization signal of a phase locked loop (PLL) 26. The servo control unit of the optical disk drive / servo system 10 further includes a switching determination device 30, a phase compensation circuit 32, a D / A converter 34, and a drive amplifier (drive amplifier) 36.

An outline of tracking servo control of the optical disk drive / servo system illustrated in FIG. 1 will be described. An optical disk 12 on which data is recorded in a groove is rotated by a spindle motor 14 at a constant angular velocity or a constant peripheral velocity. The light beam emitted from the semiconductor laser 18 is converged by an objective lens (not shown) via a half mirror 19, and is irradiated on a predetermined groove of the optical disc 12 on which data is recorded. The converged beam light applied to the optical disc 12 is
2 and the reflected light enters the light detector 16 via the half mirror 19.

The optical detector 16 is, for example, a four-division optical detector. The four-division optical detector is arranged in the groove direction (tangential direction) and the groove radial direction (radial direction) of the optical disk 12 with respect to the center. It is divided into four parts. The quadrant light detector 16 is based on the center direction.
A tracking error signal TE is generated from the difference between the left and right light receiving amounts in the radial direction (tracking direction), and a cross track signal CTS having a phase advanced by 90 ° from the tracking error signal TE is generated.
6 generates an RF signal (not shown) which is the sum of the received light.

The first A / D converter 22 is connected to the optical detector 16
Converts the analog (voltage) tracking error signal TE output from the device into digital data. The second A / D converter 24 outputs an analog (voltage) cross track signal C output from the optical detector 16.
The TS is converted to digital data. The phase synchronization circuit (PLL) 26 converts the digital tracking error signal TE converted by the first A / D converter 22 and the second A
The digital cross track signal CTS converted by the / D converter 24 is input, the phase difference between the two is calculated, and the operation is performed so that the phase difference between the two becomes zero.

FIG. 2 illustrates a general circuit of the phase locked loop (PLL) 26. FIG. 2 shows the PLL 26 illustrated in FIG.
FIG. 3 is a circuit configuration diagram of a phase synchronization circuit 40 as a specific circuit of FIG. Since the PLL 26 performs a phase synchronization process on a digital signal, the phase synchronization circuit 40 illustrated in FIG. 2 is a digital phase synchronization circuit. The digital phase locked loop circuit 40 includes a digital phase comparator 42, a digital loop filter 44, and a digital voltage controlled oscillator (V
CO) 46. The digital phase comparator 42
It compares the phase α of the digital input signal with the phase β of the digital output signal from the digital VCO 46 and outputs a voltage signal corresponding to the phase difference Δφ = (α−β). The digital loop filter 44 filters the phase difference voltage signal output from the digital phase comparator 42 with predetermined filter characteristics, and passes low frequency components. The digital loop filter 44 is not essential as a configuration of the phase locked loop 40, but is usually included in the phase locked loop 40. The digital VCO 46 oscillates at a frequency corresponding to the voltage output from the digital loop filter 44, and outputs an oscillation signal of the frequency as a digital output signal to the outside (to the traverse counter 28 in the example of FIG. 1). The digital output signal is applied to the digital phase comparator 42 (returned), and is subjected to the above-described phase difference calculation with the input signal. As a result of the above operation, the digital phase-locked loop 40 generates a signal having a frequency corresponding to the phase difference Δφ = (α−β) between the two input signals from the digital VCO 46. The digital phase comparator 42 calculates a phase difference Δφ as a reference of the oscillation signal in the digital VCO 46.

When the digital phase locked loop 40 is applied to the phase locked loop (PLL) 26 of the optical disk drive / servo system 10 illustrated in FIG. 1, the PLL 26 generates the tracking error signal TE and the cross track signal CT.
The phase difference Δφ from S is calculated, and a signal having a frequency corresponding to the phase difference is output. When the optical pickup is far away from the positioning target track position of the optical disc 12,
A large phase error occurs between the tracking error signal TE and the cross track signal CTS, and the PLL 26
Output a pulse signal having a frequency corresponding to the phase difference.

The traverse counter 28 counts the phase error signal output from the phase locked loop (PLL) 26. The tracking error signal TE and the cross track
When the phase error with the signal CTS is large, PL
Since the number of pulses per predetermined time of L26 is large, the count value of the traverse counter 28 increases.

The tracking control is performed so that the tracking error becomes zero.
When the position of the optical pickup deviates greatly from the target track, the tracking error signal TE detected by the optical detector 16 is not used, and a predetermined tracking error signal is used for servo control. Therefore, the switching determination device 30 refers to the count value of the traverse counter 28 and uses the actual tracking error signal TE from the first A / D converter 22 or uses a preset tracking error signal. Is determined, and either the actual tracking error signal TE or a preset tracking error signal is selected and output.

The digital phase compensating circuit 32 calculates the tracking error signal TE output from the switching determination device 30.
To compensate for the phase. The D / A converter 34 is a phase compensation circuit 3
In step 2, the digital-format tracking control signal whose phase has been compensated is converted into an analog-format signal. The drive amplifier 36 amplifies the tracking control signal converted into a voltage signal and applies the amplified signal to the tracking coil 20. The tracking coil 20 moves the optical pickup based on the tracking control signal applied from the drive amplifier 36 so that the tracking error becomes zero. FIG. 1
2 is an outline of tracking control in the optical disk drive / servo system 10 illustrated in FIG.

The phase locked loop (PLL) 2 illustrated in FIG.
6 is a digital tracking error signal TE output from the first A / D converter 22 and the second A / D converter.
This is a digital signal processing circuit that detects a phase error with respect to the digital cross track signal CTS output from the converter 24 and performs an operation (takes phase synchronization) to eliminate these phase differences. Therefore, PL
Phase synchronization circuit 4 illustrated in FIG. 2 used as L26
0 is also configured as a digital signal processing circuit.

Digital Phase Lock Circuit FIG. 3 is a diagram illustrating a more specific circuit configuration example of the digital phase lock circuit 40 illustrated in FIG. The digital phase locked loop circuit 50 illustrated in FIG. 3 includes a digital phase comparator 52, a digital loop filter 54,
A digital voltage-controlled oscillator (VCO) 56.

Digital Phase Comparator The digital phase comparator 52 has a digital complex multiplier 521 and a digital phase difference detector 522.

Complex Multiplier The digital complex multiplier 521 includes a digital tracking error signal TE expressed as a sine wave function sin (α) having a phase angle α, and the tracking error signal TE
, A digital cross track signal CTS expressed as a cosine wave function cos (α) of a phase angle α, and a digital voltage controlled oscillator (VCO)
56, the phase difference Δφ = (α) between the digital sine wave signal sin (β) and the digital cosine wave signal cos (β).
−β) is calculated by the following complex operation.

Sin (α−β) = sin (α) × cos (β) −cos (α) × sin (β) cos (α−β) = cos (α) × cos (β) + sin (α) × sin (β) (1)

If the above operation is directly performed in the complex multiplier 521, a sine function generation circuit, a cosine function generation circuit, four multiplication circuits, one addition circuit and 10
Since the subtraction circuit is required, the circuit becomes complicated. Furthermore, it takes a long calculation time. Therefore, preferably, the following operation is preferably performed on all combinations of the phase α and the phase β in advance, and the result is stored in a table such as a ROM, and the table lookup is performed using the phases α and β as addresses. The following calculation result of the corresponding value can be read. When the table and the look-up method are adopted as described above, the following calculation time can be greatly reduced.

A = sin (αα) × cos (ββ) B = cos (αα) × sin (ββ) C = cos (αα) × cos (ββ) D = sin (αα) × sin (ββ) αα] is angle data in a range that the phase [α] can take, and [ββ] is angle data in a range that the phase [β] can take.

When the partial operation result is stored in the ROM in advance and the table lookup method can be read out, for example, the phase α is set to 8-bit angle data, the phase β is set to 8-bit angle data, and Assuming that the operation results A, B, C, and D are 8-bit data,
The memory capacity of the ROM is calculated for A, B, C, and D.
(256 x 256 x 8 bits) x 4 = 64K bytes x
4 = 256 Kbytes.

In the complex multiplier 521, A, B,
After reading C and D by table lookup,
The following operation is performed using one subtractor and one adder.

Sin (XY) = AB cos (XY) = C + D (2)

That is, as an example of the above-described embodiment, the complex multiplier 521 includes a table memory for calculating A, B, C, and D, for example, a ROM, one subtractor, and one It can be composed of an adder. This circuit configuration is simple, and only the subtraction process and the addition process are performed after reading out A, B, C, and D from the table, so that the calculation time is short.

The phase difference detector digital phase difference detector 522 calculates a calculation result sin (α-β) and cos complex multiplier 521 (α-β), = the phase difference Δφ of the (α-β). Phase difference Δφ =
A basic method of calculating (α-β) will be described. Sin (α−β) and cos input to phase difference detector 522
As a method of calculating the phase difference Δφ = (α−β) from (α−β), from the following relationship,

Sin ² (α−β) + cos ² (α−β) = 1 (3)

In orthogonal two-dimensional coordinates, co
By taking s (α-β) and sin (α-β) in the Y-axis direction, a circle having a radius of 1 is drawn, and an angle between a line on the circle satisfying this condition and the origin and the X-axis is calculated. More specifically, as illustrated in FIG. 4, in a two-dimensional plane, X
In the axial direction and the Y-axis direction, the parameters defined by Equation 3 are represented by R
Mapping to a table such as OM, the angle Δφ that the line connecting the point closest to the corresponding value and the origin makes the X axis
Is calculated. This angle Δφ is the phase difference Δφ = (α−β) from the phase detector 522.

As described above, the memory capacity to be mapped when the method for directly calculating the phase difference Δφ = (α−β) illustrated in FIG. 4 is applied to the phase difference detector 522 will be considered. When the digital input signal and the digital output signal to the digital phase difference detector 522 have a signed 8-bit precision, it is possible to cope with the amplitude fluctuation of the input signal caused by the error of the tracking error signal TE and the cross track signal CTS. When the phase difference detector 522 is realized using a look-up table using a ROM, since the depth is 8 bits, 256 × 256 ×
8 bits = 64K bytes capacity table, for example
A ROM table with a capacity of 64 Kbytes is required.

Improved Phase Difference Detector Next, an improved phase difference detector 52 which is an improvement of the above-described phase difference detector 522, in particular, reduces the memory capacity.
A second embodiment will be described. Improved phase difference detector 522
In the above, as in the above discussion, a case of handling an 8-bit signal will be described as an example. The improved phase difference detector 522 has a table illustrated in FIG. 5 and an arithmetic circuit illustrated in FIG. As illustrated in FIG. 5, the tables constituting the improved phase difference detector 522 include a phase difference (PV) table 74 and a sine (sin) gain (Gs).
) Table 76, and a cosine (cos) gain (Gc) table 78. The phase difference detector 522 further includes
It has an arithmetic circuit illustrated in FIG. The arithmetic circuit of FIG.
It has a first multiplier 100, a second multiplier 102, an adder 104, a shifter 106, an adder circuit 108, and an adder circuit 110. That is, the improved phase difference detector 5
Reference numeral 22 denotes tables 74, 76, and 78 in FIG. 5 in which the circuits in FIG. 6 are combined.

The operation of the improved phase difference detector 522 illustrated in FIGS. 5 and 6 will be described. The data of the higher 4 bits of the 8 bits of the sine operation result: sin (α−β) output from the complex multiplier 521 illustrated in FIG. 3 is applied to the first signal input terminal 71 of FIG. To the second signal input terminal 72, data of the upper 4 bits of the 8 bits of the cosine operation result: cos (α-β) output from the complex multiplier 521 is applied, and the phase difference (PV) table 7
4. Sine gain (Gs) table 76, cosine gain (Gs)
c) Used as the address of the table lookup for table 78.

Of the 8 bits of sin (α-β), the upper 4 bits of data are denoted as sin (α-β) _H, and the lower 4 bits of data are denoted as sin (α-β) _L. Similarly, the upper 4 bits of the 8 bits of cos (α-β) are denoted as cos (α-β) _H, and the lower 4 bits are denoted as cos (α-β) _L.

Coarse phase difference calculation and phase difference (PV) table
As illustrated in FIG. 7, the bull 74 phase difference (PV) table 74 takes the cosine value of the frequency difference component having signed 8-bit precision on the X axis and the sine value on the Y axis. The PV table 74 is formed of, for example, a ROM, has a size of 16 × 16, and has higher-order 4 bits sin (α−α) input to the first signal input terminal 71 and the second signal input terminal 72.
β) _H and the value of the phase difference Δφ = (α−β) corresponding to the upper four bits cos (α−β) _H are output to the first output terminal 81. The value of the cosine of the upper 4 bits is (20) h to (2
F) h, the value of the sine of the upper 4 bits is (60) h to (6)
F) In the range of h, a value corresponding to the phase difference Δφ at the coordinates (28h, 68h) is output from the first output terminal 81. The symbol h is a symbol indicating that it is in hexadecimal notation. The phase difference value PV output from the first output terminal 81 is 8 bits, and the range of -π to 0 to + π is (80) h to
(7F) h.

In the improved phase difference detector 522, the memory capacity of the phase difference (PV) table 74 is very small, but the upper 4 bits sin (α-β) _H and the upper 4 bits cos (α- β) Since the table lookup is performed from _H , the accuracy is lower than that of the above method.
Therefore, the gain of the phase angle PV is corrected using the sine gain Gs and the cosine gain Gc.

Sine Gain Correction The sine gain correction will be described. Upper 4 bits sin
(Α-β) _H and upper 4 bits of cos (α-β) _H
As an address, for example, a ROM illustrated in FIG.
A sine gain (Gs) table 76 is looked up in a table, and a sine gain Gs is calculated, and is output from the second output terminal 82. Next, the calculated sine gain Gs is applied to the second signal input terminal 92 in FIG. 6, and the lower 4 bits of the 8-bit sin (α-β), sin (α−
β) _L is applied to the first signal input terminal 91, and the first multiplier 100 multiplies these. That is, the following calculation is performed. The following calculation result is called a sine wave component gain correction value.

Gs × sin (α-β) _L

The sine gain (Gs) table 76 is a ROM
And one input, 4-bit sin (α-
β) _H and a signed 4-bit sine gain that is looked up in a table with the 4-bit cos (α-β) _H as an address are stored. The sine gain (Gs) table 76 is 16 ×, like the phase angle (PV) table 74.
16 is a 16-dimensional table.

Cosine Gain Correction Similar to the sine wave component gain correction, the cosine wave component gain correction is performed by using the upper 4 bits cos (α-β) _H and the upper 4 bits cos (α-β) _H as addresses. 5, the cosine gain (Gc
C) The table 78 is looked up in a table to calculate the cosine gain Gc, which is output from the third output terminal 83. Then, the calculated cosine gain Gc is applied from the fourth signal input terminal 94 in FIG. 6, and the lower 4 bits of the 8-bit cos (α-β), cos (α-β) _L are applied to the third signal input terminal. The second multiplier 102 performs these multiplications. That is, the following calculation is performed. This calculation result is called a cosine wave component gain correction value.

Gc × cos (α-β) _L

The cosine gain (Gc) table 78 has a ROM
One input, upper 4 bits sin
(Α−β) _H and upper 4 bits cos (α−β)
_Stores a signed 4-bit cosine gain to be looked up in a table using _H as an address. That is, the sine gain cosine gain (Gc) table 78 is a 16 × 16 two-dimensional table, like the phase angle (PV) table 74.

The operation in the first multiplier 100 is performed by using a signed 4-bit sine gain Gs and a signed 4-bit si
This is a binary multiplication with n (α-β) _L, and the result is signed 8-bit data. Similarly, the multiplication in the second multiplier 102 is performed by using an 8-bit cosine gain Gc and 4
Binary multiplication of the bits by cos (α-β) _L ,
The result is signed 8-bit data. Note that the multiplication in the first multiplier 100 and the second multiplier 102 may be actually performed using a binary multiplication circuit, or may be performed in the first multiplier 100 and the second multiplier 102. The table lookup method can be replaced with multiplication. In the latter case, the first multiplier 100 calculates the multiplication results of all combinations of the sine gain Gs and cos (α-β) _L in advance and stores them in the ROM table to perform multiplication. Is the sine gain Gs and co
The multiplication result can be found by looking up the ROM table using s (α-β) _L as an address. Second
Is the same as that of the first multiplier 100.

Before the adder 108 adds the coarse-precision phase difference PV in the adding circuit 108, the adder 1
04 = Gs × sin (α−β) _L + G
c × cos (α−β) _L is adjusted with the phase difference (PV), so that a sine wave component gain correction value = Gs × sin
(Α−β) _L and cosine wave component gain correction value = Gc × cos
(Α-β) This is a circuit for reducing the added value of _L to 1/8. In this embodiment, since a binary operation is performed, 1/8 may be shifted by 3 bits to the LSB side. That is, the shifter 106 is a binary shift circuit (shift register).

The adder circuit 108 calculates the phase difference (PV) shown in FIG.
A coarse phase difference PV calculated from the table 74 by the table lookup table, and the phase difference PV
Gain correction value of [Gs × sin (α−β) _L + Gc ×
cos (α-β) _L ] / 8.

As a result, the following calculation result is output from the output terminal 96 of FIG. 6 as the phase difference Δφ = (α−β) of the phase difference detector 522.

Δφ = PV + [Gs × sin (α−β) _L + Gc × cos (α−β) _L ] / 8 where PV is a coarse phase difference (first phase difference), and Gs × sin (Α−β) _L is a sine wave component gain correction value, and Gc × cos (α−β) _L is a cosine wave component gain correction value. (4)

As a method of obtaining the sine gain Gs and the cosine gain Gc, one value in the table may be a true value at an effective range, that is, at a boundary of 16 × 16. However, the sine gain Gs and the cosine gain G
Since there are at most 256 combinations with c, in the present embodiment, all the combinations of the sine gain Gs table 76 and the cosine gain Gc that have the smallest error with the true value are searched. I applied what I did. More specifically, in the present embodiment,
Using a set of the sine gain Gs and the cosine gain Gc, the sum of errors in a range where the phase difference Δφ = (α−β) is calculated is used as an evaluation function, and the sine gain G is set so that the evaluation function is minimized.
s and the cosine gain Gc were determined. According to this method, the optimum sine gain (Gs) table 76 and cosine gain (Gc) table 78 can be created without considering the error in the intermediate calculation.

Basic phase difference detector and improved phase difference detector
Contrast first method (the basic method) by the phase difference detector 522 (this is called a basic phase difference detector), for comparing the improved phase detector. First, the memory capacities are compared. According to the basic method, the table of the phase difference detector 522 is created by the method shown in FIG. 4 and the phase difference (PV) table 74, the sine gain (Gs) table 76, the cosine gain ( Gc) The memory capacity when the table 78 is created is compared. As described above, according to the basic method, a memory having a capacity of 64 Kbytes is required for a signed 8-bit depth. In the improved phase difference detector 522 illustrated in FIG. 5, 16 × 16 × 8 bits = 2048 bits as the phase difference (PV) table 74 and 16 × 16 as the sine gain (Gs) table 76.
× 4 bits = 1024 bits, 16 × 16 × 4 bits = 1024 bits as a cosine gain (Gc) table 78, a total of 4096 bits, that is, 4K bits, 0.
It is only 5K bytes. That is, the memory capacity of the improved phase difference detector 522 is 0.8% of the memory capacity of the basic type phase difference detector 522 = 64 Kbytes.

The circuit shown in FIG. 5 and FIG.
FIG. 8 illustrates the result of calculating φ = (α−β). In this example, a constant frequency sine wave is converted to an improved phase difference detector 522.
2 illustrates a simulation result and a true result as input signals of FIG. The true result and the simulation result are represented as almost one curve, and it is difficult to distinguish the differences. In other words, the results from the improved phase difference detector 522 are very close to the true values. The average error of calculating the phase difference Δφ = (α−β) as a result of the improved phase difference detector 522 for all input values is 1.1.
5 °. When the absolute value of the input signal is small, the error increases, but when the amplitude of the value of the input signal is too small, the value of the input signal has low reliability and is often meaningless. Therefore, the improved phase difference detector 52 has a sine and cosine value amplitude of 38 to 100% of the full scale.
The result of the simulation for No. 2 is that the average error is 0.64 °, the signed difference is 8 bits, and the phase difference Δφ =
The quantization error when expressing (α−β) is about 92% with respect to 0.78 °, which is a very accurate result. In other words, using the table illustrated in FIG. 5, the phase difference (PV) table 74, the sine (sin) gain (Gs) table 76, and the cosine (cos) gain (Gc) table 78, the phase difference PV and the sine gain Gs And cosine gain Gc were calculated, and the gain was corrected by the circuit shown in FIG. 6, and finally the operation of Expression 4 was performed, whereby an optimal result was obtained.

The improved phase difference detector 522 includes the arithmetic circuit illustrated in FIG. 6, that is, a first multiplier 100, a second multiplier 102, an adder 104, a shifter 106, and an adder circuit 108. Phase difference (PV) illustrated in FIG.
Since only the table 74, the sine gain (Gs) table 76 and the cosine gain (Gc) table 78 are provided, the circuit configuration is simple. Also, the first multiplier 100
Except for the operation of the second multiplier 102 and the operation of the second multiplier 102, only the operation is quick and simple, so that the operation time is also quick.

First multiplier 100 and second multiplier 1
02 can also be table processed using a ROM. That is, even if the first multiplier 100 calculates the sine wave component gain correction value: Gs × sin (α−β) _L , the range of the values of the sine gain Gs and cos (α−β) _L is known. Therefore, the corresponding sine wave component gain correction value stored in the ROM table in advance using these values as addresses is given by: GGs × sin (α−β) _L
May be read out by a table lookup method. Similarly, for the second multiplier 102, the cosine wave component gain correction value = Gc from the ROM table by the table lookup method.
× cos (α-β) _L is read out. As described above, since the first multiplier 100 and the second multiplier 102 are also stored in the ROM table, the circuit configuration of the improved phase difference detector 522 is further simplified, and the operation time is further shortened.

The phase difference (PV) table 74, sine gain (Gs) table 76, and cosine gain (Gc) table 78 shown in FIG. 5 can be stored in one memory, for example, a ROM. Further, when the first multiplier 100 and the second multiplier 102 are tabulated, they can be realized by one memory, for example, a ROM. More preferably, in addition to the phase difference (PV) table 74, sine gain (Gs) table 76 and cosine gain (Gc) table 78 illustrated in FIG. 5, the first multiplier 100 and the second multiplier 102 are provided. The tabulated portion can also be integrated into one ROM.

In the above embodiment, the phase difference detector 52
2, in particular, the improved phase difference detector 522 has been described with respect to signed 8-bit data. However, the present invention is not limited to signed 8-bit data.
The same applies to 0 bits. In that case, sin (α
−β) _H is, for example, the upper 5 bits, sin (α−β)
_L is, for example, using lower 5 bits of data,
(Α-β) _H uses the upper 5 bits, and cos (α-β) _L uses the lower 5 bits.

Loop Filter The digital loop filter 54 illustrated in FIG. 3 filters the phase difference Δφ = (α−β) with a predetermined filter characteristic. The digital filter processing in the loop filter 54 can be performed by a transversal filter of a FIR type or the like in which a known multiplication circuit of delay elements is connected in a plurality of stages in a ladder type. In the phase synchronization circuit 50, it is not essential to provide the loop filter 54, but it is usually provided.

Voltage Controlled Oscillator (VCO) The digital voltage controlled oscillator (VCO) 56 passes through the digital loop filter 54 and responds to low frequency components to generate oscillation signals of sin (β) and cos (β). Generate Specific oscillation signal sin in VCO 56
(Β) and cos (β) are generated by a phase difference Δφ
= (Α−β) as a parameter, sin (β), cos
(Β) is posted in advance, the result is stored in a memory such as a ROM, and the phase difference Δφ = (α−β)
It is preferable to use a table lookup method for reading out the data of sin (β) and cos (β) from the viewpoint of shortening the operation time and simplifying the circuit configuration.

Phase Synchronization Circuit 50 The digital phase synchronization circuit 50 illustrated in FIG. 3 includes a complex multiplier 521 described with reference to FIG. 3 and a phase difference detector 522 described with reference to FIGS. In particular, a phase comparator 52 having an improved phase difference detector 522, a digital loop filter 54, and a digital voltage controlled oscillator (V
CO) 56, a complex multiplier 521, a phase difference detector 522 (in particular, an improved phase difference detector 522), a loop filter 54, and a voltage controlled oscillator (VCO) 5
6, the digital phase-locked loop 50 can be configured by a simple circuit with a small memory capacity. In particular, constituting the phase synchronization circuit 50,
The complex multiplier 521, the improved phase difference detector 522, the loop filter 54, and the like are tabulated by using a plurality of ROMs. The structure can be further simplified. Further, as described above, since the main circuits constituting the phase locked loop circuit 50 employ the table lookup method except for simple calculations, the calculations can be performed in a very short time.

Optical disk drive / servo system (device) 1
As an embodiment of the present invention, the digital synchronizing circuit (PLL) 26 in the optical disk drive / servo system (device) 10 described with reference to FIG.
Since the phase synchronization circuit 50 can be applied, the optical disk drive / servo system (apparatus) 10 as a whole can be configured with a small memory capacity, can perform calculations in a very short time, and can perform the operation in a very short time. The effect is that the circuit configuration is very simple as a whole. As a result, the phase difference Δφ = (α−β) between the tracking error signal TE and the cross track signal CTS can be calculated without lowering the accuracy, and the price of the optical disk drive / servo system (device) 10 is reduced. be able to.

The present invention is not limited to the above embodiment. For example, as the above-described embodiment, a case where the phase synchronization circuit 50 using the phase comparator 52 having the complex multiplier 521 and the improved phase difference detector 522 is applied to the optical disk drive / servo system (device) 10 will be described. However, the application of the phase difference detection circuit, phase comparator, and phase synchronization circuit of the present invention to the optical disk drive / servo system (apparatus) 10 is not limited, and can be applied to various fields as a digital phase synchronization circuit. .

[0078]

According to the phase difference detecting circuit of the present invention, it is possible to configure with a small memory capacity without deteriorating the accuracy, to perform the operation in a very short time, and to configure with a simple circuit configuration. To play. According to the phase difference detection method of the present invention, a phase difference can be calculated in a short time without reducing accuracy.

Further, according to the phase comparator having the phase difference detection circuit and the complex multiplier of the present invention, the configuration can be made with a small memory capacity without lowering the accuracy, and the operation can be performed in a very short time. Also, there is an effect that the circuit configuration is very simple.

Further, according to the phase locked loop having the phase comparator of the present invention, it is possible to configure with a small memory capacity,
The operation can be performed in a very short time, the circuit configuration is very simple, and the accuracy of phase synchronization does not decrease.

Further, according to the optical disk drive / servo system (apparatus) using the phase synchronization circuit of the present invention, the phase difference between the tracking error signal TE and the cross track signal CTS can be detected with high accuracy, and the memory capacity is small. The operation can be performed in a very short time.
This has the advantage that the circuit configuration is very simple.

[Brief description of the drawings]

FIG. 1 is a general optical disc drive / servo system (apparatus) using a phase difference detection circuit of the present invention, a phase comparator having the phase difference detection circuit, and a phase synchronization circuit using the phase synchronization circuit. FIG.

FIG. 2 is a circuit configuration diagram of a phase locked loop as a general circuit of the phase locked loop illustrated in FIG. 1;

FIG. 3 is a diagram illustrating a more specific circuit configuration example of the phase locked loop circuit illustrated in FIG. 2;

4 is a diagram illustrating a relationship between coordinates and a memory table in the basic type phase difference detection circuit illustrated in FIG. 3;

5 is a first partial circuit configuration diagram of an improved phase difference detector of the phase detector illustrated in FIG. 3;

FIG. 6 is a second partial circuit configuration diagram of the improved phase difference detection circuit of the phase detector illustrated in FIG. 3;

FIG. 7 is a diagram illustrating a relationship between coordinates and a memory table in the improved phase difference detection circuit.

FIG. 8 is a graph illustrating a simulation result of the improved phase difference detection circuit.

[Explanation of symbols]

 10 optical disk drive / servo system (device) 12 optical disk 14 spindle motor 16 optical detector 18 semiconductor laser 20 tracking coil 22 first A / D converter 24 Second A / D converter 26 Phase synchronization circuit (PLL) 28 Traverse counter 30 Switching decision device 32 Phase compensation circuit 34 D / A converter 36 Drive amplifier (Dry amplifier) ) 40 ... Phase locked loop 42 ... Phase comparator 44 ... Loop filter 46 ... Voltage controlled oscillator (VCO) 50 ... Digital phase locked loop 52 ... Digital phase comparator 521 ... Digital complex multiplication 522 Digital phase difference detector 54 Digital loop filter 56 Digital voltage controlled oscillator (V O) 74 ··· phase difference (PV) table 76 ··· sine (sin) gain (Gs) table 78 ··· cosine (Gc) table 100 ··· first multiplier 102 ··· second multiplication Unit 104 adder 106 shifter 108 adder circuit

Continued on the front page F term (reference) 2G030 AA01 AD08 AG00 5D066 FA01 5D118 AA03 AA14 BA01 CA02 CA13 CA24 CB01 CB03 CD03 5J106 AA04 BB03 CC01 CC26 CC41 DD12 DD13 DD17 DD33 DD35 DD36 JJ02 KK02 KK05 KK39 LL02

Claims (17)

[Claims] 1. A first digital signal of a first bit which changes in a sine wave shape having a function of a phase difference and a cosine wave function which has a function of the phase difference which is substantially orthogonal to the first digital signal. A digital phase difference detection circuit for detecting the phase difference from the first digital signal of the first bit, wherein the data of the predetermined bit of the first bit of the first digital signal , First upper data) and phase difference calculating means for calculating a first phase difference from data of the predetermined bit of the first bit of the second digital signal (hereinafter, second upper data) Calculating a sine wave component gain from the first higher-order data and the second higher-order data, and adding the remaining lower order of the first higher-order data of the first digital signal to the calculated sine wave component gain. Sine wave component gain correction value calculating means for calculating a sine wave component gain correction value by multiplying the sine wave component gain data (hereinafter referred to as first lower data), and a cosine from the first higher data and the second higher data. A wave component gain is calculated, and the calculated cosine wave component gain is multiplied by remaining low-order bit data (hereinafter, second lower data) of the first upper data of the second digital signal to obtain a cosine wave component. Cosine wave component gain correction value calculating means for calculating a gain correction value; the first phase difference; and the sine wave component gain correction value;
An adder for adding the cosine wave component gain correction value to the cosine wave component gain correction value. 2. The sine wave component according to claim 2, wherein said phase difference calculating means includes readable first table means having said first phase difference as an address of said first higher-order data and said second upper-order data. Gain correction value calculating means, a second table means capable of reading the sine wave component gain as the first higher-order data and the second higher-order data as an address, and a sine wave read out from the second table. First multiplication means for multiplying the component gain by the first lower data, and the cosine wave component gain correction value calculating means calculates the cosine wave component gain by the first higher data and the second higher data. Third table means capable of reading data as an address, and second multiplying means for multiplying the cosine wave component gain read from the third table by the second lower data. Phase difference detecting circuit according to claim 1, wherein that. 3. The first addition means for adding the sine wave component gain correction value and the cosine wave component gain correction value, and the addition result of the first addition means and the first addition result. 2. The phase difference detecting circuit according to claim 1, further comprising: digit matching means for performing digit matching with a phase difference; and second adding means for adding the digitized addition result and the first phase difference. 4. A first digital signal of a first bit which changes in a sine wave shape having a function of a phase difference and a cosine wave function having a function of the phase difference which is substantially orthogonal to the first digital signal. A phase difference detection method for detecting the phase difference from a first digital signal of a first bit, the data of the predetermined bit (hereinafter, the first bit) of the first bit of the first digital signal. Calculating a first phase difference from data of the predetermined bit (hereinafter, second upper data) of the first bit of the second digital signal, and calculating the first phase difference; A sine wave component gain is calculated from the data and the second higher-order data, and data of the remaining lower bits of the first higher-order data of the first digital signal (hereinafter referred to as first sine wave component gain) is calculated. Under Data) to calculate a sine wave component gain correction value, calculate a cosine wave component gain from the first higher-order data and the second upper-order data, and add the second digital value to the calculated cosine wave component gain. Multiplying the remaining lower bit data (hereinafter, second lower data) of the first higher data of the signal to calculate a cosine wave component gain correction value; A phase difference detection method for adding the sine wave component gain correction value and the cosine wave component gain correction value. 5. A first sinusoidal digital signal of a first bit which changes in a sinusoidal manner as a function of a first phase (α) and said first digital signal which is substantially orthogonal to said first digital signal.
And a first signal to be compared having a first bit of a second sinusoidal digital signal that changes in a cosine waveform with a phase as a function, and a sine wave that changes in a sine wave with a second phase (β) as a function. A 1-bit second digital signal and a first-bit second cosine-wave digital signal that changes in a cosine wave function that is a function of the second phase and that is substantially orthogonal to the second sine-wave digital signal. A phase comparator for detecting a phase difference (α-β) with a second comparison target signal, comprising: a complex multiplier and a phase detector, wherein the complex multiplier has a first sine wave shape. A first signal comprising a digital signal and said first cosine-wave digital signal;
And a second signal including the second sine wave digital signal and the second cosine wave digital signal.
And a first digital complex signal of a first bit that changes in a sine wave shape having a function of a phase difference between the first phase and the second phase and the first digital complex signal. A digital complex signal and a second digital complex signal of a first bit that changes in the form of a cosine wave having a function of the phase difference substantially orthogonal to the digital complex signal; Data of the predetermined bit of the first bit (hereinafter, first upper data)
And phase difference calculating means for calculating a first phase difference (PV) from data of the predetermined bits (hereinafter, second upper data) of the first bits of the second digital complex signal; Calculating a sine wave component gain from the first higher-order data and the second higher-order data; and adding the remaining lower bit data of the first higher-order data of the first digital complex signal to the calculated sine wave component gain (Hereinafter referred to as first lower-order data) to calculate a sine-wave component gain correction value by multiplying the first higher-order data and the second upper-order data by a cosine wave component gain. The calculated cosine wave component gain is multiplied by the remaining lower bit data (hereinafter referred to as second lower data) of the first higher data of the second digital complex signal to calculate the cosine wave component gain. And the cosine wave component gain correction value calculating means for calculating the emission correction value, wherein the first phase difference, and the sine wave component gain correction value,
A first adding means for adding the cosine wave component gain correction value. 6. The complex operation in the complex multiplier is defined by the following equation: sin (α-β) = sin (α) × cos (β) -co
s (α) × sin (β) cos (α−β) = cos (α) × cos (β) + si
n (α) × sin (β) where sin (α) is the first sine wave digital signal, cos (α) is the first cosine wave digital signal, and sin (β) is the 6. The phase comparator according to claim 5, wherein the second digital signal is a sinusoidal digital signal, and cos (β) is the second cosine digital signal. 7. The complex multiplier according to claim 1, wherein the first digital signal and the second digital signal are sin (α) ×
cos (β) is stored in the first
And cos (α) × for all of the first cosine wave digital signal and the second sine wave digital signal.
The second in which the result of previously calculating sin (β) is stored.
And cos (α) × for all of the first cosine-wave digital signal and the second cosine-wave digital signal.
cos (β) is stored in the third
And sin (α) × for all of the first sine wave digital signal and the second sine wave digital signal.
The fourth in which the result of previously calculating sin (β) is stored.
, A first subtraction means, and a second addition means, wherein the first table means stores the first sine wave digital signal at a first address, and the second cosine wave digital signal. When the signal is applied as a second address, a corresponding sin (α) × cos (β) result stored in the memory defined by these addresses is output, and the second table means outputs When one cosine wave digital signal is applied as a first address and the second sine wave digital signal is applied as a second address, the corresponding cos (α) × stored in a memory defined by these addresses. The third table means outputs the result of sin (β), the first cosine-wave digital signal is a first address, and the second cosine-wave digital signal is a second address. And outputs the result of the corresponding cos (α) × cos (β) stored in the memory defined by these addresses, and the fourth table means outputs the first sine wave When the digital signal is applied as the first address and the second sinusoidal digital signal is applied as the second address, the corresponding sin (α) × sin (β is stored in the memory defined by these addresses. ), Wherein the subtraction means calculates sin (α-β) by subtracting the result output from the second table means from the result output from the first table means, 7. The phase comparator according to claim 6, wherein said adding means calculates cos (α-β) by adding the result output from said third table means and the result output from said fourth table means. 8. The phase difference calculating means includes a readable fifth table means using the first phase difference (α-β) as an address of the first upper data and the second upper data. The sine wave component gain correction value calculating means calculates the sine wave component gain (Gs) using the first upper data and the second higher data.
And a first multiplying means for multiplying the sine-wave component gain read from the sixth table by the first lower-order data, the sixth cosine table comprising: The wave component gain correction value calculation means calculates the cosine wave component gain (Gc) using the first higher-order data and the second
8. A seventh table means which can read out the higher order data as an address, and a second multiplying means which multiplies the cosine wave component gain read out from the seventh table by the second lower order data. Phase comparator. 9. The first addition means for adding the sine wave component gain correction value and the cosine wave component gain correction value, the first addition means comprising: 9. A digit matching means for performing digit matching between the addition result and the first phase difference, and a first two adding means for adding the digit-matched addition result and the first phase difference. The phase comparator as described. 10. A phase-locked loop comprising: phase comparing means; and voltage-controlled oscillating means for applying an oscillation signal according to a phase difference from the phase comparator to the phase comparator. Has a complex multiplier and a phase detector, and has a first sinusoidal digital signal of a first bit that changes in a sinusoidal shape with the first phase as a function, and is substantially orthogonal to the first digital signal. A first comparison target signal having a first bit of a second sinusoidal digital signal that changes in a cosine waveform with a function of the first phase, and a second phase input from the voltage-controlled oscillator, And a second bit of a first bit that changes in a sinusoidal waveform and a first bit that changes in a cosine waveform with a function of the second phase that is substantially orthogonal to the second digital signal. Of the second cosine wave A phase comparator for detecting a phase difference with a second comparison target signal having a digital signal, wherein the complex multiplier converts the first sine-wave digital signal and the first cosine-wave digital signal with each other. First including
And a second signal including the second sine wave digital signal and the second cosine wave digital signal.
And a first digital complex signal of a first bit that changes in a sine wave shape having a function of a phase difference between the first phase and the second phase and the first digital complex signal. A digital complex signal and a second digital complex signal of a first bit that changes in the form of a cosine wave having a function of the phase difference substantially orthogonal to the digital complex signal; Data of the predetermined bit of the first bit (hereinafter, first upper data)
And phase difference calculating means for calculating a first phase difference (PV) from data of the predetermined bits (hereinafter, second upper data) of the first bits of the second digital complex signal; Calculating a sine wave component gain from the first higher-order data and the second higher-order data; and adding the remaining lower bit data of the first higher-order data of the first digital complex signal to the calculated sine wave component gain (Hereinafter referred to as first lower-order data) to calculate a sine-wave component gain correction value by multiplying the first higher-order data and the second upper-order data by a cosine wave component gain. The calculated cosine wave component gain is multiplied by the remaining lower bit data (hereinafter referred to as second lower data) of the first higher data of the second digital complex signal to calculate the cosine wave component gain. And the cosine wave component gain correction value calculating means for calculating the emission correction value, wherein the first phase difference, and the sine wave component gain correction value,
A first adding means for adding the cosine wave component gain correction value and the cosine wave component gain correction value. 11. The voltage controlled oscillator uses a phase difference from the phase comparator as an address and changes in a sine wave shape having a function of a corresponding second phase stored in a memory specified by the address. The 1-bit second digital signal and the first bit of the second cosine-wave digital signal which changes in a cosine wave function as a function of the second phase which is substantially orthogonal to the second sine-wave digital signal. 11. The phase-locked loop according to claim 10, further comprising first table means for outputting the following. 12. The complex operation in the complex multiplier is defined by the following equation: sin (α-β) = sin (α) × cos (β) -co
s (α) × sin (β) cos (α−β) = cos (α) × cos (β) + si
n (α) × sin (β) where sin (α) is the first sine wave digital signal, cos (α) is the first cosine wave digital signal, and sin (β) is the The phase-locked loop circuit according to claim 11, wherein the second digital signal is a sinusoidal digital signal, and cos (β) is the second cosine digital signal. 13. The complex multiplier according to claim 1, further comprising: for each of the first sine wave digital signal and the second cosine wave digital signal, sin (α) ×
cos (β) is stored in the second
And cos (α) × for all of the first cosine wave digital signal and the second sine wave digital signal.
The third in which the result of previously calculating sin (β) is stored.
And cos (α) × for all of the first cosine-wave digital signal and the second cosine-wave digital signal.
The fourth which stores the result of previously calculating cos (β)
And sin (α) × for all of the first sine wave digital signal and the second sine wave digital signal.
The fifth which stores the result of previously calculating sin (β)
, A first subtracting means, and a second adding means, wherein the second table means stores the first sine wave digital signal at a first address, and the second cosine wave digital signal. When the signal is applied as a second address, a corresponding sin (α) × cos (β) result stored in a memory defined by these addresses is output, and the third table means outputs When one cosine wave digital signal is applied as a first address and the second sine wave digital signal is applied as a second address, the corresponding cos (α) × stored in a memory defined by these addresses. The fourth table means outputs the first cosine wave digital signal to a first address, and outputs the second cosine wave digital signal to a second address. And outputs the result of the corresponding cos (α) × cos (β) stored in the memory defined by these addresses, and the fifth table means outputs the first sine wave When the digital signal is applied as the first address and the second sinusoidal digital signal is applied as the second address, the corresponding sin (α) × sin (β is stored in the memory defined by these addresses. ), And the subtraction means calculates sin (α-β) by subtracting the result output from the third table means from the result output from the second table means, 13. The phase synchronization circuit according to claim 12, wherein the adding means calculates cos (α-β) by adding the result output from the fourth table means and the result output from the fifth table means. 14. The sine wave component, wherein the phase difference calculating means includes readable fifth table means using the first phase difference as an address of the first high-order data and the second high-order data. Gain correction value calculating means for reading the sine wave component gain from the first high-order data and the second high-order data as an address, a sixth table means; and a sine wave component read from the sixth table. First multiplying means for multiplying a gain by the first lower data, wherein the cosine wave component gain correction value calculating means calculates the cosine wave component gain by the first higher data and the second higher data. Seventh table means readable as an address, and second multiplication means for multiplying the cosine wave component gain read from the seventh table by the second lower data. Phase locked loop of claim 13, wherein. 15. The first adding means for adding the sine wave component gain correction value and the cosine wave component gain correction value, and the first one adding means. 15. A digit matching means for performing digit matching between a result and the first phase difference, and a first two adding means for adding the digitized addition result and the first phase difference. Phase synchronization circuit. 16. An optical disk drive / servo having a digital phase synchronization circuit used in an optical disk drive / servo system for detecting a phase relationship between a tracking error signal and a cross track signal orthogonal to the tracking error signal. And a digital phase comparator, and a digital voltage controlled oscillator for applying an oscillation signal corresponding to a phase difference from the digital phase comparator to the digital phase comparator, wherein the digital phase comparator comprises: A tracking error signal of a first bit which changes in a sine wave form having a complex multiplier and a phase detector as a function of the first phase, and the first phase substantially orthogonal to the tracking error signal. A first bit cross track signal varying in a cosine waveform as a function; Input from control type oscillator, the first of the first bit that changes sinusoidally to a second phase corresponding to the tracking error signal function
, And a phase difference (α−
β), wherein the complex multiplier performs a complex operation of the tracking error signal and the cross track signal, and the first digital signal and the second digital signal. A first digital complex signal of a first bit, which changes in a sine wave form as a function of a phase difference between the first phase and the second phase, and the first digital complex signal, which is substantially orthogonal to the first digital complex signal; A second digital complex signal of a first bit which changes in a cosine wave function as a function of a phase difference, wherein the phase detector comprises: a first bit of the first digital complex signal; Bit data (hereinafter, first upper data)
And phase difference calculating means for calculating a first phase difference from data of the predetermined bits (hereinafter, second higher-order data) of the first bits of the second digital complex signal; A sine wave component gain is calculated from the high-order data and the second high-order data. Sine wave component gain correction value calculating means for calculating a sine wave component gain correction value by multiplying the first higher data and the second higher data, and calculating a cosine wave component gain from the first higher data and the second higher data. The calculated cosine wave component gain is multiplied by the remaining lower bit data (hereinafter, second lower data) of the first higher data of the second digital complex signal to correct the cosine wave component gain. And the cosine wave component gain correction value calculating means for calculating, said the first phase difference, and the sine wave component gain correction value,
An optical disc drive / servo device, comprising: first addition means for adding the cosine wave component gain correction value. 17. The voltage-controlled oscillator according to claim 1, wherein the phase difference from the phase comparator is used as an address, and the voltage-controlled oscillator changes in a sinusoidal waveform having a function of a corresponding second phase stored in a memory defined by the address. The 1-bit second digital signal and the first bit of the second cosine-wave digital signal which changes in a cosine wave function as a function of the second phase which is substantially orthogonal to the second sine-wave digital signal. 17. The optical disk drive / servo apparatus according to claim 16, further comprising table means for outputting the following.