JP2000069418A5 - - Google Patents

Description

The encoder / decoder 15 compresses (encodes) or decompresses (decodes) image data. For example, when processing a still image, JPEG (Joint Photographic Experts Group) is used, when processing video, MPEG (Moving Picture Experts Group) is used. Here, it is assumed that the encoder / decoder 15 compresses or decompresses image data by JPEG. However, the encoder / decoder 15 may have a function corresponding to both coding methods. Further, regarding JPEG, encoding / decoding may be performed by software processing of the CPU 12.

After displaying the captured image for a predetermined time, the CCD2 is set to the EtoE mode, the switch SW2 of the memory controller 5 is set to the input terminal c , the display is returned to the image being captured, and the image in the DRAM 9 is encoded by the encoder / The decoder 15 (or CPU 12) JPEG-compresses the image and writes it to the external storage medium 11 via the interface 10.

FIG. 13 shows an example of a specific configuration of the horizontal pixel number conversion units 51 and 54. Three 1-pixel delay elements 20 are connected in series, four taps are derived from the series connection, a multiplier 21 is connected to each tap, the multiplication output of the multiplier 21 is added by the adder 22, and the adder is added. The output signal is taken out from 22. Coefficients a0, a1, a2, and a3 are supplied to the multiplier 21 from the coefficient switching unit 23. The coefficient switching unit 23 uses the output corresponding to the pixel position of the pixel position counting unit 24 to generate a coefficient corresponding to the pixel position and the thinning process or the interpolation process. FIG. 13 shows a 4-tap FIR filter configuration, in which a required number of taps are provided according to a calculation accuracy requirement. The combination of coefficients is switched according to each image size. In FIG. 1 0, and the image capture mode, are represented separately circuit between image reproduction mode, in fact, to distinguish a common circuit by mode.

FIG. 14 shows an example of a specific configuration of the vertical line number conversion units 52 and 55. Three 1-line delay elements 25 are connected in series, four taps are derived from the series connection, a multiplier 26 is connected to each tap, the multiplication output of the multiplier 26 is added by the adder 27, and the adder The output signal is taken out from 27 . Coefficients b0, b1, b2, and b3 are supplied to the multiplier 26 from the coefficient switching unit 28. The coefficient switching unit 28 uses the output corresponding to the number of lines of the number of lines counting unit 29 to generate a coefficient corresponding to the number of lines. FIG. 14 shows a 4-tap FIR filter configuration, in which a required number of taps are provided according to a calculation accuracy requirement. The combination of coefficients is switched according to each image size. The 1-line delay element 25 requires 1270 pixels, which is one horizontal period of the CCD2. For example, in the case of a 4: 2: 2 component signal, 1,270 × 3 × 2 = 7,620 bytes of memory are required for one line delay. In FIG. 1 0, and the image capture mode, are represented separately circuit between image reproduction mode, in fact, to distinguish a common circuit by mode.

Next, a method of performing pixel number conversion by software processing will be described. Since the pixel number conversion when capturing each VGA, CIF, and QCIF image is performed by software, the configuration of the memory controller 5 is greatly simplified as shown in FIG. That is, the switch SW1 selects the input terminal b in the image capture mode, and selects the input terminal a in the EtoE mode and the playback mode. Regardless of the captured image size mode, all in XGA data is captured against DRAM 9, converts the data in the DRAM 9 by a software processing. In the playback mode, the switch SW2 selects the input terminal d, and in the EtoE mode, the switch SW2 selects the input terminal c.

In step S6, the CPU 12 checks the size of the captured image in order to perform the pixel number conversion. In the case of other than XGA, in step S7, horizontal / vertical pixel number conversion (captured image) is performed according to each image size. In step S 8, performs horizontal and vertical pixel number conversion (display image) corresponding to each image size. Further, in step S6, the image size is in the case of XGA, the process proceeds to step S 8 skips step S 7. The horizontal / vertical pixel number conversion (captured image) and horizontal / vertical pixel number conversion (display image) processing are shown in FIG. 11, and these pixel number conversion processing is performed by software.

In step S51, the image capture operation is completed, and then the mode shifts to the confirmation playback mode. The image size is checked in step S52, and if the image size is QCIF, the number of lines in the DRAM 9 is read out as it is . When the image size is determined to be other than QCIF in step S52, simple thinning out reading is performed in step S53. The simple thinning-out reading is a process of thinning out the number of lines by making the reading address in the vertical direction generated by the address generation unit 53 intermittent when reading data from the DRAM 9.

In FIG. 7, the white circles are the pixels resulting from the horizontal pixel number conversion of the image (XGA) taken by the CCD2, and the triangles are the VGA pixels to be obtained by the conversion. In order to calculate the VGA pixel a by interpolation, four XGA pixels surrounded by a broken line are used. The vertical line conversion process by software will be described by taking 2/3 line thinning from XGA to VGA as an example. In FIG. 8, Yn indicates a line before conversion, yno indicates an odd line after conversion, and yne indicates an even line after conversion.

On the other hand, in one embodiment of the present invention
Circuit scale Memory 3Byte (horizontal pixel count converter)
(3810Byte (number of vertical lines converting unit) content reduction)
Multiplication circuit 4 (horizontal pixel number conversion unit)
(4 (number of vertical lines converting unit) content reduction)
Addition circuit 3 (horizontal pixel number conversion unit)
(3 (number of vertical lines converting unit) content reduction)
Not required for software processing playback Multiplication 640 x480 x4 = 1,228,800
Add 25% of all software methods 640 x 480 x 4 = 1,228,800
All are 25% of the software method.

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