JP2000068496A - Manufacture of bipolar transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the change in characteristics and deterioration in reliability by forming first and second semiconductor films on a silicon substrate, injecting impurities with a member corresponding to an emitter region formed on the second semiconductor film as a mask, and introducing impurities of opposite conductivity to that of the collector region into the collector region. SOLUTION: A silicon oxide film 2 which is to be an element isolation region is formed on a silicon substrate 1 having a bipolar transistor forming region 3, and then after an excessive silicon oxide film 2 on a surface of the bipolar transistor forming region 3 is removed, a first P-type silicon film 4 is grown as a first semiconductor film. Subsequently, a second silicon film 5 of N-type is grown as a second semiconductor film. Impurities are introduced with a silicon oxide film 6, corresponding to an emitter region formed on the second silicon film 5 as a mask, and impurities of opposite conductivity to that of a collector region are introduced into the collector region.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a bipolar transistor, and more particularly to a method for manufacturing a high-performance bipolar transistor such as a self-aligned bipolar transistor or a heterojunction bipolar transistor.

[0002]

2. Description of the Related Art Conventionally, bipolar transistors have been used as circuit elements having characteristics of high speed and high current capacity.

One type of particularly high performance bipolar transistor is a self-aligned base transistor, one example of which is US Pat.
No. 32. Here, a method is disclosed for forming raised subcollectors, intrinsic bases and emitters by implantation through an implantation window.

Further, there is a method of forming a heterojunction to improve the performance of a bipolar transistor. Providing such a heterojunction in a silicon transistor requires a wide bandgap material (GaP, S grown on the base).
A method using iC, amorphous Si) and a method using a material with a narrow band gap (SiGe alloy as a base) have been developed (for example, JP-A-6-77245).

[0005]

However, as described above, when a mask having an opening is used and high-concentration impurities are implanted into the collector through the opening through the base layer immediately below the emitter, the impurity is implanted. At this time, there is a problem that defects are introduced into the base layer. In particular, in the case of a heterojunction transistor, the composition changes or the amount of strain in the crystal changes due to implantation for self-alignment, and as a result, there arises a problem that the characteristics become unstable.

SUMMARY OF THE INVENTION In view of the above problems, it is a main object of the present invention to provide a method of manufacturing a self-aligned bipolar transistor and a heterojunction bipolar transistor with less change in characteristics and lower reliability.

[0007]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, a method of manufacturing a bipolar transistor according to the present invention comprises introducing an impurity into a current path region when forming a current path when operating the bipolar transistor. Is formed not by ion implantation but by injecting impurities of the opposite conductivity type into regions other than the current path region.

According to this configuration, it is possible to prevent a defect or the like due to impurity ion implantation from being generated in a region serving as a current path when operating the bipolar transistor.

More specifically, a method of manufacturing a bipolar transistor according to the present invention comprises the steps of sequentially forming a first semiconductor film of the other conductivity type and a second semiconductor film of the one conductivity type on a silicon substrate of one conductivity type. And implanting impurities of the other conductivity type using a member corresponding to the emitter region formed on the second semiconductor film as a mask, and introducing an impurity of a conductivity type opposite to that of the collector region into the collector region. It has a configuration.

More specifically, a step of sequentially forming a first semiconductor film of another conductivity type and a second semiconductor film of one conductivity type on a silicon substrate of one conductivity type;
Forming a film capable of selective etching with the emitter electrode film on the semiconductor film of the above, and removing the portion corresponding to the bipolar transistor formation region of the film capable of selective etching, forming an emitter electrode film, Further removing the part of the emitter electrode film to form an emitter electrode;
Implanting impurities of the other conductivity type at least using the emitter electrode as a mask, and introducing an impurity of a conductivity type opposite to that of the collector region into the collector region; or Forming a first semiconductor film and a second semiconductor film of one conductivity type sequentially, and selectively etching the second semiconductor film with a portion corresponding to a bipolar transistor formation region on the second semiconductor film. Forming a film capable of performing the etching, and performing impurity implantation of the other conductivity type using at least the film capable of the selective etching as a mask, and introducing an impurity of a conductivity type opposite to that of the collector region into the collector region; Removing a film capable of forming an emitter electrode and forming an emitter electrode in that region.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a bipolar transistor according to an embodiment of the present invention will be described below with reference to the drawings. In the example shown below, NPN
The present invention will be described with reference to a bipolar transistor, but the present invention can also be applied to a PNP bipolar transistor.

(First Embodiment) FIG. 1 is a sectional view showing a manufacturing process of a bipolar transistor according to a first embodiment of the present invention. However, FIG. 1 shows a process sectional view of the base and the emitter, and the extraction electrode of the collector can be formed by the same method as the formation of the emitter. Hereinafter, a method for manufacturing a bipolar transistor according to the present embodiment will be described step by step.

First, as shown in FIG. 1A, a silicon oxide film 2 serving as an element isolation region is formed on a silicon substrate 1 by using, for example, the LOCOS method. That is, a bipolar transistor is formed in the bipolar transistor formation region 3. The periphery of the bipolar transistor forming region 3 is an N-type region having an impurity concentration of about 1E ¹⁷ cm ⁻³ , and further deep (lower in the drawing) an N-type high concentration layer (about 1E ¹⁹ cm ^−3). N ⁺ is formed. These structures can be formed by a normal implantation technique and an epitaxial growth technique.

Next, after removing an excess silicon oxide film (including a natural oxide film) on the surface of the bipolar transistor formation region 3 using dilute hydrofluoric acid, the first silicon oxide film is removed using a UHV-CVD method.
As a semiconductor film, a P-type first silicon film 4 (impurity concentration is about 1E ¹⁸ cm ⁻³ ) is epitaxially grown to about 50 nm. Subsequent to the growth, an N-type second silicon film 5 (impurity concentration is about 1E ¹⁹ cm ⁻³ ) is epitaxially grown as a second semiconductor film by about 100 nm. As a result, a bipolar transistor formation region 3 that eventually becomes a collector, a first silicon film 4 that becomes a base, a defect introduction barrier when forming an emitter, a part of an emitter, and a second silicon that becomes a part of a base This means that the film 5 has been formed.

Then, as shown in FIG. 1B, a silicon oxide film 6 of about 100 nm (selection with an emitter electrode film to be formed later) is formed by using a low-temperature silicon oxide film forming technique (for example, AP-CVD method). A film that can be etched) is deposited, and an opening 7 of the emitter is formed using a photolithography technique and a dry etching technique for an oxide film. At this time, although damage and impurity introduction during dry etching are likely to occur under the opening 7 of the emitter, the presence of the second silicon film 5 absorbs defects and affects the original base layer. Not be given.

Next, as shown in FIG. 1C, after removing an excess silicon oxide film with dilute hydrofluoric acid, an N-type doped polysilicon film 8 is deposited to a thickness of about 200 nm. And FIG.
As shown in (d), a photolithography technique and a dry etching technique for the polysilicon film 8 (selective etching)
Is used to form the emitter electrode 9. Reference numeral 13 denotes a resist used when forming the emitter electrode 9.

Next, as shown in FIG. 1E, boron is applied to at least the
By implanting with eV, the first silicon film 4 and the second silicon film 5 other than the emitter electrode 9 are made to have a high-concentration P type (about 1E ²⁰ cm ⁻³ ) to reduce the sheet resistance and finally A region serving as a base extraction electrode is formed. Next, the implantation energy is increased to, for example, 80 KeV.
By implanting boron in the region, P-type boron is introduced into a region other than the lower portion of the emitter electrode 9 in the bipolar transistor formation region 3 to reduce the effective N-type impurity concentration. Density difference (about 8E
¹⁶ cm ^-3 ).

Thereafter, as shown in FIG. 1 (f), an interlayer insulating film (for example, a BPSG film) 10 is formed, and a heat treatment for both activation and diffusion of the impurities introduced up to this step is performed. Specifically, 950 ° C., about 30
By performing the heat treatment for seconds, a structure as shown in FIG. 1 (g) is obtained. This heat treatment must be optimized so that the second silicon film 5 becomes N-type or P-type and a good PN junction interface can be formed. As a result, the impurity concentration at the interface between the emitter and the base is reduced to about 1E ²⁰ cm ^-3 . Become.

Next, as shown in FIG. 1H, after opening contact holes 11 for forming respective electrodes of a base, an emitter, and a collector, an aluminum film is deposited by a sputtering method, and an aluminum electrode 12 is formed by photolithography. The bipolar transistor is completed by using a brazing technique and an aluminum film dry etching technique.

According to the bipolar transistor of the present embodiment as described above, the current path can be narrowed and the base-collector capacitance can be reduced by compensating the collector portion other than the vicinity of the emitter electrode 9 with the reverse impurity. at the same time,
It is not necessary to implant impurities into the lower portion of the emitter electrode 9 serving as a current path, and it is possible to prevent a defect due to the impurity ions from being implanted in the base region and the like, thereby improving high frequency characteristics. Can be.

In the present embodiment, the device isolation is performed using a silicon oxide film using the LOCOS method. However, a trench isolation method in which a groove is formed in a silicon substrate and an insulator is embedded therein may be used. . The P-type first silicon film 4 was epitaxially grown using the UHV-CVD (ultra high vacuum chemical vapor deposition) method.
The growth may be performed using a BE (molecular beam epitaxy) method.

Further, in order to improve the characteristics, a P-type silicon germanium film may be used instead of the P-type first silicon film 4. In this case, it is necessary to optimize the P-type impurity concentration and the germanium concentration in order to exhibit the performance. Further, the second silicon film 5
Is formed on the silicon germanium film, germanium contamination at the time of device fabrication can be reduced. Further, by forming the second silicon film 5 as extremely thin as about 20 nm, the PN junction interface can be formed almost as designed by making this film a film for preventing defects and impurity contamination. However, it is necessary to separately form a base extraction electrode (for example, using silicide). Since the formation of the base and the emitter is continuous, the matching of the interface is high and a good junction can be formed. If it becomes difficult to form the contact hole 11 on the emitter electrode 9 due to miniaturization in the future, it is possible to form a second N-type doped polysilicon film to form a large electrode on the emitter electrode 9. It is.

(Embodiment 2) A method of manufacturing a bipolar transistor according to Embodiment 2 of the present invention will be described below with reference to the drawings. FIG. 2 is a sectional view showing a manufacturing process of the bipolar transistor according to the present embodiment. In FIG. 2, the same components as those in FIG. 1 are denoted by the same reference numerals.

First, a structure as shown in FIG. 2A is formed. Since this structure is the same as that of FIG. 1A, the description is omitted here. After that, AP-CVD
Silicon oxide film 30 using silane gas (second
Film that can be selectively etched with a silicon film)
Subsequently, a silicon nitride film 31 is deposited to a thickness of about 200 nm by LP-CVD. Next, using the resist pattern 32, the silicon oxide film 30 and the silicon nitride film 31 are removed by dry etching (selective etching) (FIG. 2B).

Next, using the resist pattern 32 as a mask, BF ₂ ions are implanted at an acceleration energy of about 30 keV, and then boron ions are implanted at about 100 keV over the entire surface. As a result, similarly to the above-described first embodiment, the second silicon film 5 is inverted to the P-type, and the concentration of the N-type region other than the lower part of the emitter opening of the bipolar transistor formation region 3 is reduced (FIG. 2 (c)).

Thereafter, a resist pattern 33 covering the base and the base electrode region is formed, and using the resist pattern 33 as a mask, the first silicon film 4 and the second silicon film 5 in the region not covered by the resist pattern are dried. Etching by etching method (Fig. 2
(D)).

Next, after depositing the silicon oxide film 34, sidewalls of the silicon oxide film 34 are formed on the side surfaces of the silicon oxide film 30 and the silicon nitride film 31 by using anisotropic etching of a dry etching method. Silicon film 4
And silicon oxide film 3 on the side surface of second silicon film 5 as well.
4 are formed (FIG. 2E).

Next, a BPSG film 35 is formed as an interlayer insulating film by the AP-CVD method (FIG. 2F). And CM
The substrate surface is flattened by using a P (chemical mechanical polishing) method until the silicon nitride film 31 is exposed (FIG. 2G). Further, the silicon nitride film 31 is removed using hot phosphoric acid at about 150 ° C., and the silicon oxide film 30 is removed using dilute hydrofluoric acid. Here, since the etching rate of the silicon oxide film 30 of the silicon oxide film 30 and the sidewall oxide film 34 is about five times faster, the silicon oxide film 30 can be removed with good controllability (FIG. 2).
(H)).

Thereafter, N-type doped polysilicon is deposited to form an emitter electrode 37 (FIG. 2).
(I)). BPSG by AP-CVD method as interlayer insulating film
After forming the film 36, a heat treatment is performed to activate and diffuse the impurities (FIG. 2 (j)).

Finally, after opening contact holes 11 for forming respective electrodes of a base, an emitter, and a collector, an aluminum film is deposited by a sputtering method, and an aluminum electrode 1 is formed.
2 is formed by using a photolithography technique and a dry etching technique for an aluminum film (FIG. 2 (k)) to complete a bipolar transistor.

As described above, according to the present embodiment, in addition to the effects of the first embodiment, since the base-emitter and base-collector regions can be formed in a self-aligned manner, the characteristics can be stabilized even if the device is miniaturized. It is possible to take out.

[0032]

As described above, the present invention relates to a bipolar transistor having a substantially self-aligned collector by implanting a reverse impurity into the collector side using the emitter electrode portion as a mask when fabricating a high performance bipolar transistor. Can be formed, and it is possible to suppress a change in composition and a change in characteristics of a bipolar transistor having a defect or a heterojunction formed in a device region which becomes a problem at the time of implantation, thereby providing an element having stable characteristics.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a manufacturing process of a bipolar transistor according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing a manufacturing process of the bipolar transistor according to the second embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Element isolation silicon oxide film 3 Bipolar transistor formation region 4 First silicon film 5 Second silicon film 6,30,34 Silicon oxide film 7 Emitter opening 8 N-type doped polysilicon film 9 Emitter electrode 10 Interlayer insulating film 11 Contact hole 12 Aluminum electrode 31 Silicon nitride film 35, 36 BPSG film 37 Emitter electrode

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Akira Asai 1006 Kadoma Kadoma, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd.

Claims (4)

[Claims] A step of sequentially forming a first semiconductor film of another conductivity type and a second semiconductor film of one conductivity type on a silicon substrate of one conductivity type, and forming the first semiconductor film and the second semiconductor film of one conductivity type on the second semiconductor film; Implanting impurities of the other conductivity type using a member corresponding to the emitter region as a mask, and introducing an impurity of a conductivity type opposite to that of the collector region into the collector region. A step of sequentially forming a first semiconductor film of another conductivity type and a second semiconductor film of one conductivity type on a silicon substrate of one conductivity type; and forming an emitter electrode film on the second semiconductor film. Forming a film capable of selective etching with
After removing a portion corresponding to the bipolar transistor formation region of the film capable of selective etching, forming an emitter electrode film, further removing a part of the emitter electrode film by selective etching to form an emitter electrode, Implanting impurities of the other conductivity type at least using the emitter electrode as a mask, and introducing an impurity of a conductivity type opposite to that of the collector region into the collector region. 3. A step of sequentially forming a first semiconductor film of another conductivity type and a second semiconductor film of one conductivity type on a silicon substrate of one conductivity type, and forming a bipolar transistor on the second semiconductor film. Forming a film that can be selectively etched with the second semiconductor film in a portion corresponding to a region;
Impurity implantation of the other conductivity type is performed by using at least the film capable of selective etching as a mask, and impurities of a conductivity type opposite to that of the collector region are introduced into the collector region. Then, the film capable of selective etching is removed. Forming an emitter electrode in the bipolar transistor. 4. The method for manufacturing a bipolar transistor according to claim 1, wherein the first semiconductor film is a silicon germanium compound semiconductor film formed by epitaxial growth.