JP2000048600A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To monitor an inner voltage including a boosted voltage and a negative voltage through a simple arrangement by dividing the differential potential between a boosted voltage and a second voltage or between a first voltage and a negative voltage between first and second potentials and outputting it through an MOSFET which is turned on under a predetermined mode. SOLUTION: An inner voltage generating circuit comprises a booster circuit, a voltage drop circuit and a negative voltage generating circuit. A dividing voltage is determined by the ratio of size between MOSFETs: Q1, Q2. At the time of test operation for monitoring VBB, a test signal ϕTT has high level and ϕTB has low level. The high level ϕTT employs a power supply voltage VDD when the differential voltage between the power supply voltage VDD and the dividing voltage is higher than the threshold level Vth of an MOSFET: Q4 otherwise employs a boosted voltage. Consequently, a dividing voltage (VDD-VBB)/2 is outputted, as it is, from an external terminal Ai regardless of the threshold level Vth of an MOSFET: Q4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, such as a dynamic RAM (random access memory), such as a boosted voltage or a substrate back bias voltage, which is larger than a power supply voltage supplied from an external terminal. The present invention relates to a technology having a voltage or an internal voltage having a reverse polarity and being effective for use in a test technology.

[0002]

2. Description of the Related Art As an example of a dynamic RAM having an internal power supply circuit which receives a power supply voltage supplied from an external terminal and forms an internal voltage necessary for the operation of the circuit, Japanese Patent Laid-Open Publication No. Hei 3
No. 214669.

[0003]

In a semiconductor integrated circuit device having an internal voltage as described above, the internal voltage is monitored as one of the operation tests of the internal circuit to determine whether or not the internal voltage is normally formed. It is convenient to be able to verify Dynamic type memory cell address selection M
In order to raise the potential of the word line to which the gate of the OSFET is connected to a high level applied to the bit line or higher than the threshold voltage, a voltage supplied from an external terminal and boosted from the power supply voltage is formed. In the case where an internal voltage generating circuit for forming a negative voltage or the like for supplying a back bias voltage to a semiconductor region in which the memory cell is formed is provided, it is easy to output the internal voltage as it is from an external terminal. There is a problem that can not be.

When a switch MOSFET is turned on at the time of a test and a boosted voltage is sent to an external terminal, a voltage reduced by the threshold voltage is output when an N-channel MOSFET is used. Due to the process variation of the value voltage, it becomes impossible to know an accurate boosted voltage. Therefore, P-channel type MOSF
Although it is conceivable to use ET, a P-type diffusion layer is connected to the external terminal, and the parasitic thyristor element is turned on by a high voltage such as overshoot generated at the external terminal, and the semiconductor integrated circuit device itself is turned on. Therefore, in a CMOS integrated circuit device, a P-type diffusion layer is not connected to an external terminal.

When a substrate back bias voltage such as -1.0 V is output via the switch MOSFET in the same manner as described above, the source electrode of the MOSFET to which the substrate back bias voltage such as -1.0 V is applied is connected to the source. It functions as an electrode, and is constantly turned on even when a ground potential of a circuit such as 0 V is applied to the gate electrode, causing a leakage current to flow between the external terminal and the substrate. Therefore, it is conceivable to provide a switch control circuit so as to supply a negative voltage such as -1.0 V to the gate electrode of the switch MOSFET. However, the switch control circuit operates with the power supply voltage and the substrate voltage, so that a large current flows to the substrate side when the circuit is operated, causing the substrate voltage to fluctuate significantly, or the leakage flowing to the substrate through the switch control circuit. There is a problem that the current is increased.

An object of the present invention is to provide a semiconductor integrated circuit device capable of monitoring an internal voltage including a boosted voltage and a negative voltage with a simple configuration. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0007]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, an internal circuit that receives the first voltage and the second voltage supplied from the first and second external terminals and forms a boosted voltage that is higher than the first voltage or a reverse polarity voltage that is lower than the second potential. In a semiconductor integrated circuit device including a power supply circuit, a potential difference between the boosted voltage and the second voltage or a difference voltage between the first voltage and the negative voltage is divided into a voltage between the first potential and the second potential. A voltage dividing circuit is provided, and the MO that is turned on in a predetermined operation mode is
The divided voltage is output through a third external terminal via the SFET.

[0008]

FIG. 1 is a schematic block diagram showing one embodiment of a dynamic RAM to which the present invention is applied. In FIG. 1, of the circuit blocks constituting the dynamic RAM to which the present invention is applied,
The main part is exemplarily shown as a representative, and it is formed on one semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique.

[0009] An address signal input from the address terminal Ai in a time-division manner is taken into the address buffer 1. Address buffer 1 is an X address buffer (X AD buffer).
DRESSBUFFER) and Y address buffer (Y ADDRESS BUFFE)
R), and each address signal input from the address terminal Ai is fetched in a time-division manner. The X address signal taken into the X address buffer is supplied to an X latch (XLATCH) and a predecoder (PRE-DEC).
It is conveyed to 2. The Y address signal taken into the Y address buffer is supplied to a Y decoder (YDEC) 4 via a Y latch (YLATCH) and a predecoder (PRE-DEC) 3. A part of the signal of the Y address is supplied to a mat control circuit (MAT CONTROL) included in the word line selection circuit 5, an amplification circuit (WA / MA) 14, and a read / write control circuit (R / W CONTROL).
10 is also supplied. The word line selection circuit 5 includes the mat control circuit and an X decoder (XDEC). The memory part is a memory mat (MAT) 6 and a sense amplifier (SA)
7 is comprised.

The memory mat 6 has a dynamic memory cell comprising an address selection MOSFET and a storage capacitor arranged in a matrix at an intersection of a word line and a bit line, and has a large storage capacity of, for example, 256 Mbits. In this case, a large number of memory mats 6 are provided in the memory section. An X decoder included in the word line selection circuit 5 selects a word line of a memory mat specified by an address signal from a large number of memory mats, and a Y decoder 4 selects a word line of the memory mat specified by the address signal. The bit line is selected.

In a read operation, the main amplifier MA of the amplifier circuit 14 is operated by the read / write control circuit 10 to amplify a read signal from the memory unit,
The data is output from the data terminal DQ through the data output circuit (DOUT BUFFER) 11. At the time of the write operation, the write amplifier WA of the amplifier circuit 14 is operated by the read / write control circuit 10, and the write signal input from the data terminal DQ is transmitted to the data input circuit (DIN BUFFER) and the write amplifier WA. The data is written to the selected memory cell. The clock buffer (CLOCK BUF) 8 receives the row address strobe signal / RAS, the column address strobe signal / CAS, the write enable signal / WE, and the output enable signal / OE, and transmits the received signal to a clock control circuit (CLOCK CONTROL) 9 for internal operation. Form various control signals necessary for the operation.

In this embodiment, an internal voltage generating circuit 13 for generating an operating voltage of a memory circuit is provided. The internal voltage generating circuit 13 includes a boosting circuit VPP-GEN, a step-down circuit VDL-GEN, and a negative voltage generating circuit VBB-GEN.
Is included. The step-down circuit VDL-GEN forms an internal voltage VDL obtained by stepping down the power supply voltage VDD for low power consumption and protection of the gate breakdown voltage of a miniaturized MOSFET. The internal voltage VDL is used as an operating voltage of the sense amplifier 7, although there is no particular limitation. As a result, the high level of the bit line to which the memory cell is connected is
The step-down voltage corresponds to the internal voltage VDL. When the power supply voltage VDD is 3.3 V, the internal step-down voltage VDD
L is set to, for example, 2.0V.

The word line to which the memory cell is connected needs to be higher than the internal step-down voltage VDL corresponding to the high level of the bit line above the threshold voltage of the address selection MOSFET. In order to form such a high voltage, a booster circuit VPP- using a charge pump circuit is used.
A GEN is provided. The booster circuit VPP-GEN includes:
A boosted voltage of about 3.6 V is formed by using a pulse signal generated by an oscillation circuit or the like that operates at the power supply voltage VDD. A negative voltage VBB such as -1.0 V is supplied to a semiconductor region or a substrate in which the memory cell is formed. By the supply of the negative voltage VBB, the threshold voltage of the address selection MOSFET is increased, the leak current in the off state is reduced, and the information retention time of the storage capacitor can be extended.

The internal voltage generation circuit 13 may be provided with a step-down voltage VPERI supplied to internal circuits such as an address selection circuit. As described above, the external power supply voltage VD
When D is 3.3V, the internal voltage VP is reduced to 2.5V.
An ERI may be formed and used as an operating voltage of an address selection circuit or the like to achieve low power consumption and high speed. Input / output circuits such as the address buffer 1, the data output circuit 11, and the data input circuit 12 which transmit and receive signals via external terminals are operated by the power supply voltage VDD.

The above-mentioned internal voltages VPP, VDL and VBB
Has a great effect on the memory operation. Therefore, in the operation test of the memory, the internal voltages VPP and VD are set in order to directly determine whether or not the internal voltage generating circuit 13 is operating normally.
It is convenient to add a function of outputting L and VBB through external terminals. There is no problem in adding the function of outputting the step-down voltage VDL, but it is difficult to output the step-up voltage VPP or the negative voltage VBB to an external terminal for the above-described reason.

FIG. 2 is a circuit diagram showing one embodiment of the VPP monitor circuit VPPM according to the present invention. VPP
The monitor circuit VPPM includes the following circuit elements. P is between the boosted voltage VPP and the ground potential of the circuit.
A voltage dividing circuit composed of channel type MOSFETs Q1 and Q2 and an N-channel type switching MOSFET Q3 for enabling the operation of the voltage dividing circuit are provided. Since the voltage dividing circuit only needs to operate during the test operation, the switch MOSFET Q3 is turned off during normal operation to prevent DC current from flowing between the boosted voltage VPP and the ground potential of the circuit. I do.

MOSFETs Q1 and Q constituting a voltage dividing circuit
2 is not particularly limited, but has a large resistance value in order to suppress the direct current flowing in the voltage dividing operation state, in other words, to prevent the boosted voltage VPP itself from being reduced by the operation of the voltage dividing circuit. And the DC current flowing therethrough is formed to be small. The on-resistance value of the N-channel switch MOSFET is smaller than the on-resistance of the P-channel MOSFETs Q1 and Q2, and the divided voltage is
It is set so as to be determined by the size ratio between Q1 and Q2. For example, if the MOSFETs Q1 and Q2 are formed in the same size, the on-resistance values of both become equal,
Since the on-resistance value of the OSFET Q3 is negligible, the boosted voltage VPP can be divided by half.
When the boost voltage VPP is about 3.6 V as described above,
A divided voltage of 1.8 V can be obtained.

The above-mentioned divided voltage is output from an external terminal Ai through an N-channel type switch MOSFET Q4. Although not particularly limited, the external terminal Ai is also used as an address terminal. That is, an external terminal used only for a test is not provided, but an address terminal or the like provided in a normal operation is used and used as a VPP monitor terminal only in a test operation. With such a configuration, an increase in the number of external terminals of the semiconductor integrated circuit device can be prevented.

The external terminal Ai and the switch MOS
An electrostatic protection circuit ESD is provided between the FET Q4 and the address buffer A via the protection circuit ESD.
DB input terminal and VPP monitor switch MO
Connected to SFET Q4. In this case, although not particularly limited, the switch MOSFET Q4 and the protection circuit ESD
And a resistor R2 is provided between
A diode-connected MOSFET Q5 is provided between the output side of Q4 and the ground potential of the circuit. Also, MOSFE
An N-channel MOSFET Q6 whose gate is supplied with the ground potential of the circuit is provided between the gate of TQ4 and the output side.

When a negative voltage undershoot occurs at the address terminal Ai during normal operation, the MOSFET Q6 is turned off by the MOSFET Q6.
4 is prevented from turning on. That is, when the negative voltage is supplied, the N-channel MOSFET Q
6 is turned on, the gate and source of MOSFET Q4 are short-circuited, and MOSFET Q4
Is prevented from turning on. The resistor R1 is equal to the above MO
It prevents an undesired signal from being transmitted to the test signal φTT when the SFET Q6 is in the ON state. Also, MOSF
The ETQ6 and Q5 and the resistors R1 and R2 operate as a surge voltage protection circuit.

The operation of the circuit of this embodiment is as follows. During normal operation, the test signal φTT supplied to the gates of the MOSFETs Q3 and Q4 is at a low level such as the ground potential of the circuit, and the MOSFETs Q3 and Q4 are turned off. As a result, no current flows through the voltage dividing circuit during normal operation, so that the boosting circuit VPP
-Does not affect GEN. In the above operation state, even if an undershoot of a negative voltage occurs at the address terminal Ai, the MOSFET Q4 keeps the off state by the operation of the MOSFET Q6. Does not flow to fluctuate the boosted voltage VPP.

During a test operation for monitoring VPP, the test signal φTT is set to a high level. Although not particularly limited, the high level of φTT is determined by the MOSFET Q4
Considering the effective threshold voltage Vth including the substrate effect, if VDD− (VPP / 2)> Vth, the power supply voltage VDD
Using a high level such as D, VDD- (VPP / 2)
If <Vth, a high level like the boost voltage VPP is used. Thereby, the above divided voltage (VPP / 2) is
The signal can be directly output from the external terminal Ai without being affected by the threshold voltage of the SFET Q4. From the divided voltage VPP / 2 output from the address terminal Ai,
The boosted voltage VPP itself can be determined.

FIG. 3 is a circuit diagram showing one embodiment of the VBB monitor circuit VBBM according to the present invention. VBB
The monitor circuit VBBM includes the following circuit elements. In the VBB monitor circuit VBBM, V
Those performing the same circuit operations as the PP monitor circuit VPPM are provided with the same circuit symbols. Between the substrate voltage VBB and the power supply voltage VDD, a P-channel MOSFET Q
1 and Q2, and a P-channel switch MOSFET Q7 for enabling the operation of the voltage divider.
Is provided. Since the voltage dividing circuit only needs to operate during the test operation, the switch MO is normally operated.
The SFET Q3 is turned off to prevent DC current from flowing between the power supply voltage VDD and the substrate voltage VBB.

MOSFETs Q1 and Q constituting a voltage dividing circuit
2 is to suppress the DC current flowing in the voltage dividing operation state as in the case of the VPP monitor circuit, in other words, the substrate voltage VBB itself is not reduced (increased) by the operation of the voltage dividing circuit. The resistance is set to be large as described above, and the DC current flowing therethrough is formed to be small. P-channel type switch MOSFET
Q3 is the ON resistance value of the P-channel type MOS
It is made smaller than the on-resistance of the FETs Q1 and Q2, and the divided voltage is set so as to be determined by the size ratio between the MOSFETs Q1 and Q2. For example, MOSFETQ
If 1 and Q2 are formed to have the same size, the on-resistance values of the two become equal and the on-resistance value of the MOSFET Q3 is negligible. Therefore, the difference voltage (VDD-VBB) between the power supply voltage VDD and the substrate voltage VBB is obtained. Can be divided by half. As described above, the substrate voltage VBB is -1.0.
1.15 V when the power supply voltage VDD is 3.3 V
Can be obtained.

The above divided voltage is output from an external terminal Ai through an N-channel type switch MOSFET Q4. The external terminal Ai is also used as an address terminal as described above. The external terminal Ai and the switch MOS
An electrostatic protection circuit ESD is provided between the FET Q4 and the address buffer A via the protection circuit ESD.
DB input terminal and switch MO for VBB monitor
Connected to SFET Q4. Similarly to the VPP monitor circuit, the switch MOSFET Q4 and the protection circuit ESD
And a resistor R2 is provided between
A diode-connected MOSFET Q5 is provided between the output side of Q4 and the ground potential of the circuit. MOSFET Q4
An N-channel MOSFET Q6 whose gate is supplied with the ground potential of the circuit is provided between the gate and the output side.

The MOSFET Q6, like the VPP monitor circuit, prevents the MOSFET Q4, which should be off, from being turned on when an undershoot of a negative voltage occurs at the address terminal Ai during normal operation. The resistor R1 prevents an undesired signal from being transmitted to the test signal φTT when the MOSFET Q6 is in the on state, and the resistor R2 controls the address signal to V during normal operation.
It is prevented from being transmitted to the PP monitor circuit VPPM. In this embodiment, since the switch MOSFET Q7 of the voltage dividing circuit is of the P-channel type, the test signal φTB is at the low level of the active level, and the switch MOSFET Q4 for monitoring is of the N-channel type. The level is set to the active level.

The operation of the circuit of this embodiment is as follows. During normal operation, the test signal φTB supplied to the gate of the MOSFET Q7 is at a high level such as the power supply voltage VDD, and the test signal φTT supplied to the gate of the MOSFET Q4 is at a low level such as the ground potential of the circuit. MOSFETs Q7 and Q4 are off. Thus, during normal operation, no current flows through the voltage dividing circuit, so that the boosting circuit VBB-GEN is not affected. In the above operation state, even if the address terminal A
Even if a negative voltage undershoot occurs in i, the operation of the MOSFET Q6 causes the MOSFET Q4
Maintains the off state, so that the power supply voltage VDD
Unwanted leak current does not flow through the FETs Q1 and Q4, and the substrate voltage VBB does not fluctuate.

During a test operation for monitoring VBB, the test signal φTT is set to a high level, and φTB is set to a low level. Although not particularly limited, the high level of φTT is determined in consideration of the effective threshold voltage Vth including the body effect of the MOSFET Q4, when the difference voltage between the power supply voltage VDD and the divided voltage is larger than Vth. When a high level such as the power supply voltage VDD is used and the difference voltage between the power supply voltage VDD and the divided voltage is smaller than Vth,
A high level such as the boost voltage VPP is used. As a result, the divided voltage (VDD-VBB) / 2 is
The signal can be directly output from the external terminal Ai without being affected by the threshold voltage of the ETQ4. Since the VDD is a known voltage supplied from an external terminal, the divided voltage (VDD−VB) output from the address terminal Ai is output.
B) / 2, the substrate voltage VBB itself can be determined.

FIG. 4 is a circuit diagram showing another embodiment of the VPP monitor circuit VPPM according to the present invention. In the VPP monitor circuit VPPM of this embodiment, the voltage division ratio can be changed. That is, the P-channel type MOSFETs Q1 and Q2 constituting the voltage dividing circuit are respectively composed of two MOSFETs Q11 and Q12 and Q21 and Q22, and one of them functions as a fuse between the drain and source of the MOSFETs Q12 and Q22. The wiring M2 is formed. Although not particularly limited, the divided VPP monitor voltage is output from the address terminal A8.

In a state where the wiring M2 is not cut, the MOSFETs Q11 and Q21 are the same as in the embodiment of FIG.
Performs a 1/2 voltage dividing operation. By selectively cutting the wiring M2, for example, by cutting the wiring M2 corresponding to the MOSFET Q12, the MOSFETs Q11, Q1
2 and the MOSFET Q21, a divided voltage such as VPP / 3 can be obtained by a resistance ratio of 2: 1. Conversely, if the wiring M2 corresponding to the MOSFET Q22 is cut, the MOSFET Q11 and the MOSFETs Q21, Q22
As a result, a divided voltage such as 2 VPP / 3 can be obtained with a resistance ratio of 1: 2.

With this configuration, the divided voltage is set to VPP /
A low voltage such as 3 = 1.2V can be obtained. As a result,
Since the difference voltage from the power supply voltage VDD such as 3.3 V can be increased, the test signal TREGMD corresponding to the high level of the power supply voltage VDD causes the switch MOSFET Q4
By turning 1 on, the divided voltage can be output as it is without being affected by the threshold voltage.
As a result, the switch MO is turned on using the booster VPP.
The load on the booster circuit VPP-GEN can be reduced as compared with the case where the SFET Q41 is turned on.

When the difference between the power supply voltage VDD and the boosted voltage VPP is relatively small, the divided voltage can be shifted to a higher voltage such as 2 VPP / 3. As described above, the number of MOSFETs constituting the voltage dividing circuit is changed by the selective cutting of the fuse using wiring or the like to change the voltage dividing ratio, thereby forming the internal voltage generating circuit provided in the semiconductor integrated circuit device. The divided voltage is selected in accordance with the voltage to be supplied. The selective cutting of the fuse is not particularly limited, but cutting by laser beam irradiation is effective.

In this embodiment, the switch MOSFETs for outputting the monitor voltage are also two MOSFETs Q41 and Q41.
42. The MOSFET Q41 is a switch MOSFET for outputting the divided voltage, and a MOSFET Q42 newly added in parallel with the switch MOSFET is used for directly outputting the voltage when the boosted voltage VPP is not normally formed. The above switch MOSF
The test signal TREGMD is supplied to the ETQ41 so as to operate in conjunction with the switch MOSFET Q3 of the voltage dividing circuit. On the other hand, an independent test signal TREGMP is supplied to the gate of the switch MOSFET Q42. Thus, when the booster circuit VPP-GEN malfunctions, the switch MOSFET Q42 can be turned on using the test signal TREGMP, and the boosted voltage VPP at that time can be output.

FIG. 5 is a circuit diagram showing another embodiment of the VBB monitor circuit VBBM according to the present invention. The VBB monitor circuit VBBM of this embodiment is the same as the VBB monitor circuit of FIG.
Like the PP monitor circuit, the voltage division ratio can be changed. In other words, the P-channel MOSFETs Q1 and Q2 that constitute the voltage dividing circuit each have two MOSFETs.
A wiring M2 functioning as a fuse is formed between the drain and the source of one of the MOSFETs Q11 and Q21. The terminal for outputting the VBB monitor voltage is
For example, it is an address terminal A9.

When the wiring M2 is not cut, the MOSFETs Q12 and Q22 are connected in the same manner as in the circuit of FIG.
Performs a 1/2 voltage dividing operation. By selectively cutting the wiring M2, for example, by cutting the wiring M2 corresponding to the MOSFET Q21,
With the SFETs Q21 and Q22, a divided voltage such as (VDD-VBB) / 3 can be obtained with a resistance ratio of 2: 1. Conversely, the wiring M2 corresponding to the MOSFET Q11
Is cut, MOSFETs Q11 and Q12 and MOSF
With ETQ22, the resistance ratio of 1 to 2 is set to 2 (VDD
-VBB) / 3 can be obtained.
With this configuration, it is possible to select the optimum divided voltage corresponding to the negative voltage and the power supply voltage formed by the internal voltage generation circuit provided in the semiconductor integrated circuit device as described above. The other configuration is the same as that of the embodiment of FIG. 4 and its description is omitted.

FIG. 6 is a circuit diagram showing one embodiment of the internal voltage monitor circuit provided in the semiconductor integrated circuit device according to the present invention. FIG. 1A shows a VDL monitor voltage circuit VLLM for outputting the operating voltage VDL of the sense amplifier, and FIG. 2B shows an operating voltage VPERI of a peripheral circuit such as an address selection circuit. VP
The ERI monitor voltage circuit VPERIM is shown. Switch MOSFETs Q41 and Q similar to those shown in FIGS.
The VDL and VPERI are output from the address terminals A10 and A11 using the terminal 42. In this case, VDL or VERR
Since I is a voltage stepped down to 2 V or 2.5 V as described above, it can be output through the switch MOSFET Q41 by a control signal using VDD or VPP as a test signal.

FIG. 7 is a circuit diagram of an embodiment of the level conversion circuit. This level conversion circuit is used to generate the test signals φTT, φTB and TREGM. For example, if the test circuit is the step-down voltage VPER
In the case of operating at I, the test signal has a small signal amplitude corresponding to the step-down voltage VPERI, and the switch MOSFET Q4 (Q41) and the like cannot be sufficiently turned on. Therefore, the level conversion circuit of this embodiment is used to level-convert the VPERI level signal to the VPP level using the boosted voltage VPP.

P-channel MOSFET Q30 and N-channel MOSFET Operating at Step-Down Voltage VPERI
Q31 is a CMOS that forms an inverted signal of the test signal φT.
It is an inverter circuit. The input signal and the output signal of the CMOS inverter circuit are complementary signals having phases opposite to each other. The gates and drains of the P-channel MOSFETs Q32 and Q34 whose sources are connected to the boosted voltage VPP are cross-connected to form a latch. MOS above
N-channel MOSFETs Q33 and Q35 are provided between the drains of the FETs Q32 and Q34 and the ground potential of the circuit, respectively. The above N-channel type MOSFET
The input signal of low amplitude corresponding to the step-down voltage VPERI is transmitted to the gate of Q33, and the input signal of low amplitude and inverted with respect to the input signal is transmitted to the gate of the N-channel MOSFET Q35. Supplied.
A level-converted signal is formed from the commonly connected drains of the MOSFETs Q32 and Q33, and a P-channel MOSFET Q36 operated at the boosted voltage VPP.
And CMOS comprising N-channel MOSFET Q37
Output via an inverter circuit.

The operation of the level conversion circuit of this embodiment is as follows. When the input signal is at a low level and its inverted signal is at a high level (VPERI), the low level turns off the N-channel MOSFET Q31, and the high-level (VDD3) turns on the N-channel MOSFET Q35. You. The P-channel MOSFET Q32 is turned on by the MOSFET Q35 in the on state, and its drain potential is set to a high level corresponding to VPP. As a result, the gate of the P-channel MOSFET Q34 becomes a high level corresponding to the VPP, and the P-channel MOSFET
SFET Q34 is turned off. Therefore, the P-channel MOSFET Q32 is turned on, the N-channel MOSFET Q33 is turned off, and the output C
Since a high level corresponding to the boosted voltage VPP is supplied to the input of the MOS inverter circuit, a low level output signal is output.

When the input signal goes high (VPERI),
When the inverted signal changes to low level, the high level turns on the N-channel MOSFET Q33, and the low level of the inverted signal turns on the N-channel MOSFET Q33.
FET Q35 is turned off. MO in the above ON state
P-channel MOSFET Q3 by SFET Q33
4 is turned on, and its drain potential is set to a high level corresponding to VPP. As a result, the P-channel type MOS
The gate of the FET Q32 goes to a high level corresponding to the VPP, and the P-channel MOSFET Q32 is turned off. Therefore, the P-channel MOSFET Q
32 is turned off and the N-channel MOSFET Q33
Is turned on to supply a low level to the input of the output CMOS inverter circuit, so that a high level output signal corresponding to VPP is output. Such a level conversion circuit can be used when converting a VPERI level to a VDD level and also when converting a VDL level to a VDD level.

FIG. 8 is a circuit diagram of a simplified embodiment from address input to data output centering on the sense amplifier section of the dynamic RAM according to the present invention. In this embodiment, a divided word line system or a hierarchical word line system is adopted, a memory array is divided into a plurality of memory mats, and such a memory mat is configured to be sandwiched between a sense amplifier and a sub-word driver. FIG. 2 exemplarily shows a sense amplifier 7 sandwiched between two memory mats 6 from above and below, and a circuit provided in an intersection area between the sense amplifier 7 and the sub-word driver 51. It is shown as

The dynamic memory cell is typically exemplified by one provided between the sub-word line SWL provided in the one memory mat 6 and one of the complementary bit lines BL and BLB. Is shown. The dynamic memory cell has an address selection MOS
It comprises an FET Qm and a storage capacitor Cs. The gate of the address selection MOSFET Qm is connected to the sub word line S
The drain of the MOSFET Qm is connected to the bit line BL, and the source is connected to the storage capacitor Cs. The other electrode of the storage capacitor Cs is shared and supplied with the plate voltage VPLT. MOS above
A negative back bias voltage VBB is applied to the substrate (channel) of the FET Qm. Although not particularly limited, the back bias voltage VBB is set to a voltage such as -1.0V. The selection level of the sub word line SWL is a boosted voltage VPP which is higher than the high level of the bit line by the threshold voltage of the address selection MOSFET Qm.

When the sense amplifier 7 is operated at the internal step-down voltage VDL, the high level amplified by the sense amplifier and given to the bit line is equal to the internal voltage VDL.
The DL level is set. Therefore, the boosted voltage VPP corresponding to the word line selection level is set to VDL + Vth + α. A pair of complementary bit lines BL and BLB of the sub-array provided on the left side of the sense amplifier are arranged in parallel as shown in FIG. Such complementary bit lines BL and BLB
Are connected to input / output nodes of a unit circuit of the sense amplifier 7 by shared switch MOSFETs Q1 and Q2.

The unit circuit of the sense amplifier 7 is constituted by a CMOS latch circuit comprising N-channel type amplifying MOSFETs Q5, Q6 and P-channel type amplifying MOSFET MOSFETs Q7, Q8 whose gates and drains are cross-connected to form a latch. You. N-channel MO
The sources of SFETs Q5 and Q6 are connected to a common source line CSN. The sources of the P-channel MOSFETs Q7 and Q8 are connected to a common source line CSP. Power switch MOSFETs are connected to the common source lines CSN and CSP, respectively. Although not particularly limited, the cross area 1 is connected to the common source line CSN to which the sources of the N-channel type amplification MOSFETs Q5 and Q6 are connected.
8 N-channel type power switch MOS
An operation voltage corresponding to the ground potential is applied by FET Q14.

Although not particularly limited, the common source line CSP to which the sources of the P-channel type amplification MOSFETs Q7 and Q8 are connected is connected to the N-channel type power MO for overdrive provided in the cross area 18.
An SFET Q16 and an N-channel power MOSFET Q15 for supplying the internal voltage VDL are provided.
The power supply voltage VDD supplied from an external terminal is used for the overdrive voltage, although there is no particular limitation. Alternatively, the power supply voltage VDD of the sense amplifier operating speed
VPP is applied to the gate to reduce the dependency,
The voltage may be slightly reduced as the voltage is obtained from the source of the N-channel MOSFET whose power supply voltage VDD is supplied to the drain.

The N-channel type power MOSFET
The sense amplifier overdrive activation signal SAP1 supplied to the gate of Q16 is the N-channel type MO.
Activation signal SAP supplied to the gate of SFET Q15
2, and SAP1 and SAP2 are set to a high level in time series. Although not particularly limited, SAP1
And the high level of SAP2 is a signal of the boosted voltage VPP level. That is, the boosted voltage VPP is about 3.6 V, so that the N-channel MOSFETs Q15 and Q16
Can be sufficiently turned on. MOSFET
After Q16 is off (signal SAP1 is low), a voltage corresponding to internal voltage VDL can be output from the source side by turning on MOSFET Q15 (signal SAP2 is high).

The input / output node of the unit circuit of the sense amplifier 7 includes an equalizing MOS for short-circuiting the complementary bit line.
FET Q11 and switch MOSFETs Q9 and Q1 for supplying a half precharge voltage VBLR to a complementary bit line.
A precharge (equalize) circuit including 0 is provided. The gates of these MOSFETs Q9 to Q11 are commonly supplied with a precharge signal PCB. Although not shown, a driver circuit for forming the precharge signal PCB is provided with an inverter circuit in the above-mentioned intersection area to make the rising and falling speed high. That is, at the start of the memory access, prior to the word line selection timing,
MOSFETs Q9 to Q9 constituting the precharge circuit through inverter circuits provided in each intersection area.
Q11 is switched at high speed.

In the above intersection area, an IO switch circuit IO
SW (switch M connecting local IO and main IO)
OSFETs Q19, Q20) are located. In addition to the circuits shown in the figure, if necessary, a half precharge circuit for the common source lines CSP and CSN of the sense amplifier 7, a half precharge circuit for the local input / output line LIO, and a VDL precharge circuit for the main input / output line , Shared distributed signal lines SHR and SHL are also provided.

The unit circuit of the sense amplifier 7 is connected to similar complementary bit lines BL and BLB of the memory mat 6 on the lower side of the figure via shared switch MOSFETs Q3 and Q4. For example, the sub word line S of the upper memory mat 6
When WL is selected, the upper shared switch MOSFETs Q1 and Q2 of the sense amplifier are turned on, and the lower shared switch MOSFETs Q3 and Q4 are turned off. Switch MOSFET Q12 and Q13
Constitutes a column (Y) switch circuit,
When the selection signal YS is set to a selection level (high level), it is turned on, and the input / output nodes of the unit circuit of the sense amplifier and the local input / output lines LIO1, LIO1B, L
IO2, LIO2B, etc. are connected.

As a result, the input / output node of the sense amplifier 7 is connected to the upper complementary bit lines BL and BLB to amplify the minute signal of the memory cell connected to the selected sub-word line SWL. Switch circuit (Q
12 and Q13) through the local input / output lines LIO1, L
Communicate to IO1B. The local input / output lines LIO1, L
IO1B extends along the sense amplifier row, that is, in the horizontal direction in FIG. The local input / output line LI
O1 and LIO1B are connected to main input / output lines MIO and MIOB to which input terminals of the main amplifier 61 are connected via an IO switch circuit including N-channel MOSFETs Q19 and Q20 provided in the intersection area. I above
The O switch circuit is switch-controlled by a selection signal formed by decoding an X-system address signal. Note that the IO switch circuit is based on the N-channel MOSFET Q19.
A CMOS switch configuration in which P-channel MOSFETs are connected in parallel to Q20 and Q20, respectively.

As described above, according to the column selection signal YS,
In the configuration for selecting two pairs of complementary bit lines, the local input / output line LIO and the main input / output line MIO indicated by two dotted lines in the embodiment of FIG. 2 correspond to the two pairs of input / output lines. It is. In the burst mode of the synchronous DRAM, the column selection signal YS is switched by a counter operation, and the local input / output lines LIO1, LIO1B
And the connection between LIO2, LIO2B and two pairs of complementary bit lines BL, BLB of the sub-array is sequentially switched.

The address signal Ai is supplied to the address buffer 1
Supplied to The address buffer 1 operates in a time-division manner and takes in an X address signal and a Y address signal.
The X address signal is supplied to the predecoder 2, and a selection signal for the main word line MWL is formed via the main row decoder and the main word driver 5. Since the address buffer 1 receives the address signal Ai supplied from the external terminal, it is operated by the power supply voltage VDD supplied from the external terminal, and the predecoder 2 and the like are operated by the step-down voltage VPERI. The main word driver 5 is operated by the boosted voltage VPP. The main word driver 5 also uses the level conversion circuit as shown in FIG. The column decoder (driver 41) 4 receives the Y address signal supplied by the time-division operation of the address buffer 1 and forms the selection signal YS.

The main amplifier 14 has a step-down voltage VPE
A read signal is output from the external terminal Dout through the data output circuit 11 operated by the RI and operated by the power supply voltage VDD supplied from the external terminal. A write signal input from the external terminal Din is captured through the data input circuit 12, and supplies a write signal to the main input / output lines MIO and MIOB through a write amplifier (write driver) included in the main amplifier 14 in FIG. The input section of the data output circuit 11 is provided with the above-described level conversion circuit and a logic section for outputting an output signal thereof in synchronization with a timing signal corresponding to the clock signal.

Although not particularly limited, the power supply voltage VDD supplied from the external terminal is set to 3.3 V in the first embodiment, and the step-down voltage VPERI supplied to the internal circuit is set to 2.
5V, and the operating voltage VDL of the sense amplifier is set to 2.0V. Then, the word line selection signal (boosted voltage) is set to 3.6V. The bit line precharge voltage VBLR is set to 1.0 V corresponding to VDL / 2, and the plate voltage VPLT is also set to 1.0 V. Then, the substrate voltage VBB is set to -1.0V. The power supply voltage VDD supplied from the external terminal is a low voltage such as 2.5 V in the second embodiment. In the case of such a low power supply voltage VDD, the step-down voltage VPERI is omitted, the peripheral circuits such as the decoder circuit are operated by the power supply voltage VDD of 2.5 V, and the other voltages are the same as above.

By making the same circuit operable in two operating voltage modes, a dynamic RAM that is easy to use can be obtained. By adding the voltage monitor circuit as described above, even if the power supply voltage VDD is 3.3 V as described above, or even if the power supply voltage VDD is lowered as 2.5 V, the above-described voltage division ratio adjustment is performed. Thus, an accurate internal voltage can be output through an external terminal without being affected by process variations such as a threshold voltage of the internal element.

The functions and effects obtained from the above embodiment are as follows. (1) Receiving the first voltage and the second voltage supplied from the first and second external terminals, forming a boosted voltage that is higher than the first voltage or a reverse polarity voltage lower than the second potential. In a semiconductor integrated circuit device having an internal power supply circuit, a potential difference between the boosted voltage and the second voltage or a difference voltage between the first voltage and the negative voltage is divided into a voltage between the first potential and the second potential. Providing the voltage dividing circuit for applying the voltage can provide an effect that the voltage can be output through the third external terminal without being affected by the threshold voltage of the MOSFET for outputting the voltage.

(2) According to the above (1), since the internal voltage can be directly monitored, the reliability of the operation test can be increased and the test time can be shortened. Is obtained.

(3) By allowing a current to flow through the voltage dividing circuit by a switch MOSFET that operates only in a predetermined operation mode, the load of the internal voltage generating circuit using the charge pump circuit can be reduced. The effect that low power consumption can be maintained is obtained.

(4) When the power supply voltage is a positive voltage, an N-channel MOSFET is used as a switch MOSFET.
By providing an N-channel MOSFET whose gate is connected to the ground potential of the circuit between the gate and the source and drain on the output side, surge protection operation and under-current generated at an external terminal during normal operation are provided. Even if a shoot occurs, an effect is obtained that the switch MOSFET can be kept in the off state to stabilize the internal voltage.

(5) A plurality of word lines, a plurality of complementary bit line pairs, and a plurality of dynamic memory cells provided at the intersections thereof are provided, and a memory array is provided. And a dynamic RA for applying an internal voltage as a substrate back bias voltage applied to a semiconductor region in which a memory cell is formed.
By providing the voltage monitoring circuit in M, it is possible to increase the reliability of the operation test and to shorten the test time.

Although the invention made by the inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the above embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say. For example, in the dynamic RAM shown in FIG. 1, the configuration of the memory mat and the sense amplifier can adopt various embodiments, and the input / output interface of the dynamic RAM conforms to the synchronous specification, the Rambus specification, and the like. Various embodiments such as those described above can be adopted. The word line may adopt a word shunt system in addition to the above-described hierarchical word line system.

The voltage monitor circuit according to the present invention includes, in addition to the above-described dynamic RAM, an internal voltage generating circuit that uses a power supply voltage supplied from an external terminal and forms a boosted voltage or an internal voltage of the opposite polarity. It can be mounted on various semiconductor integrated circuit devices provided. The present invention can be widely used for a semiconductor integrated circuit device having the above-described internal voltage generating circuit.

[0063]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, an internal circuit that receives the first voltage and the second voltage supplied from the first and second external terminals and forms a boosted voltage that is higher than the first voltage or a reverse polarity voltage that is lower than the second potential. In a semiconductor integrated circuit device including a power supply circuit, a potential difference between the boosted voltage and the second voltage or a difference voltage between the first voltage and the negative voltage is divided into a voltage between the first potential and the second potential. By providing the voltage dividing circuit, the voltage can be output through the third external terminal without being affected by the threshold voltage of the MOSFET that outputs the voltage.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram showing an embodiment of a dynamic RAM to which the present invention is applied.

FIG. 2 is a circuit diagram showing one embodiment of a VPP monitor circuit according to the present invention.

FIG. 3 is a circuit diagram showing one embodiment of a VBB monitor circuit according to the present invention.

FIG. 4 is a circuit diagram showing another embodiment of the VPP monitor circuit according to the present invention.

FIG. 5 is a circuit diagram showing another embodiment of the VBB monitor circuit according to the present invention.

FIG. 6 is a circuit diagram showing an embodiment of an internal voltage monitor circuit provided in the semiconductor integrated circuit device according to the present invention.

FIG. 7 is a circuit diagram showing one embodiment of a level conversion circuit used in the semiconductor integrated circuit device according to the present invention.

FIG. 8 is a circuit diagram showing a simplified embodiment from address input to data output with a focus on the sense amplifier section of the dynamic RAM according to the present invention.

[Explanation of symbols]

1 ... address buffer, 2 ... X latch and predecoder,
3 ... Y latch and predecoder, 4 ... Y decoder, 5 ... word line selection circuit, 6 ... memory mat, 7 ... sense amplifier, 8 ... control buffer, 9 ... clock control circuit, 10 ... read / write control circuit, 11 ... Data output circuit, 12 data input circuit, 13 internal voltage generation circuit, 14 amplifier circuit, VPPM VPP monitor circuit,
VBBM: VBB monitor circuit, VDLM: VDL monitor circuit, VPERIM: VPERI monitor circuit, Q1 to Q
62 MOSFET, R1 to R2 resistors, ESD input protection circuit.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification code FI Theme coat ゛ (Reference) H01L 21/822 (72) Inventor Yutaka Ito 6-16-16 Shinmachi, Ome-shi, Tokyo 3 Hitachi, Ltd. Devices Inside the Development Center (72) Inventor Masahiro Koyamada 5-2-12-1 Kamimizu Honcho, Kodaira-shi, Tokyo Inside Hitachi Super LSI Systems Co., Ltd. 5-20-1, Honcho F-term in Semiconductor Division, Hitachi, Ltd. F-term (reference) 5L106 DD00 EE08 GG00

Claims (6)

[Claims] A first internal power supply circuit that receives a first voltage and a second voltage supplied from first and second external terminals and forms a boosted voltage that is higher than the first voltage; A voltage dividing circuit for dividing a potential difference between the boosted voltage and the second voltage to the first potential or less, and a voltage dividing circuit which is turned on when a predetermined operation mode is turned on. Switch M for outputting through a third external terminal
A semiconductor integrated circuit device comprising an OSFET. 2. The voltage dividing circuit according to claim 1, wherein a switch MOSFET that operates only in the predetermined operation mode is connected to a voltage dividing path provided between the boosted voltage and the second voltage. A semiconductor integrated circuit device which is inserted. 3. A second voltage receiving a first voltage and a second voltage supplied from first and second external terminals, and forming an internal voltage having a polarity lower than the second voltage and opposite to the first voltage. A semiconductor integrated circuit device having an internal power supply circuit, wherein a voltage difference between the internal voltage and the first voltage or a step-down voltage formed based on the first voltage is divided into the second potential or more; A switch M that is turned on in the operation mode to output the divided voltage through a third external terminal
A semiconductor integrated circuit device comprising an OSFET. 4. The voltage dividing circuit according to claim 1, wherein the voltage dividing circuit operates only in the predetermined operation mode, and forms the divided voltage by receiving the internal voltage and the first voltage or the stepped-down voltage. A semiconductor integrated circuit device. 5. The device according to claim 1, wherein the first potential is a positive power supply voltage, and the switch MOSFET is an N-channel MOSFET.
ET, the gate of the switch MOSFET and the source on the output side,
A semiconductor integrated circuit device, wherein an N-channel MOSFET whose gate is connected to the ground potential of the circuit is provided between the drain and the drain. 6. The semiconductor integrated circuit device according to claim 5, further comprising a memory array provided with a plurality of word lines, a plurality of complementary bit line pairs, and a plurality of dynamic memory cells provided at intersections thereof. The boosted voltage is used to set a selection level of the word line, and the internal voltage is used to set a substrate back bias voltage applied to a semiconductor region where the memory cell is formed. A semiconductor integrated circuit device, wherein the operation mode is a test mode.