HK1250281A1 - 製造半導體裝置的方法 - Google Patents
製造半導體裝置的方法Info
- Publication number
- HK1250281A1 HK1250281A1 HK18109635.2A HK18109635A HK1250281A1 HK 1250281 A1 HK1250281 A1 HK 1250281A1 HK 18109635 A HK18109635 A HK 18109635A HK 1250281 A1 HK1250281 A1 HK 1250281A1
- Authority
- HK
- Hong Kong
- Prior art keywords
- manufacturing
- semiconductor device
- semiconductor
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 238000000034 method Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
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- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H01L2224/732—Location after the connecting process
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- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
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- H01L2224/8512—Aligning
- H01L2224/85148—Aligning involving movement of a part of the bonding apparatus
- H01L2224/85169—Aligning involving movement of a part of the bonding apparatus being the upper part of the bonding apparatus, i.e. bonding head, e.g. capillary or wedge
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- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/852—Applying energy for connecting
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- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
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- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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- H—ELECTRICITY
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
- H01L24/92—Specific sequence of method steps
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Mechanical Engineering (AREA)
- Geometry (AREA)
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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JP2016252468A JP2018107296A (ja) | 2016-12-27 | 2016-12-27 | 半導体装置の製造方法 |
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HK1250281A1 true HK1250281A1 (zh) | 2018-12-07 |
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US (1) | US10128130B2 (zh) |
EP (1) | EP3349240A1 (zh) |
JP (1) | JP2018107296A (zh) |
KR (1) | KR20180076318A (zh) |
CN (1) | CN108242408B (zh) |
HK (1) | HK1250281A1 (zh) |
TW (1) | TW201839943A (zh) |
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JP2020136331A (ja) * | 2019-02-14 | 2020-08-31 | 株式会社日産アーク | 半導体装置及びその製造方法 |
US11501116B1 (en) | 2021-07-19 | 2022-11-15 | Sas Institute Inc. | Quality prediction using process data |
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JPH01170034A (ja) * | 1987-12-25 | 1989-07-05 | Hitachi Ltd | リードフレーム及び半導体装置 |
JPH08236564A (ja) | 1995-02-28 | 1996-09-13 | Nec Kyushu Ltd | 半導体装置 |
JP3062192B1 (ja) * | 1999-09-01 | 2000-07-10 | 松下電子工業株式会社 | リ―ドフレ―ムとそれを用いた樹脂封止型半導体装置の製造方法 |
IT1317559B1 (it) * | 2000-05-23 | 2003-07-09 | St Microelectronics Srl | Telaio di supporto per chip avente interconnessioni a bassa resistenza. |
JP2003338519A (ja) * | 2002-05-21 | 2003-11-28 | Renesas Technology Corp | 半導体装置及びその製造方法 |
JP2004095572A (ja) * | 2002-08-29 | 2004-03-25 | Hitachi Ltd | 半導体装置およびその製造方法 |
KR100555495B1 (ko) * | 2003-02-08 | 2006-03-03 | 삼성전자주식회사 | 칩 어레이 몰딩용 몰드 다이, 그것을 포함하는 몰딩 장치및 칩 어레이 몰딩 방법 |
JP4570868B2 (ja) * | 2003-12-26 | 2010-10-27 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP4307362B2 (ja) * | 2004-11-10 | 2009-08-05 | パナソニック株式会社 | 半導体装置、リードフレーム及びリードフレームの製造方法 |
US7464854B2 (en) * | 2005-01-25 | 2008-12-16 | Kulicke And Soffa Industries, Inc. | Method and apparatus for forming a low profile wire loop |
JP2009049072A (ja) * | 2007-08-15 | 2009-03-05 | Panasonic Corp | リードフレーム、半導体装置、リードフレームの製造方法、および半導体装置の製造方法 |
JP4957513B2 (ja) * | 2007-11-05 | 2012-06-20 | 富士通セミコンダクター株式会社 | 半導体装置及び半導体装置の製造方法 |
JP5448727B2 (ja) * | 2009-11-05 | 2014-03-19 | ルネサスエレクトロニクス株式会社 | 半導体装置及びその製造方法 |
JP5467959B2 (ja) * | 2010-07-21 | 2014-04-09 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP2012109435A (ja) * | 2010-11-18 | 2012-06-07 | Renesas Electronics Corp | 半導体装置の製造方法 |
JP5795277B2 (ja) * | 2012-03-22 | 2015-10-14 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法および半導体装置 |
JP6129645B2 (ja) * | 2013-05-29 | 2017-05-17 | ルネサスエレクトロニクス株式会社 | 半導体装置および半導体装置の製造方法 |
JP6092084B2 (ja) | 2013-11-29 | 2017-03-08 | アオイ電子株式会社 | 半導体装置および半導体装置の製造方法 |
JP2015220248A (ja) * | 2014-05-14 | 2015-12-07 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法および半導体装置 |
JP2018046242A (ja) * | 2016-09-16 | 2018-03-22 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
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CN108242408B (zh) | 2023-07-18 |
CN108242408A (zh) | 2018-07-03 |
JP2018107296A (ja) | 2018-07-05 |
US10128130B2 (en) | 2018-11-13 |
KR20180076318A (ko) | 2018-07-05 |
US20180182644A1 (en) | 2018-06-28 |
EP3349240A1 (en) | 2018-07-18 |
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