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GB9504794D0 - Bus configuration for memory systems - Google Patents

Bus configuration for memory systems

Info

Publication number
GB9504794D0
GB9504794D0 GBGB9504794.0A GB9504794A GB9504794D0 GB 9504794 D0 GB9504794 D0 GB 9504794D0 GB 9504794 A GB9504794 A GB 9504794A GB 9504794 D0 GB9504794 D0 GB 9504794D0
Authority
GB
United Kingdom
Prior art keywords
memory systems
bus configuration
bus
configuration
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GBGB9504794.0A
Other versions
GB2288256A (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HP Inc
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of GB9504794D0 publication Critical patent/GB9504794D0/en
Publication of GB2288256A publication Critical patent/GB2288256A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1642—Handling requests for interconnection or transfer for access to memory bus based on arbitration with request queuing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)
  • Memory System (AREA)
GB9504794A 1994-04-08 1995-03-09 Bus configuration for memory systems Withdrawn GB2288256A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US22494194A 1994-04-08 1994-04-08

Publications (2)

Publication Number Publication Date
GB9504794D0 true GB9504794D0 (en) 1995-04-26
GB2288256A GB2288256A (en) 1995-10-11

Family

ID=22842868

Family Applications (1)

Application Number Title Priority Date Filing Date
GB9504794A Withdrawn GB2288256A (en) 1994-04-08 1995-03-09 Bus configuration for memory systems

Country Status (3)

Country Link
JP (1) JPH07281988A (en)
DE (1) DE19503022A1 (en)
GB (1) GB2288256A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2759178B1 (en) * 1997-02-05 1999-04-09 Sgs Thomson Microelectronics MEMORY MANAGEMENT CIRCUIT IN A MULTI-USER ENVIRONMENT WITH REQUEST AND PRIORITY OF ACCESS
US7043593B1 (en) * 2003-04-29 2006-05-09 Advanced Micro Devices, Inc. Apparatus and method for sending in order data and out of order data on a data bus

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3699530A (en) * 1970-12-30 1972-10-17 Ibm Input/output system with dedicated channel buffering
US4451880A (en) * 1980-10-31 1984-05-29 Honeywell Information Systems Inc. Memory controller with interleaved queuing apparatus
US5168558A (en) * 1986-01-29 1992-12-01 Digital Equipment Corporation Apparatus and method for providing distributed control in a main memory unit of a data processing system

Also Published As

Publication number Publication date
JPH07281988A (en) 1995-10-27
DE19503022A1 (en) 1995-10-12
GB2288256A (en) 1995-10-11

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Legal Events

Date Code Title Description
WAP Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1)