GB8518231D0 - Producing layered structures - Google Patents
Producing layered structuresInfo
- Publication number
- GB8518231D0 GB8518231D0 GB858518231A GB8518231A GB8518231D0 GB 8518231 D0 GB8518231 D0 GB 8518231D0 GB 858518231 A GB858518231 A GB 858518231A GB 8518231 A GB8518231 A GB 8518231A GB 8518231 D0 GB8518231 D0 GB 8518231D0
- Authority
- GB
- United Kingdom
- Prior art keywords
- layered structures
- producing layered
- producing
- structures
- layered
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB858518231A GB8518231D0 (en) | 1985-07-19 | 1985-07-19 | Producing layered structures |
PCT/GB1986/000424 WO1987000688A1 (en) | 1985-07-19 | 1986-07-18 | Methods of producing layered structures |
EP86904308A EP0231242A1 (en) | 1985-07-19 | 1986-07-18 | Methods of producing layered structures |
GB08617654A GB2178896B (en) | 1985-07-19 | 1986-07-18 | Methods of producing layered structures for integrated circuits |
JP61504078A JPS63500346A (en) | 1985-07-19 | 1986-07-18 | How to make layered structures |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB858518231A GB8518231D0 (en) | 1985-07-19 | 1985-07-19 | Producing layered structures |
Publications (1)
Publication Number | Publication Date |
---|---|
GB8518231D0 true GB8518231D0 (en) | 1985-08-29 |
Family
ID=10582519
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB858518231A Pending GB8518231D0 (en) | 1985-07-19 | 1985-07-19 | Producing layered structures |
GB08617654A Expired GB2178896B (en) | 1985-07-19 | 1986-07-18 | Methods of producing layered structures for integrated circuits |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB08617654A Expired GB2178896B (en) | 1985-07-19 | 1986-07-18 | Methods of producing layered structures for integrated circuits |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP0231242A1 (en) |
JP (1) | JPS63500346A (en) |
GB (2) | GB8518231D0 (en) |
WO (1) | WO1987000688A1 (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
NL8701032A (en) * | 1987-05-01 | 1988-12-01 | Philips Nv | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE WITH INTERCONNECTIONS LOCATED BOTH ABOVE A SEMICONDUCTOR AREA AND ABOVE AN ISOLATING AREA THEREIN. |
JPH08111460A (en) * | 1994-08-16 | 1996-04-30 | Nec Corp | Structure of multilayer wiring and fabrication thereof |
JPH10261709A (en) * | 1996-09-27 | 1998-09-29 | Nec Corp | Manufacture of semiconductor device |
JPH11121612A (en) * | 1997-10-14 | 1999-04-30 | Mitsubishi Electric Corp | Semiconductor device and its manufacture |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4077854A (en) * | 1972-10-02 | 1978-03-07 | The Bendix Corporation | Method of manufacture of solderable thin film microcircuit with stabilized resistive films |
NL7608901A (en) * | 1976-08-11 | 1978-02-14 | Philips Nv | PROCESS FOR THE MANUFACTURE OF A SEMI-CONDUCTOR DEVICE AND SEMIC-CONDUCTOR DEVICE MANUFACTURED BY SUCH PROCESS. |
JPS56130947A (en) * | 1980-03-17 | 1981-10-14 | Fujitsu Ltd | Manufacture of semiconductor device |
GB8316476D0 (en) * | 1983-06-16 | 1983-07-20 | Plessey Co Plc | Producing layered structure |
DE3331759A1 (en) * | 1983-09-02 | 1985-03-21 | Siemens AG, 1000 Berlin und 8000 München | INTEGRATED SEMICONDUCTOR CIRCUIT WITH A MULTIPLE LAYER WIRING EXISTING FROM ALUMINUM OR AN ALUMINUM ALLOY AND METHOD FOR THEIR PRODUCTION. |
EP0175604B1 (en) * | 1984-08-23 | 1989-07-19 | Fairchild Semiconductor Corporation | A process for forming vias on integrated circuits |
-
1985
- 1985-07-19 GB GB858518231A patent/GB8518231D0/en active Pending
-
1986
- 1986-07-18 GB GB08617654A patent/GB2178896B/en not_active Expired
- 1986-07-18 JP JP61504078A patent/JPS63500346A/en active Pending
- 1986-07-18 WO PCT/GB1986/000424 patent/WO1987000688A1/en not_active Application Discontinuation
- 1986-07-18 EP EP86904308A patent/EP0231242A1/en not_active Withdrawn
Also Published As
Publication number | Publication date |
---|---|
WO1987000688A1 (en) | 1987-01-29 |
GB8617654D0 (en) | 1986-08-28 |
GB2178896A (en) | 1987-02-18 |
EP0231242A1 (en) | 1987-08-12 |
JPS63500346A (en) | 1988-02-04 |
GB2178896B (en) | 1988-11-09 |
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