GB2504308A - Phase locked loop with digital coarse tuning circuit - Google Patents

Abstract

An acquisition circuit for a PLL is provided. The circuit comprises a controlled frequency oscillator 102 having a wide range coarse control and a narrow range fine control; a digital coarse tune circuit 110 including a sample and hold circuit 120, an up/down counter 130 and an inflection detector 140. The PLL circuit also contains an analogue phase comparator 150 and integrator 152 to provide fine tuning. The sample and hold circuit 120 provides two signals 132, 134 to the counter 130 to control counting and count direction. The inflection detector 140 detects when the up/down counter inflects. The fine tuning circuit is configured to be activated when inflection is detected.

Description

IMPROVEMENTS RELATING TO PHASE-LOCK-LOOP SYNTHESISERS

Phase-Lock-Loop (PLL) synthesisers are used in a wide range of radio) telecommunication and computational devices. They are used to generate an output signal of an oscillator that is phase linked to an input "reference" signal.

In order to achieve phase lock the PLL must acquire the correct frequency and, in order to do this, an acquisition circuit may be provided.

According to the present invention there is provided an acquisition circuit for a PLL, the circuit comprising: at least one digital coarse tune device, a sample and hold circuit configured to provide two incremented frequency pulses to the coarse tune device at a rate proportional to the frequency error of the oscillator relative to the reference, the one leading or lagging the other by 90 degrees of phase, an up/down counter configured to be incremented or decremented by the sample and hold circuit, an inflection detect circuit configured to detect when the up/down counter inflects, and a fine tune device which is configured to be activated when inflection is detected.

The proportionality is a natural consequence of the operation of the sample and hold circuit, but is useful in so far as the rate of approach to correct operation is proportional to error, giving an exponential approach, thus minimising transient induced instability in the operation of the oscillator.

The phase relationship indicates whether the oscillator is too slow or too fast with relation to the reference.

It is preferable to provide a fine tune device that has a linear response and is capable of providing accurate matching with the phase of the reference signal. However, if the frequency of the PLL is considerably different from the reference signal, then the phase will vary considerably, at a high frequency, and the fine tune device will not be able to respond to the rapid fluctuations. Therefore, the acquisition circuit of the present invention is additionally provided with a coarse tune device that brings the frequency of the PLL close to the frequency of the reference signal and a clamp to hold the fine tune device whilst the course tune device is active.

The fine tune device may be a phase comparator. The phase comparator has a very small range of control. Over this range, it is very accurate. It is used to make fine adjustments to the signal, especially to the phase of the signal in order accurately to complete the matching with the reference signal.

The acquisition circuit may comprise more than one digital coarse tune device. The provision of a number of separate devices, the outputs of which are weighted and combined provides an improved response in comparison with the response obtainable from a single device. A further benefit of a circuit containing a plurality of coarse tune devices is that such a circuit will have a reduced level of noise in comparison with a circuit with a single device. In some examples, the weighting of one or more of the coarse tune devices may be zero. This enables the coarse tune device or devices with the most relevant frequency response to be used to the exclusion of those with a less optimum frequency response.

The coarse tune device is digital so that there is no additional error creation within the acquisition circuit itself.

The incremented frequency pulses may be configured to comprise a frequency step and a direction.

The frequency step is a "push" of the frequency of the course tune device and the direction is either "up", toa higher frequency) or "down" to a lower frequency.

The sample and hold circuit may further comprise an end of range detector and toggled latch, combined with an XOR gate. This augmentation of the sample and hold circuit is provided in case the frequency of the coarse tune device has deviated from the frequency of the reference signal so such an extent that it has reached the extreme of its frequency range. This would be the consequence of incorrect connection. If this scenario is detected, the toggled latch switches into the opposite condition and this is fed, via the XOR gate, into the direction part of the sample and hold circuit. As a result, the frequency of the signal provided to the coarse tune device drives in the opposite direction.

The acquisition circuit may further comprise a digital to analogue converter provided between the up/down counter and the coarse tune device, having a compressed range, and not monotonic. This converter ensures that all voltage responses are covered and that there are no gaps in the voltage range of the circuit as a whole.

The up/down counter may be further configured to include a reset function configured to reset the counter to its midrange point. Acquisition of the correct frequency is on average more rapid starting from the mid point than starting from either extreme.

The fine tune device may further be configured to be clamped at its midrange point. By clamping at the midrange point, subsequent errors arising from drift of the fine tune device maybe avoided.

The sample and hold circuit may be a master-slave data latch.

The present invention will now be further described, by way of example only, with reference to the accompanying drawing in which: Figure 1 shows one example of the present invention.

An acquisition circuit 100 for a PLL is provided. The circuit 100 comprises a controlled frequency oscillator 102, having a wide range coarse control and a narrow range fine control; a digital coarse tune device 110 including a sample and hold circuit 120, an up/down counter 130, and an inflection detector 140; an analogue fine tune device 150 and an integrator 200.

The sample and hold circuit 120 comprises a pair of D-type flip-flops) which are provided with inputs consisting substantially of a signal derived from the reference frequency 122 and the two outputs 124, 126 from the controlled frequency oscillator 102. There is a 9O phase shift between the two outputs 124, 126 of the controlled frequency oscillator 102.

The sample and hold circuit 120 provides two outputs 132, 134. The first output 132, is effectively a "push" signal and the second output effectively gives a direction (i.e. up/down in the frequency domain) for the "push". The two outputs 132, 134 of the sample and hold circuit are provided to the up/down counter 130. In addition, the two outputs 132, 134 are also provided to the inflection detector 140.

Whilst the coarse tune device 110 is active, the integrator 200 is held, clamped, at its central position. Once the inflection detector 140 detects that the frequency step provided by the sample and hold circuit 120 has changed direction, i.e. an inflection has occurred, the integrator 200 is un-clamped. This indicates that the frequency is close enough for the analogue fine tune device 150 to obtain a lock. The state of the counter 130 will not change further because no further pulses will come from the sample and hold circuit 120.

Clamping integrator 200 at the centre point of the range is advantageous because it gives maximum control and avoids the detrimental effects of drift which can be evident if the fine tune control of the oscillator 102 is activated at one extreme of its range.

The fine tune device 150 is an analogue phase comparator which feeds its output into the PPL integrator 200. A facility for adding an offset can be provided by a differential unity-gain device 152.

An end of range detector and toggled latch 160 are provided. These are configured to receive the output of the up/down counter 130. If the up/down counter 130 is identified to have reached the end of its range, the toggled latch 160 activates to invert the "direction" signal 134 being fed to the up/down counter 130 from the sample and hold circuit 120. The inversion occurs within the XOR gate 162. This ensures that, if the PLL has not acquired a lock and the coarse tune control signal to the oscillator 102 has reached one end of its range, then the counter 130 will then step in the opposite direction in order to try to obtain a lock.

The up/down counter 130 is also provided with a set feature 138 which sets the up/down counter to the mid-point in its range. On average, a lock is more quickly obtained when starting from a mid-point, than when starting from either end of the available range.

The output of the up/down counter 130 is provided to a Digital to Analogue converter 170 before being provided to the coarse tune control signal to the oscillator 102. The converter 170 ensures that all voltage values are covered and that there are no gaps in frequency response.

Claims (6)

1. CLAIMS1. An acquisition circuit for a PLL, the circuit comprising: at least one digital coarse tune device, a sample and hold circuit configured to provide two incremented frequency pulse trains to the coarse tune device at a rate proportional to the frequency error and lead-lag relationship indicating sign of frequency error, an up/down counter configured to be incremented by the sample and hold circuit, an inflection detector configured to detect when the up/down counter inflects, and a fine tune device which is configured to be activated when inflection is detected.
2. 2. The circuit according to claim 1, wherein the fine tune device is a phase comparator.
3. 3. The circuit according to claim 1 or claim 2, wherein there is more than one digital coarse tune device.
4. 4. The circuit according to any one of claims ito 3, wherein the sample and hold circuit further comprises an end of range detector and toggled latch, combined with an XOR gate.
5. 5. The circuit according to any one of claims 1 to 4, further comprising a digital to analogue converter provided between the up/down counter and the coarse tune device.
6. 6. The circuit according to any one of claims ito 5, wherein the sample and hold circuit is a master-slave data latch.