GB2503513A

GB2503513A - A rear contact heterojunction intrinsic thin layer silicon solar cell

Info

Publication number: GB2503513A
Application number: GB1211683.6A
Authority: GB
Inventors: Daniel Nilsen Wright
Original assignee: REC CELLS Pte Ltd
Current assignee: REC CELLS Pte Ltd
Priority date: 2012-06-29
Filing date: 2012-06-29
Publication date: 2014-01-01
Also published as: GB201211683D0

Abstract

A rear contact heterojunction intrinsic thin layer silicon solar cell 1 and fabrication method for such solar cell are proposed, For fabricating the solar cell 1 a thin intrinsic amorphous Si layer 7 is deposited over the entire rear surface of a silicon substrate 3. A first semiconductor layer 13 of a first doping polarity is deposited through a mask. Subsequently, a separation layer 19 of electrically insulating malarial such as silicon nitride is deposited through the same mask such that it covers an entire back surface of the first semiconductor layer 13. Then, a second semiconductor layer 21 is deposited over the entire area of the rear surface of the silicon substrate 3. Finally, metal contacts 39, 41 are formed optionally using a dielectric layer 23 and removable or permanent masking layers 29. The proposed method allows for simple fabrication of HIT solar cells requiring only one mask and enabling high solar cell efficiencies due to p- and n-type-regions being very close to one another.

Description

Method for fabricating a rear contact heterojunction intrinsic thin layer silicon solar cell with only one masking step and respective solar cell

FIELD OF THE INVENTION

The present invention relates to a rear contact heterojunction intrinsic thin layer silicon solar cell and a method for fabricating such solar cell.

TECHNICAL BACKGROUND

Solar cells are used to convert sunlight into electricity using a photovoltaic effect. A * * 20 general object is to achievc high conversion efficiency balanced by a need for low production costs.

In order to obtain high efficiency, semiconductor materials of good quality should be used as substrates for the solar cell and the surfaces of the substrates should be highly passivated *.25 in order to minimize any recombination losses. Furthermore, contact schemes for electrically contacting the substrate should be optimized in order to minimize resistance losses and optical shading.

Iii order to keep production costs low, it is generally intended to use as few processing steps as possible and furthermore to prevent complicated and costs-intensive production steps such as e.g. photolithography masking and high temperature processing steps.

A solar cell concept has been proposed in WO 03/083955 Al. Therein, a rear-junction type photovoltaic element is proposed in which a pn junction and electrodes are formed on a rear surface opposite to a light incident surface of a semiconductor silicon substrate. The photovoltaic element has an intrinsic semiconductor film on its rear side having a thickness ranging from 0.1 nm to 50 nm. On the back side of the intrinsic semiconductor film, p-type conductive semiconductor portions and ntype conductive semiconductor portions are disposed and each of the conductive semiconductor portions is contacted with a respective first or second electrode. Such interdigitated back contact heterojunction intrinsic-thin film solar cell is sometimes referred to as IBC HIT solar cell.

Several attempts to improve this solar cell concept and methods for fabricating such solar cells have been proposed. Therein, the fabricating methods comprise several processing steps inter alia including different approaches for passivating the substrate surface, defining the geometry of the various semiconductor electrode ayers and insulator layers andJor applying electrical electrodes to the solar cell substrate. For example, it has been S proposed to use expensive photolithography processing steps to precisely define areas of S.....

* semiconductor layers andlor insulator layers on the substrat's rear surface. Furthermore, it has been proposed to locally remove previously deposited layers by locally etching in order to subsequently deposit other layer materials in the prepared openings thereby generating a desired geometry of a rear side layer arrangement. * ..* * . *..

*. In UK patent application GB 1111 302.4 and associated PCT application PCTIEP2O12/002274, an improved concept for a HIT solar cell and its fabrication have been proposed. Many details on possible method features as well as possible structural or ftmctional fcaturcs of the solar cell are presented. These applications are assigned to the same applicant as the present application and shall be incorporated herein in their entirety by reference.

However, it seems that many conventional approaches for generating a rear contact heterojunction intrinsic thin film solar cell scheme may suffer from at least one of the following shortcomings: -a lack of a cheap mass-production method -poor passivation at electrode edges due to imperfect definition of electrode areas -a risk of shunting forcing metallization only over a limited part of the electrodes -difficulties in controlling the cleanness and deposition homogeneity of the intrinsic thin film in the critical layer closest to the substrate -expensive layer geometry definition due to the use of lithography and/or use of multiple masks.

SUMMARY OF THE INVENTION

It is an object of the present invention to at least partially overcome shortcomings of the above-mentioned prior art approaches. Particularly, it may be an object of the present invention to provide a rear contact heterojunction intrinsic thin layer solar cell and a * ** * method for fabricating such solar cell allowing high solar cell efficiency while using a relatively simple and cost-efficient fabrication processing sequence. Furthermore, it may * 15 be seen as an object of the present invention to refine the solar cell and fabrication approach presented in. co-assigned GB 1111 302.4 and PCT/EP2012/002274.

Such objects may be achieved with the subject-matter of the independent claims.

Advantageous embodiments are defined in the dependent claims.

According to a first aspect of the present invention, a method for fabricating a rear contacted heterojunction intrinsic thin layer solar cell is proposed. Therein, the rear side is formed by at least the following process steps, preferably in the indicated order: -providing a silicon substrate with a front surface and a rear surface; -depositing a thin layer of i-a-Si as a blanket deposition over the entire rear surface of the silicon substrate, the i-a-Si layer having a front surface adjacent to the rear surface of the silicon substrate and having a back surface opposite to the front surface; -depositing a first semiconductor layer comprising a doped semiconducting material such as a-Si of a first doping polarity wherein the first semiconductor layer is deposited through a mask such that it covers first portions of the back surface of the i-a-Si layer; -depositing a separation layer comprising an electrically insulating material such as preferably silicon nitride (SiN) or i-a-Si or another dielectric material, wherein the * separation layer is deposited through the mask such that it covers at least an entire back surface of the first semiconductor layer; and -depositing a second scmiconductor layer comprising a doped semiconducting material such as a-Si of a second doping polarity opposite to the first doping polarity wherein the second semiconductor layer is deposited as a blanket deposition over the entire area of the rear surface of the silicon substrate.

Therein, using only one single mask, the first semiconductor layer, the second * :* semiconductor layer and the separation layer are arranged and deposited such that the * * separation layer separates the first semiconductor layer from the second semiconductor *:*::* layer. * S. S

* According to a second aspect of the present invention, a rear contact heterojunclion solar **..

* 20 cell is proposed compnslng *. * -a silicon substrate with a front surface and a rear surface; -a passivating layer at the front surface of the silicon substrate; -a thin i-a-Si layer covering the entire rear surface of the substrate, the i-a-Si layer having a front surface adjacent to the rear surface of the silicon substrate and having a back surface opposite to the front surface; -a first semiconductor layer comprising a doped semiconductirig material of a first doping polarity and covering first portions of the back surface of the i-a-Si layer; -a second semiconductor layer comprising a doped semiconducting material of a second doping polarity opposite to the first doping polarity and covering the entire area of the rear surface of the silicon substrate, and -a separation layer comprising an electrically insulating material and covering the S entire area of the rear surface of the silicon substrate and being arranged between the first semiconductor layer and the second semiconductor layer for separating the first semiconductor layer from the second semiconductor layer.

A gist of the present invention and its embodiments maybe seen as based on the following ideas and recognitions: A concept for a HIT solar cell and its fabrication has been described in GB 1111 302.4 and PCTIEP2OI2/002274. Embodiments of the invention described herein aim at further simplifying a processing sequence for fabricating a rear contact HIT solar cell and further * i5 increasing its efficiency. * .

* ** Like in other HIT solar cell concepts, a thin i-a-Si layer is deposited on top of a rear surface of a silicon substrate. On top of the back surface of this thin i-a-Si layer, first and second semiconductor layers are deposited in areas neighbouring each other and possibly partly laterally overlapping each other. The first and second semiconductor layers may be S...

* doped a-Si layers and have opposite doping polarities.

In the prior application documents mentioned above, it is taught to separate such first and second semiconductor layers from each other by an intennediate separation layer which is deposited before each of the first and second semiconductor layer is deposited. Therein, each of the separation layer, the first semiconductor layer and the second semiconductor layer is deposited through a mask. Accordingly, three masking steps were necessary.

Furthermore, minimum lateral dimensions of each of the layers were predetermined by the technical feasibility of minimum dimensions of openings provided in the various masks.

For example, such minimum dimensions are in the range of at least several micrometers, for example more than 10 urn. Furthermore, when very small openings are to be used, the mask should be very thin, e.g. about or less than lOOpim thick, in order to prevent shadowing and aspect-ratio problems. Such thin masks are however difficult to handle and durability may be short. Finally, using three separate masks requires very precise alignment of all these masks.

In contrast hereto, the method for fabricating a rear contact HIT solar cell proposed herein requires only one single masking step for depositing each of the first semiconductor layer, the second semiconductor layer and a separation layer for electrically separating these first and second semiconductor layers from each other. Accordingly, the proposed fabrication method possesses a self-alignment nature thereby simplifying the fabrication procedure and avoiding any risks in correlation with misalignments during masked depositing the various layers.

In thc proposed method, first, a thin i-a-Si layer is deposited over the entire rear surface of the silicon substrate. Due to such blanket deposition, the entire rear surface of the silicon * * substrate is highly passivated. * ** * * .

Then, in preparation for generating the first semiconductor layer and the separation layer onto partial areas of the back surface of the i-a-Si layer, a mask is applied above the rear * . surface of the silicon substrate. This mask comprises openings in first regions. Through : . these openings, material may be deposited onto associated portions of the back surface of the i-a-Si layer. The first semiconductor layer may be a doped a-Si layer which may serve as an emitter layer or a base layer in the final solar cell.

In order to electrically isolate the first semiconductor layer from any neighbouring or overlapping semiconductor layers, a separation layer of an electrically insulating material is deposited on top of the back surface of the first semiconductor layer. The electrically insulating material is preferable silicon nitride (SiN) or silicon oxide (SiO) as these dielectrics are highly isolating and ftirthermore have advantageous etching characteristics which may beused during metal contact formation as described further below.

Alternatively, other insulating materials such as i-a-Si or silicon carbide may be used.

The separation layer is deposited using the same mask as used for depositing the underlying first semiconductor layer. Consequently, due to the involved self-alignment, the separation layer covers and electrically isolates the entire back surface of the first semiconductor layer.

Subsequently, the mask may be removed and a second semiconductor layer of opposite polarity is deposited over the entire area of the rear surface of the silicon substrate including the back surface of the underlying separation layer and the underlying first semiconductor layer deposited previously. As this second semiconductor layer is deposited over the entire area of the rear surface of the silicon substrate without using any mask, this second semiconductor layer comes into direct contact with the underlying i-a-Si layer in :15 second portions where no first semiconductor layer and separation layer has been deposited previously. Furthermore, in the first portions of the rear surface of the silicon substrate, this second semiconductor layer laterally overlaps and covers the underlying first s. semiconductor layer from which it is electrically isolated by the intermediate separation Accordingly, using only one mask, an interdigitated structure with first portions comprising a first semiconductor layer and second portions comprising a second semiconductor layer maybe generated wherein, due to the self-aligning nature of the deposition of the separation layer, reliable electrical separation of these two semiconductor layers may be achieved.

Furthermore, while in prior art approaches first and second semiconductor layers were separated from each other by an intermediate separation layer the lateral dimension of which was predetermined by the masking techniques used for depositing such separation layer and was in the range of at least several micrometers, according to the approach described herein, the first and second semiconductor layers may be separated from each other by the intermediate separation layer. Accordingly, a separation distance between the first and second semiconductor layer is given by the thickness of the separation layer. With conventional deposition techniques, a separation layer having a thickness of only a few nanometers may be deposited. It has been observed that depositing the first separation layer with a thickness of between 1 and l000nm, preferably between 3 and 300nm and more preferably between 10 and lOOnm may be sufficient for reliably electrically insulating the adjacent first and second semiconductor layers from each other.

Enabling the first and second semiconductor layers to be separated from each other only by a thin intermediate isolating layer, i.e. being very close to one another, has been observed to be beneficial for the efficiency of the resulting solar cell, particularly for increasing its fill factor.

According to an embodiment of the present invention, the process of depositing the first separation layer is performed with a less directional deposition technique than the process *. . of depositing the first semiconductor layer.

* I S I S 4 5 * In other words, when depositing the first semiconductor layer through the mask, process parameters are adapted such that material for forming the first semiconductor layer is transmitted through the mask in a predetermined main deposition direction, for example 4 * ** * orthogonal to the plane of the mask, and deviations from such main deposition direction * are small. Accordingly, an area and geometry of the resulting first semiconductor layer generally corresponds to an area and geometry of an opening in the first mask.

Subsequently, the first separation layer is deposited on top of the first semiconductor layer with a significantly smaller directionality, i.e. deviations from a main deposition direction may be larger. Accordingly, an area of the first separation layer may be slightly larger than an area of a respective opening in the first mask and tails of the first separation layer may extend laterally beyond edges of the underlying first semiconductor layer.

The presence of such lateral tails may further ensure that the separation layer reliably covers the entire underlying first semiconductor layer and prevents any portions of the first semiconductor layer to remain exposed, thereby preventing any electrical contact with adjacent or overlapping neighbouring semiconductor layers.

A directionality of a depositing process may be influenced for example during PECVD S deposition by operating pressure, temperature and substrate bias. For example, decreasing the operating temperature, increasing the pressure andlor increasing the DC bias on the substrate is assumed to increase directionality of the deposition process.

Due to the self-aligning nature of the processes of depositing the first semiconductor layer and depositing the separation layer within the fir st pQrtiofls of the back surface of the i-a-Si layer, these two processes may be performed using a non-contacting mask. In other words, the mask used for depositing the first semiconductor layer and the separation layer does not need to be arranged in direct mechanical contact to the silicon substrate but there may be a gap between such mask and the surface of the silicon substrate. While such gap may result in the deposited layers having enlarged lateral tail regions, i.e. having fuzzy edges, such enlarged tail regions may be accepted as the separation layer is self-aligned on top of the * * first semiconductor layer and any tail region of the first semiconductor layer is covered by a corresponding tail region of the separation layer. Using a non-contacting mask may reduce any risk of surface contamination and damage to the surface of the silicon substrate. S..

*,* Additionally to depositing the first semiconductor layer, the separation layer and the -second semiconductor layer, the proposed method may further comprise depositing a dielectric layer after the step of depositing the second semiconductor layer. This dielectric layer may be deposited as a blanket deposition over the entire area of the rear surface of the silicon substrate on top of the second semiconductor layer and therefore does not require any mask. Such additional dielectric layer may be beneficially used for example during subsequent metal contact formation and may serve for isolating overlying metal contacts from the second semiconductor layer. Due to advantageous etching characteristics, silicon nitride or silicon oxide are preferred insulating materials for this dielectric layer. Furthermore, when using low refractive index materials, such as SiN and -10 -SiO, this second separation layer may increase the back reflection of transmitted light in regions where it resides after metal contact formation.

After depositing such additional dielectric layer, the proposed method may comprise several further processing steps for forming metal contacts.

For example, a removable masking layer having openings at locations corresponding to the first portions of the back surface of the i-a-Si layer may be deposited and the second semiconductor layer and the dielectric layer may be locally removed by etching holes into these layers at the openings not protected by the removable masking layer. Subsequently, the removable masking layer is removed before then depositing a permanent masking layer which may remain onto the silicon substrate and may serve for example as a back reflecting layer for the finalized solar cell. The permanent masking layer has first openings at locations corresponding to the first portions of the back surface of the i-a-Si layer and . :15 furthermore has second openings at locations corresponding to adjacent second portions of * the back surface of the i-a-Si layer. Using such permanent masking layer, the separation * layer is locally removed by etching first holes at the first opening not protected by the permanent masking layer and the dielectric layer is locally removed by etching second * holes at the second openings not protected by the permanent masking layer. Finally, metal contacts are applied at the first and second portions of the back surface of the i-a-Si layer for separately electrically contacting the first and the second semiconductor layers through the first and second holes, respectively.

Using such approach of first depositing a removable masking layer and etching holes only at the first portions of the back surface of the i-a-Si layer but not at the second portions and then removing this removable masking layer and applying a permanent masking layer with which first holes at the first portions as well as second holes at the second portions are etched may be beneficially used for generating metal contacts contacting the first and second semiconductor layers through the associated first and second holes.

Particularly, when the first and second semiconductor layers are made with a-Si and both the separation layer deposited in between the first and second semiconductor layer as well as the dielectric layer deposited on top of the second semiconductor layer are made with specific dielectric materials, the first and second holes may be generated using selective etching. Therein, the first holes in the separation layer are etched with an etchant which does not etch the underlying first semiconductor layer and the second holes in the dielectric layer are etched with an etchant which does not etch the underlying second semiconductor layer.

For example, when the separation layer as well as the dielectric layer are made with silicon nitride or silicon oxide, first, these layers may be locally removed using hydrofluoric acid (HF) which does not etch the underlying doped a-Si layer. Subsequently, this a-Si layer may be locally etched using potassium hydroxide (KOH) which does not etch an underlying silicon nitride or silicon oxide layer. Accordingly, using such selective etching approach, holes may be created within the respective dielectric layers and semiconductor layers without risking any damage to underlying further layers. * .

* : ::* It may be noted that possible features and advantages of embodiments of the present *:. invention are described herein with respect to the proposed rear contact heterojunction solar cell or with respect to the proposed method for fabricating such solar cell. One skilled * .* * *.. in the art will recognize that the different features may be suitably combined and features *. of the solar cell may be realized in a corresponding maimer in the fabricating method and vice versa in order to implement further advantageous embodiments and realize synergetic effects.

BRIEF DESCRIPTION OF THE DRAWINGS

In the following, features and advantages of embodiments of the present invention will be described with respect to the enclosed drawings. Therein, neither the description nor the drawings shall be interpreted as limiting the invention. -12-

Figs. 1(a) (i) illustrates a processing sequence of a method for fabricating a HIT solar ccli according to an embodiment of the present invention.

The figures are only schematically and not to scale. Same or similar features are designated with same reference signs throughout the figures.

DESCRIPTION OF PREFERRED EMBODIMENTS

With reference to Figs. I, an embodiment of a processing sequence according to the present invention for fabricating a rear contacted heterojunction intrinsic thin layer solar ccli will be described.

It shall be noted that the illustrated sequence is mainly used for explaining the processing steps relevant for an exemplary embodiment of the inventive method. One skilled in the art realizes that further processing steps may be added or some of the described processing i 5 steps may be replaced by equivalent processing steps for fabricating the solar cell. * .

* Particularly, it shall be noted that in the described processing sequences, any suitable processing means and techniques may be applied such as, inter alia, those described in *. * * detail in GB 1111 302.4 and PCTIEP2O12/002274. * S...

*: * As shown in Fig. 1, first an n-type silicon wafer is provided as a silicon substrate 3 (Fig. * 1(a)). On a front surface of this silicon substrate 3, a passivating layer 6 is deposited. This passivating layer 6 may additionally serve as an antireflection coating and may be made for example with a dielectric material such as silicon nitride or silicon oxide. A rear surface 5 of the silicon substrate is thoroughly cleaned.

Subsequently, a thin intrinsic amorphous silicon layer 7 having a thickness of e.g. less than run is deposited on a rear surface 5 of the silicon substrate 3 (Fig. 1(b)). The i-a-Si layer 7 is deposited in a single deposition step as a blanket layer and covers the entire rear surface 5 of the silicon substrate 3. The thickness is selected to be, on the one hand, -13 -sufficiently thick for good passivation of the underlying silicon substrate (3) rear surface (5) and, on the other hand, thin enough for charge carriers to tunnel through such thin layer.

Then, a first semiconductor layer 13 such as e.g. a p-type-doped amorphous silicon layer is deposited through a mask 11 (Fig. 1(c)). This mask 11 has openings 12 and the deposition process is performed with high directionality such that deposition takes place mainly at first portions 15 of the back surface 9 of the i-a-Si layer 7 such first portions mainly coinciding with the areas of the openings 12 in the fir st mask 11.

Subsequently, a first separation layer 19 is deposited on top of the previously deposited first semiconductor layer portions 13 while the mask 11 remaining at the position as used during depositing the first semiconductor layer 13 (Fig. 1(d)). The separation layer comprises an electrically insulating material. Preferably, the separation layer consists of a :15 dielectric material which may be etch e.g. in hydrofluoric acid (HF). For example, the * separation layer 19 comprises silicon nitride, silicon oxide, silicon carbide, etc and maybe * deposited using e.g. PECVD (plasma enhanced chemical vapour deposition) techniques.

*:c: The separation layer 19 is deposited with a thickness of between 50 arid 300nm. * *

While both the first semiconductor layer 13 and the separation layer 19 are deposited using the same first mask 11, deposition parameters influencing a directionality of a deposition process may be different. When the first semiconductor layer 13 is deposited, a higher directionality is desired in order to keep any tails 14 at the edges of the first semiconductor layer portions 13 as small as possible. Such high directionality may be achieved by adjusting parameters such as pressure, substrate temperature and substrate bias. When depositing the separation layer 19, less directionality is desired such that tails 20 of the separation layer 19 may reach laterally relatively far beyond the edges of the openings 12 in the first mask 11. Accordingly, the separation layer 19 including these tails 20 completely covers and isolates the underlying first semiconductor layer 13 including its tails 14. -14-

Subsequently, the mask 11 is removed and a blanket layer of n-type-doped amorphous silicon is deposited as a second semiconductor layer 21 over the entire rear surface 7 of the silicon substrate 3 (Fig. 1(e)). This blanket second semiconductor layer 21 covers both the back surface of the separation layer 19 in the first portions 15 and adjacent tails 20 as well as the exposed back surface 9 of the blanket thin i-a-Si layer 7 in neighbouring second portions 33.

Subsequently, a dielectric layer 23 is deposited over the entire area of the rear surface 5 of the silicon substrate 3 (Fig. 1W)). This dielectric layer 23 preferably comprises a dielectric material etchable in HF such as e.g. silicon nitride or silicon oxide.

After having formed the first and second semiconductor layers 13, 21 and the separating layer 19 and the dielectric layer 23, metal contacts are formed for electrically contacting both the first and second dielectric layers 13, 21. As illustrated in Figs. 1(g) to (i), such :15 formation of locally contacting electrodes may comprise two masking steps and may * beneficially use selective etching for generating holes within the various layers 19, 21, 23 * Oae* * in order to locally expose the respective semiconductor layers 13, 21. * ** * a * **

*:. First, a removable masking layer 25 having openings 27a at the first portions 15 of the back surface 9 of the i-a-Si layer 7 is applied. Such removable masking layer 25 may be * applied using e.g. patterned screen printing technology or using a peelable layer, e.g. ** * polyimide or an adhesive layer. At the openings 27a an etching solution such as hydrofluoric acid may get into contact with the underlying dielectric layer 23. This dielectric layer 23 made of e.g. silicon nitride is etched by the hydrofluoric acid. The etching process stops at the surface of the underlying a-Si second semiconductor layer 21 which is resistant to HF. Subsequently, this second semiconductor layer 21 is etched in a KOH etchant wherein the etching process stops at the surface of the underlying silicon nitride separation layer 19. As a result of such 2-step etching process, holes 34 are generated in the second semiconductor layer 21 and the dielectric layer 23 at the openings 27a of the removable masking layer 25. The removable masking layer 25 may then be removed.

Subsequently, a permanent masking layer 29 is applied (Fig. (h)). This permanent masking layer 29 has first openings 27b at the first portions 15 of the back surface 9 of the i-a-Si layer 7 which are arranged at the same positions as the openings 27a of the removable masking layer 25. The permanent masking layer 29 additionally has second openings 31 at adjacent second portions 33. In a subsequent etching step using hydrofluoric acid, the separation layer 19 is locally removed at the bottom of the etched holes 34 generated in the preceding etching step thereby forming deeper holes 35 at the bottom of which the first semiconductor layer 13 is locally exposed. Additionally, the dielectric layer 23 is locally removed by etching second holes 37 at the second openings 31 of the permanent masking layer 29.

In a final processing step, metal contacts 39,41 are applied. Therein, a first type of metal contacts 39 is generated for forming electrical contact to the first semiconductor layer 13 and a second type of metal contact 41 is generated for forming electrical contact to the second semiconductor layer 21. Both metal contact types 39,41 may be generated by S.....

* * blanket metal deposition and subsequent laser separation wherein the permanent masking layer 29 may serve as a buffer layer. Alternatively, the metal contact types 39, 41 may be applied using patterned deposition such as masked metal deposition or screen printing technology.

* ** * * * *.** Summarizing, a simplified way of processing of an interdigitated back contact HIT silicon solar cell 1 enabling a very narrow gap between doped semiconductor regions 13,21 for increased efficiency is presented. After a blanket i-a-Si layer 7 has been deposited on the rear surface of a silicon substrate 3, a masked deposition of an emitter (or base) semiconductor layer 13 is concluded by a deposition of an HF removable dielectric such as silicon nitride serving as a separation layer 19. Then a blanket deposition of a base (or emitter) semiconductor layer 21 is made also concluded by a deposition of a same type of HF removable dielectric 23. Then, a first removable etch mask 25 is applied to remove the top dielectric layer 23 and the base (emitter) layer 21 where the emitter (base) contacts 39 are required. This is made possible by the etching selectivity between a-Si and silicon -16-nitride as a-Si is resistant to HF while silicon nitride is resistant to KOH. Then a permanent etch mask 29 is applied to open holes 35, 37 both for base and emitter contacts 39, 41.

With the proposed fabrication method, only one mask 11 is required for forming the pattern of first and second semiconductor layersl3, 21. Such mask 11 may be used for example in a masked PECVD step.

An important feature of the proposed fabrication method and solar cell 1 is the provision of a thin dielectric separation layer 19 to electrically isolate any a-and p-a-Si regions that may overlap. This separation layer 19 also enables the p-and n-regions to be very close to one another which has been shown to increase especially the fill factor of a resulting solar cell.

Finally, it should be noted that the term "comprising" does not exclude other elements or steps and the "a" or "an" does not exclude a plurality. Also elements described in * association with different embodiments may be combined. It should also be noted that *: * reference signs in the claims should not be construed as limiting the scope of the claims. * * * S * * ** * *** ** * * * * . * ** 0 * 0'* -17-

LIST OF REFERENCE SIGNS

1 solar cell 3 silicon substrate rear surface of silicon substrate 6 passivating layer on front surface of silicon substrate 7 intrinsic amorphous silicon (i-a-Si) layer 9 back surface of i-a-Si layer 11 mask 13 first semiconductor layer first portions 17 back surface of the first semiconductor layer 19 separation layer 21 second semiconductor layer 23 dielectric layer * 25 removable mask layer * 27a openings in removable mask layer * 27b first openings hi permanent mask layer 20 29 permanent mask layer 31 second openings in permanent mask layer 33 secondportions holes at first openings 37 holes at second openings 39, 41 metal contacts -18-

Claims

CLAIMS1. A method for fabricating a rear contacted heterojunction intrinsic thin layer solar cell (1) wherein the rear side is formed by at least: -providing a silicon substrate (3) with a front surface and a rear surface (5); -depositing a thin layer (7) of i-a-Si as a blanket deposition over the entire rear surface (5) of the silicon substrate (3), the i-a-Si layer (7) having a front surface adjacent to the rear surface (5) of the silicon substrate (3) and having a back surface (9) opposite to the front surface; -depositing a first semiconductor layer (13) comprising a doped semiconducting material of a first doping polarity wherein the first semiconductor layer (13) is deposited through a mask (11) such that it covers first portions (15) of the back surface (9) of the i-a-Si layer (7); -depositing a separation layer (19) comprising an electrically insulating material wherein * * the separation layer (19) is deposited through the mask (11) such that it covers at least an entire back surface (17) of the first semiconductor layer (13); * -depositing a second semiconductor layer (21) comprising a doped semiconducting r 20 material of a second doping polarity opposite to the first doping polarity wherein the second semiconductor layer (21) is dcposited as a blanket deposition over the entire area of the rear surface (5) of the silicon substrate (3), such that the separation layer (19) separates the first semiconductor layer (13) from the second semiconduôtor layer (21).
2. The method of claim 1, wherein the process of depositing the separation layer (19) is performed with a less directional deposition technique than the process of depositing the first semiconductor layer (13). -19-
3. The method of claim 1 or 2, wherein the separation layer (19) has a thickness of between 1 and l000nm.
4. The method of one of claims ito 3, wherein the separation layer (19) comprises at least one of silicon nitride, silicon oxide, i-a-Si and silicon carbide.
5. The method of one of claims 1 to 4, wherein the process of depositing the first semiconductor layer (13) and the process of depositing the separation layer (19) is performed using a non-contacting mask (11).
6. The method of one of claims ito 5, further comprising the following step after the deposition of the second semiconductor layer (21): depositing a dielectric layer (23) wherein the dielectric layer (23) is deposited as a blanket deposition over the entire area of the rear surface (5) of the silicon substrate (3) on top of S the second semiconductor layer (21).
* **.** * * * : : : The method of claim 6, thrther comprising the following steps after the deposition of the dielectric layer (23): depositing a removable masking layer (25) having openings (27a) at the first portions (15) of the back surface (9) of the i-a-Si layer (7), and * : * removing the second semiconductor layer (21) and the dielectric layer (23) by etching holes (34) in these layers (21,23) at the openings (27a) not protected by the removable masking layer (25), and subsequently removing the removable masking layer (25); and depositing a permanent masking layer (29) having first openings (27b) at the first portions (15) of the back surface (9) of the i-a-Si layer (7) and having second openings (31) at adjacent second portions (33) of the back surface (9) of the i-a-Si layer (7), and removing the separation layer (19) by etching first holes (35) at the first openings (27b) not protected by the permanent masking layer (29), and -20 -removing the dielectric layer (23) by etching second holes (37) at the second openings (31) not protected by the permanent masking layer (29), and applying metal contacts (39, 41) at the first and second portions (15, 33) for separately electrically contacting the first semiconductor layer (13) and the second semiconductor layer (21) through the first holes (35) and the second holes (37), respectively.
8. The method of claim 7, wherein the first and second holes (35, 37) are generated using selective etching wherein the first holes (35) in the separation layer (19) are etched with an etchant which does not etch the underlying first semiconductor layer (13) and wherein the second holes (37) in the dielectric layer (23) are etched with an etchant which does not etch the underlying second semiconductor layer (23).
9. A rear contacted heterojunction intrinsic thin layer solar cell (1) comprising: * . fl 5 -a silicon substrate (3) with a front surface and a rear surface (5); * : ** -a passivating layer (6) at the front surface of the silicon substrate (3); -a thin i-a-Si layer (7) covering the entire rear surface (5) of the substrate (3), the i-a-Si layer (7) having a front surface adjacent to the rear surface (5) of the silicon substrate (3) : and having a back surface (9) oppsite to the front surface; * 20 -a first semiconductor layer (13) comprising a doped semiconducting material of a first eec.*: doping polarity and covering first portions (15) of the back surface (9) of the i-a-Si layer (7); -a second semiconductor layer (21) comprising a doped semiconducting material of a second doping polarity opposite to the first doping polarity and covering the entire area of the rear surface (5) of the silicon substrate (3), -a separation layer (9) comprising an electrically insulating material and covering the entire area of the rear surface (5) of the silicon substrate (3) and being arranged between the first semiconductor layer (13) and the second semiconductor layer (21) for separating the first semiconductor layer (13) from the second semiconductor layer (21). -21 -
10. The solar cell of claim 9, wherein the separation layer (9) has a thickness of between 1 and 1000nm. * . * * *. * * * ** * * . * *. * * * a a... *. a * a.